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Commit dd864226 by Ravi Varadarajan
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Updated scripts for genus iSpatial flow; add qrc tech file for NG45; update… 

Updated scripts for genus iSpatial flow; add qrc tech file for NG45; update floorplan def to have row definitions

Signed-off-by: Ravi Varadarajan <rvaradarajan@ucsd.edu>
parent 02644d9d
Showing with 301 additions and 105 deletions
Flows/NanGate45/ariane133/def/ariane133_fp_rows.def 0 → 100644
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Flows/NanGate45/ariane133/scripts/cadence/design_setup.tcl
......@@ -5,7 +5,7 @@ set DESIGN ariane
set sdc ../../constraints/${DESIGN}.sdc
# def file with die size and placed IO pins
set floorplan_def ../../def/ariane133_fp.def
set floorplan_def ../../def/ariane133_fp_rows.def
#
# Effort level during optimization in syn_generic -physical (or called generic) stage
# possible values are : high, medium or low
......
Flows/NanGate45/ariane133/scripts/cadence/lib_setup.tcl
......@@ -4,6 +4,7 @@
set libdir "../../../../../Enablements/NanGate45/lib"
set lefdir "../../../../../Enablements/NanGate45/lef"
set qrcdir "../../../../../Enablements/NanGate45/qrc"
set_db init_lib_search_path { \
${libdir} \
......@@ -29,10 +30,9 @@ set lefs "
${lefdir}/fakeram45_256x16.lef \
${lefdir}/fakeram45_256x64.lef \
"
set qrc_max "${qrcdir}/NG45.tch"
set qrc_min "${qrcdir}/NG45.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
#set qrc_max "SigCmax/qrcTechFile"
#set qrc_min "SigCmin/qrcTechFile"
Flows/NanGate45/ariane133/scripts/cadence/mmmc_iSpatial_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
#create_opcond -name op_cond_wc -process 1.0 -voltage 0.72 -temperature 125
#create_opcond -name op_cond_bc -process 1.0 -voltage 0.88 -temperature -40
create_timing_condition -name timing_wc -library_sets { WC_LIB }
create_timing_condition -name timing_bc -library_sets { BC_LIB }
create_rc_corner -name Cmax -qrc_tech $qrc_max
create_rc_corner -name Cmin -qrc_tech $qrc_min
create_delay_corner -name WC -early_timing_condition { timing_wc } \
-late_timing_condition { timing_wc } \
-early_rc_corner Cmax \
-late_rc_corner Cmax
create_delay_corner -name BC -early_timing_condition { timing_bc } \
-late_timing_condition { timing_bc } \
-early_rc_corner Cmin \
-late_rc_corner Cmin
create_constraint_mode -name CON -sdc_file $sdc
create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
set_analysis_view -setup WC_VIEW -hold BC_VIEW
Flows/NanGate45/ariane133/scripts/cadence/run.sh
......@@ -7,5 +7,5 @@ module unload innovus
module load innovus/21.1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
#innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
Flows/NanGate45/ariane133/scripts/cadence/run_genus_iSpatial.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
read_mmmc mmmc_iSpatial_setup.tcl
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
read_physical -lefs $lefs
# Target library
set link_library $list_lib
set target_library $list_lib
# set path
set_db auto_ungroup none
#set_db library $list_lib
#################################################
# Load Design and Initialize
#################################################
source rtl_list.tcl
foreach rtl_file $rtl_all {
read_hdl -sv $rtl_file
}
elaborate $DESIGN
time_info Elaboration
#read_sdc $sdc
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
###############################################
# Read DEF
###############################################
read_def $floorplan_def
check_floorplan -detailed
# keep hierarchy during synthesis
set_db auto_ungroup none
syn_generic -physical
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
syn_map -physical
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
syn_opt -spatial
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
#write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
#write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exit
Flows/NanGate45/ariane133/scripts/cadence/run_invs.tcl
......@@ -73,40 +73,14 @@ createPinBlkg -name side_top -edge 1
createPinBlkg -name side_right -edge 2
createPinBlkg -name side_bottom -edge 3
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setNanoRouteMode -routeTopRoutingLayer 10
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
#setPlaceMode -placeIoPins true
setDesignMode -topRoutingLayer 10
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
## Creating Pin Blcokage for lower and upper pin layers ##
createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
createPinBlkg -name Layer_2 -edge 1
createPinBlkg -name Layer_3 -edge 2
createPinBlkg -name Layer_4 -edge 3
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setNanoRouteMode -routeTopRoutingLayer 10
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
setPlaceMode -placeIoPins true
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
defOut -netlist -floorplan ${DESIGN}_placed.def
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
......@@ -121,12 +95,10 @@ set_clock_propagation propagated
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
setNanoRouteMode -routeTopRoutingLayer 10
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
setNanoRouteMode -routeUseAutoVia true
##Recommended by lib owners
# Prevent router modifying M1 pins shapes
......@@ -135,7 +107,6 @@ setNanoRouteMode -routeWithViaOnlyForStandardCellPin "1:1"
## limit VIAs to ongrid only for VIA1 (S1)
setNanoRouteMode -drouteOnGridOnly "via 1:1"
setNanoRouteMode -dbCheckRule true
setNanoRouteMode -drouteAutoStop false
setNanoRouteMode -drouteExpAdvancedMarFix true
setNanoRouteMode -routeExpAdvancedTechnology true
......@@ -143,24 +114,11 @@ setNanoRouteMode -routeExpAdvancedTechnology true
#SM suggestion for solving long extraction runtime during GR
setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
defOut -netlist -floorplan -routing ${DESIGN}_route.def
setDelayCalMode -reset
setDelayCalMode -SIAware true
setExtractRCMode -engine postRoute -coupled true -tQuantusForPostRoute false
setAnalysisMode -analysisType onChipVariation -cppr both
# routeOpt
#optDesign -postRoute -setup -hold -prefix postRoute -expandedViews
#extractRC
deselectAll
selectNet -clock
reportSelect > summaryReport/clock_net_length.post_route
deselectAll
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
......
Flows/NanGate45/ariane136/def/ariane136_fp_rows.def 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/NanGate45/ariane136/scripts/cadence/design_setup.tcl
......@@ -5,7 +5,7 @@ set DESIGN ariane
set sdc ../../constraints/${DESIGN}.sdc
# def file with die size and placed IO pins
set floorplan_def ../../def/ariane136_fp.def
set floorplan_def ../../def/ariane136_fp_rows.def
#
# Effort level during optimization in syn_generic -physical (or called generic) stage
# possible values are : high, medium or low
......
Flows/NanGate45/ariane136/scripts/cadence/lib_setup.tcl
......@@ -4,6 +4,7 @@
set libdir "../../../../../Enablements/NanGate45/lib"
set lefdir "../../../../../Enablements/NanGate45/lef"
set qrcdir "../../../../../Enablements/NanGate45/qrc"
set_db init_lib_search_path { \
${libdir} \
......@@ -29,10 +30,9 @@ set lefs "
${lefdir}/fakeram45_256x16.lef \
${lefdir}/fakeram45_256x64.lef \
"
set qrc_max "${qrcdir}/NG45.tch"
set qrc_min "${qrcdir}/NG45.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
#set qrc_max "SigCmax/qrcTechFile"
#set qrc_min "SigCmin/qrcTechFile"
Flows/NanGate45/ariane136/scripts/cadence/mmmc_iSpatial_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
#create_opcond -name op_cond_wc -process 1.0 -voltage 0.72 -temperature 125
#create_opcond -name op_cond_bc -process 1.0 -voltage 0.88 -temperature -40
create_timing_condition -name timing_wc -library_sets { WC_LIB }
create_timing_condition -name timing_bc -library_sets { BC_LIB }
create_rc_corner -name Cmax -qrc_tech $qrc_max
create_rc_corner -name Cmin -qrc_tech $qrc_min
create_delay_corner -name WC -early_timing_condition { timing_wc } \
-late_timing_condition { timing_wc } \
-early_rc_corner Cmax \
-late_rc_corner Cmax
create_delay_corner -name BC -early_timing_condition { timing_bc } \
-late_timing_condition { timing_bc } \
-early_rc_corner Cmin \
-late_rc_corner Cmin
create_constraint_mode -name CON -sdc_file $sdc
create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
set_analysis_view -setup WC_VIEW -hold BC_VIEW
Flows/NanGate45/ariane136/scripts/cadence/run.sh
......@@ -7,5 +7,5 @@ module unload innovus
module load innovus/21.1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
Flows/NanGate45/ariane136/scripts/cadence/run_genus_iSpatial.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
read_mmmc mmmc_iSpatial_setup.tcl
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
read_physical -lefs $lefs
# Target library
set link_library $list_lib
set target_library $list_lib
# set path
set_db auto_ungroup none
#set_db library $list_lib
#################################################
# Load Design and Initialize
#################################################
source rtl_list.tcl
foreach rtl_file $rtl_all {
read_hdl -sv $rtl_file
}
elaborate $DESIGN
time_info Elaboration
#read_sdc $sdc
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
###############################################
# Read DEF
###############################################
read_def $floorplan_def
check_floorplan -detailed
# keep hierarchy during synthesis
set_db auto_ungroup none
syn_generic -physical
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
syn_map -physical
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
syn_opt -spatial
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
#write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
#write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exit
Flows/NanGate45/ariane136/scripts/cadence/run_invs.tcl
......@@ -73,40 +73,14 @@ createPinBlkg -name side_top -edge 1
createPinBlkg -name side_right -edge 2
createPinBlkg -name side_bottom -edge 3
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setNanoRouteMode -routeTopRoutingLayer 10
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
#setPlaceMode -placeIoPins true
setDesignMode -topRoutingLayer 10
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
## Creating Pin Blcokage for lower and upper pin layers ##
createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
createPinBlkg -name Layer_2 -edge 1
createPinBlkg -name Layer_3 -edge 2
createPinBlkg -name Layer_4 -edge 3
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setNanoRouteMode -routeTopRoutingLayer 10
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
setPlaceMode -placeIoPins true
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
defOut -netlist -floorplan ${DESIGN}_placed.def
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
......@@ -121,12 +95,10 @@ set_clock_propagation propagated
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
setNanoRouteMode -routeTopRoutingLayer 10
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
setNanoRouteMode -routeUseAutoVia true
##Recommended by lib owners
# Prevent router modifying M1 pins shapes
......@@ -135,7 +107,6 @@ setNanoRouteMode -routeWithViaOnlyForStandardCellPin "1:1"
## limit VIAs to ongrid only for VIA1 (S1)
setNanoRouteMode -drouteOnGridOnly "via 1:1"
setNanoRouteMode -dbCheckRule true
setNanoRouteMode -drouteAutoStop false
setNanoRouteMode -drouteExpAdvancedMarFix true
setNanoRouteMode -routeExpAdvancedTechnology true
......@@ -143,24 +114,11 @@ setNanoRouteMode -routeExpAdvancedTechnology true
#SM suggestion for solving long extraction runtime during GR
setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
defOut -netlist -floorplan -routing ${DESIGN}_route.def
setDelayCalMode -reset
setDelayCalMode -SIAware true
setExtractRCMode -engine postRoute -coupled true -tQuantusForPostRoute false
setAnalysisMode -analysisType onChipVariation -cppr both
# routeOpt
#optDesign -postRoute -setup -hold -prefix postRoute -expandedViews
#extractRC
deselectAll
selectNet -clock
reportSelect > summaryReport/clock_net_length.post_route
deselectAll
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
......
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