Updated flow figures

Signed-off-by: sakundu <sakundu@ucsd.edu>

CodeElements/Clustering/README.md

@@ -106,7 +106,7 @@ distribute any compiled binaries. While we build our implementation on top of th
 
 Input file: [setup.tcl](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Clustering/test/setup.tcl) (you can follow the example to set up your own design) and [FixFile](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Clustering/test/fix_files_grouping/ariane.fix.old) (This file is generated by our [Grouping](https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/CodeElements/Grouping) scripts)
 
-Output_files: [clusters.lef](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Clustering/test/results/OpenROAD/clusters.lef) and [clustered_netlist.def](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Clustering/test/results/OpenROAD/clustered_netlist.def) for OpenROAD flows; [cluster.tcl](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Clustering/test/results/Cadence/ariane_cluster_500.tcl) for Cadence flows.
+Output_files: [clusters.lef](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Clustering/test/results/OpenROAD/clusters.lef) and [clustered_netlist.def](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Clustering/test/results/OpenROAD/clustered_netlist.def) for OpenROAD flows; [cluster.tcl](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Clustering/test/results/Cadence/ariane_cluster_500.tcl) for Cadence flows; [ariane.pb.txt](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Clustering/test/results/Protocol_buffer_format/ariane.pb.txt) for clustered netlist in protocol buffer format.
 
 Note that the [example](https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/CodeElements/Clustering/test) that we provide is the ariane design implemented in NanGate45.  The netlist and corresponding def file with placed instances are generated by [Genus iSpatial](https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/Flows/NanGate45/ariane133) flow. Here the macro placement is automatically done by the Genus and Innovus tools,
 i.e., according to Flow **(B.1)** above.

CodeElements/Clustering/src/clustering.py

@@ -128,8 +128,6 @@ class Clustering:
                      self.net_file, self.soft_macros, \
                      self.pbf_file, self.net_size_threshold, 1.0)
 
-        exit()
-
 
         self.CreateInvsCluster()  # Generate Innovus Clustering Commands
         self.CreateDef()  # Generate clustered lef and def file

CodeElements/Clustering/test/rtl_mp/ariane.hgr.outline

-0  0  1599.99  1598.8

CodeElements/FormatTranslators/src/FormatTranslators.py

@@ -43,6 +43,13 @@ class Port:
         self.str += "node {\n"
         self.str += '  name: "' + self.name + '"\n'
         for sink in self.sinks:
+            sink_new = ''
+            for char in sink:
+                if char == '\\':
+                    sink_new += '\\\\'
+                else:
+                    sink_new += char
+            sink = sink_new
             self.str += '  input: "' + sink + '"\n'
         self.str += "  attr {\n"
         self.str += '    key: "type"\n'
@@ -108,6 +115,13 @@ class StandardCell:
         self.str += "node {\n"
         self.str += '  name: "' + self.name + '"\n'
         for sink in self.sinks:
+            sink_new = ''
+            for char in sink:
+                if char == '\\':
+                    sink_new += '\\\\'
+                else:
+                    sink_new += char
+            sink = sink_new
             self.str += '  input: "' + sink + '"\n'
         self.str += "  attr {\n"
         self.str += '    key: "type"\n'
@@ -263,6 +277,13 @@ class MacroPin:
         self.str += "node {\n"
         self.str += '  name: "' + self.name + '"\n'
         for sink in self.sinks:
+            sink_new = ''
+            for char in sink:
+                if char == '\\':
+                    sink_new += '\\\\'
+                else:
+                    sink_new += char
+            sink = sink_new
             self.str += '  input: "' + sink + '"\n'
         self.str += "  attr {\n"
         self.str += '    key: "macro_name"\n'

README.md

 # **MacroPlacement**
-**MacroPlacement** is an open, transparent effort to provide a public, baseline implementation of [Google Brain's Circuit Training](https://github.com/google-research/circuit_training) (Morpheus) deep RL-based placement method. We will provide (1) testcases in open enablements, along with multiple EDA tool flows; (2) implementations of missing or binarized elements of Circuit Training; (3) reproducible example macro placement solutions produced by our implementation; and (4) post-routing results obtained by full completion of the place-and-route flow using both proprietary and open-source tools.
+**MacroPlacement** is an open, transparent effort to provide a public, baseline implementation of [Google Brain's Circuit Training](https://github.com/google-research/circuit_training) (Morpheus) deep RL-based placement method. We will provide (1) testcases in open enablements, along with multiple EDA tool flows; (2) implementations of missing or binarized elements of Circuit Training; (3) reproducible example macro placement solutions produced by our implementation; and (4) post-routing results obtained by full completion of the synthesis-place-and-route flow using both proprietary and open-source tools.
   
 ## **Table of Contents**
   <!-- - [Reproducible Example Solutions](#reproducible-example-solutions) -->
-  - [Testcases](#testcases)
-  - [Enablements](#enablements)
-  - [Flows](#flows)
-  - [Code Elements](#code-elements)
+  - [Testcases](#testcases) contains open-source designs such as Ariane, MemPool and NVDLA.
+  - [Enablements](#enablements) contains PDKs for open-source enablements such as NanGate45, ASAP7 and SKY130HD with FakeStack. Memories required by the designs are also included.
+  - [Flows](#flows) contains tool setups and runscripts for both proprietary and open-source SP&R tools such as Cadence Genus/Innovus and OpenROAD.
+  - [Code Elements](#code-elements) contains implementation of engines such as Clustering, Grouping, Gridding, Format translators required by Circuit Training flow.
   - [FAQ](#faq)
   - [Related Links](#related-links)
 
 ## **Testcases**  
-The list of available testcases
+The list of available testcases is as follows.
 - Ariane (RTL)
-  - [RTL files for Ariane design with 136 macros](./Testcases/ariane136/), which are generated by instantiating 16-bit memories in Ariane netlist availabe in [lowRISC](https://github.com/lowRISC/ariane) GitHub repository.
-  - [RTL files for Ariane designs with 133 macros](./Testcases/ariane133/), which are generated by updating the memory connection of 136 macro version.
+  - [RTL files for Ariane design with 136 macros](./Testcases/ariane136/), which are generated by instantiating 16-bit memories in Ariane netlist available in the [lowRISC](https://github.com/lowRISC/ariane) GitHub repository.
+  - [RTL files for Ariane design with 133 macros](./Testcases/ariane133/), which are generated by updating the memory connections of the 136 macro version.
 - MemPool (RTL)
-  - [RTL files for Mempool tile design](./Testcases/mempool_tile/)
-  - RTL files for Mempool group design
+  - [RTL files for Mempool tile design](./Testcases/mempool/)
+  - [RTL files for Mempool group design](./Testcases/mempool/)
 - NVDLA (RTL)
   - [RTL files for NVDLA Partition *c*](./Testcases/nvdla/)
   
-In the [Nature Paper](https://www.nature.com/articles/s41586-021-03544-w), the authors report results for an Ariane design with 133 memory (256x16, single ported SRAM) macros. We observe that synthesizing from the available Ariane RTL in the [lowRISC](https://github.com/lowRISC/ariane) GitHub repository using 256x16 memories results in an Ariane design that has 136 memory macros. We outline the steps instantiate memories for Ariane 136 [here](./Testcases/ariane136/) and we show how we convert the Ariane 136 design to an Ariane 133 design that matches Google's SRAM count [here](./Testcases/ariane133/). 
+In the [Nature Paper](https://www.nature.com/articles/s41586-021-03544-w), the authors report results for an Ariane design with 133 memory (256x16, single ported SRAM) macros. We observe that synthesizing from the available Ariane RTL in the [lowRISC](https://github.com/lowRISC/ariane) GitHub repository using 256x16 memories results in an Ariane design that has 136 memory macros. We outline the steps to instantiate the memories for Ariane 136 [here](./Testcases/ariane136/) and we show how we convert the Ariane 136 design to an Ariane 133 design that matches Google's memory macros count [here](./Testcases/ariane133/). 
 
 
-All the testcases are available under the [Testcases](./Testcases/) directory. Details of the sub-directories of each testcases:  
-  - *rtl*: directory contains all the required rtl files to synthesize the testcase.
-  - *sv2v*: If the main repository contains multiple Verilog files or the SystemVerilog files, then we convert it to a single Verilog file. This is availabe in the *sv2v* sub-drectory.
+All the testcases are available in the [Testcases](./Testcases/) directory. Details of the sub-directories are  
+  - *rtl*: directory contains all the required rtl files to synthesize the design.
+  - *sv2v*: If the main repository contains multiple Verilog files or SystemVerilog files, then we convert it to a single synthesizable Verilog RTL. This is available in the *sv2v* sub-drectory.
 
 ## **Enablements**
-The list of available enablements
+The list of available enablements is as follows.
 - [NanGate45](./Enablements/NanGate45/)
 - [ASAP7](./Enablements/ASAP7/)
 - [SKY130HD FakeStack](./Enablements/SKY130HD/)
   
-Open-source enablements NanGate45, ASAP7 and SKY130DH are utilized in our SP&R flow. All the enablements are available under [Enablements](./Enablements) directory. Details of the sub-directories of each enablements:
- - *lib* directory contains all the required liberty files.
+Open-source enablements NanGate45, ASAP7 and SKY130HD are utilized in our SP&R flow. All the enablements are available under the [Enablements](./Enablements) directory. Details of the sub-directories are:
+ - *lib* directory contains all the required liberty files for standard cells and hard macros.
  - *lef* directory contains all the required lef files.
  - *qrc* directory contains all the required qrc tech files.
   
-Also, we provide steps to generate the fakerams.
+We also provide the steps to generate the fakeram models for each of the enablements based on the required memory configurations.
 
 
 ## **Flows**
-We provide multiple flows for each of the testcases and enablements. They are logical synthesis-based SP&R flow using Cadence Genus and Innovus ([Flow-1](./Flows/figures/flow-1.PNG)), physical synthesis-based SP&R flow using Cadence Genus iSpatial and Innovus ([Flow-2](./Flows/figures/flow-2.PNG)), logical synthesis-based SP&R flow using Yosys and OpenROAD ([Flow-3](./Flows/figures/flow-3.PNG)), and input data for Physical synthesis based CircuitTraining using Genus iSpatial ([Flow-4](./Flows/figures/flow-4.PNG)).
+We provide multiple flows for each of the testcases and enablements. They are: (1) a logical synthesis-based SP&R flow using Cadence Genus and Innovus ([Flow-1](./Flows/figures/flow-1.PNG)), (2) a physical synthesis-based SP&R flow using Cadence Genus iSpatial and Innovus ([Flow-2](./Flows/figures/flow-2.PNG)), (3) a logical synthesis-based SP&R flow using Yosys and OpenROAD ([Flow-3](./Flows/figures/flow-3.PNG)), and (4) creation of input data for Physical synthesis-based Circuit Training using Genus iSpatial ([Flow-4](./Flows/figures/flow-4.PNG)).
 
-The details of each flow are shown below:  
+The details of each flow are are given in the following.
 - **Flow-1:**  
   <img src="./Flows/figures/flow-1.PNG" alt="Flow-1" width="800"/>
-
 - **Flow-2:**  
   <img src="./Flows/figures/flow-2.PNG" alt="Flow-2" width="800"/>    
 - **Flow-3:**  
@@ -57,7 +56,7 @@ The details of each flow are shown below:
   <img src="./Flows/figures/flow-4.PNG" alt="Flow-4" width="800"/>  
 
 
-In the table below, we provide the details of each testcase on each of the enablements for the different flows.
+In the following table, we provide the status details of each testcase on each of the enablements for the different flows.
 <table class="tg">
 <thead>
   <tr>
@@ -146,7 +145,7 @@ In the table below, we provide the details of each testcase on each of the enabl
 </table>
 
 
-The directory structure is as follows *./FLows/\<enablement\>/\<testcase\>/<constraint\|def\|netlist\|scripts\|run>/*. Details of the sub-directories for each testcase on each enablement:
+The directory structure is : *./Flows/\<enablement\>/\<testcase\>/<constraint\|def\|netlist\|scripts\|run>/*. Details of the sub-directories for each testcase on each enablement are as follows.
 - *constraint* directory contains the *.sdc* file.
 - *def* directory contains the def file with pin placement and die area information.
 - *scripts* directory contains required scripts to run SP&R using the Cadence and OpenROAD tools.
@@ -186,7 +185,7 @@ while allowing soft macros (standard-cell clusters) to also find good locations.
   - simulated annealing on the gridded canvas: documentation and implementation
   - donated cloud resources (credits) for experimental studies
   - relevant testcases with reference implementations and implementation flows (Cadence, OpenROAD preferred since scripts can be shared)
-  - protobuf, lef/def, Bookshelf: detailed and confirmed documentation, plus translators
+  - protobuf, lef/def, Bookshelf: detailed and confirmed documentation, plus tests and other help to improve our initial versions of translators
   - "fakeram" generator for the ASAP7 research PDK
   - qrctechfile for NanGate45