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macroplacement
Commit cd524b57 by sakundu
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Updated flow figures 

Signed-off-by: sakundu <sakundu@ucsd.edu>
parents 0eb4b697 ad4a5646
Showing with 45 additions and 523 deletions
CodeElements/Clustering/README.md
......@@ -106,7 +106,7 @@ distribute any compiled binaries. While we build our implementation on top of th
Input file: [setup.tcl](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Clustering/test/setup.tcl) (you can follow the example to set up your own design) and [FixFile](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Clustering/test/fix_files_grouping/ariane.fix.old) (This file is generated by our [Grouping](https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/CodeElements/Grouping) scripts)
Output_files: [clusters.lef](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Clustering/test/results/OpenROAD/clusters.lef) and [clustered_netlist.def](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Clustering/test/results/OpenROAD/clustered_netlist.def) for OpenROAD flows; [cluster.tcl](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Clustering/test/results/Cadence/ariane_cluster_500.tcl) for Cadence flows.
Output_files: [clusters.lef](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Clustering/test/results/OpenROAD/clusters.lef) and [clustered_netlist.def](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Clustering/test/results/OpenROAD/clustered_netlist.def) for OpenROAD flows; [cluster.tcl](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Clustering/test/results/Cadence/ariane_cluster_500.tcl) for Cadence flows; [ariane.pb.txt](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Clustering/test/results/Protocol_buffer_format/ariane.pb.txt) for clustered netlist in protocol buffer format.
Note that the [example](https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/CodeElements/Clustering/test) that we provide is the ariane design implemented in NanGate45. The netlist and corresponding def file with placed instances are generated by [Genus iSpatial](https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/Flows/NanGate45/ariane133) flow. Here the macro placement is automatically done by the Genus and Innovus tools,
i.e., according to Flow **(B.1)** above.
......
CodeElements/Clustering/src/clustering.py
......@@ -128,8 +128,6 @@ class Clustering:
self.net_file, self.soft_macros, \
self.pbf_file, self.net_size_threshold, 1.0)
exit()
self.CreateInvsCluster() # Generate Innovus Clustering Commands
self.CreateDef() # Generate clustered lef and def file
......
CodeElements/Clustering/test/rtl_mp/ariane.hgr deleted 100644 → 0
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CodeElements/Clustering/test/rtl_mp/ariane.hgr.fix deleted 100644 → 0
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CodeElements/Clustering/test/rtl_mp/ariane.hgr.instance deleted 100644 → 0
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CodeElements/Clustering/test/rtl_mp/ariane.hgr.io deleted 100644 → 0
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rst_ni 0 903.175 0.07 903.245
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boot_addr_i[14] 0 853.195 0.07 853.265
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boot_addr_i[10] 0 851.515 0.07 851.585
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boot_addr_i[8] 0 850.675 0.07 850.745
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boot_addr_i[6] 0 849.835 0.07 849.905
boot_addr_i[5] 0 849.415 0.07 849.485
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hart_id_i[63] 0 901.495 0.07 901.565
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hart_id_i[59] 0 899.815 0.07 899.885
hart_id_i[58] 0 899.395 0.07 899.465
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hart_id_i[55] 0 898.135 0.07 898.205
hart_id_i[54] 0 897.715 0.07 897.785
hart_id_i[53] 0 897.295 0.07 897.365
hart_id_i[52] 0 896.875 0.07 896.945
hart_id_i[51] 0 896.455 0.07 896.525
hart_id_i[50] 0 896.035 0.07 896.105
hart_id_i[49] 0 895.615 0.07 895.685
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hart_id_i[47] 0 894.775 0.07 894.845
hart_id_i[46] 0 894.355 0.07 894.425
hart_id_i[45] 0 893.935 0.07 894.005
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hart_id_i[43] 0 893.095 0.07 893.165
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hart_id_i[40] 0 891.835 0.07 891.905
hart_id_i[39] 0 891.415 0.07 891.485
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hart_id_i[37] 0 890.575 0.07 890.645
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hart_id_i[31] 0 888.055 0.07 888.125
hart_id_i[30] 0 887.635 0.07 887.705
hart_id_i[29] 0 887.215 0.07 887.285
hart_id_i[28] 0 886.795 0.07 886.865
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hart_id_i[26] 0 885.955 0.07 886.025
hart_id_i[25] 0 885.535 0.07 885.605
hart_id_i[24] 0 885.115 0.07 885.185
hart_id_i[23] 0 884.695 0.07 884.765
hart_id_i[22] 0 884.275 0.07 884.345
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hart_id_i[20] 0 883.435 0.07 883.505
hart_id_i[19] 0 883.015 0.07 883.085
hart_id_i[18] 0 882.595 0.07 882.665
hart_id_i[17] 0 882.175 0.07 882.245
hart_id_i[16] 0 881.755 0.07 881.825
hart_id_i[15] 0 881.335 0.07 881.405
hart_id_i[14] 0 880.915 0.07 880.985
hart_id_i[13] 0 880.495 0.07 880.565
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hart_id_i[11] 0 879.655 0.07 879.725
hart_id_i[10] 0 879.235 0.07 879.305
hart_id_i[9] 0 878.815 0.07 878.885
hart_id_i[8] 0 878.395 0.07 878.465
hart_id_i[7] 0 877.975 0.07 878.045
hart_id_i[6] 0 877.555 0.07 877.625
hart_id_i[5] 0 877.135 0.07 877.205
hart_id_i[4] 0 876.715 0.07 876.785
hart_id_i[3] 0 876.295 0.07 876.365
hart_id_i[2] 0 875.875 0.07 875.945
hart_id_i[1] 0 875.455 0.07 875.525
hart_id_i[0] 0 875.035 0.07 875.105
irq_i[1] 0 902.755 0.07 902.825
irq_i[0] 0 902.335 0.07 902.405
ipi_i 0 901.915 0.07 901.985
time_irq_i 0 903.595 0.07 903.665
debug_req_i 0 874.615 0.07 874.685
axi_req_o\[r_ready\] 0 780.115 0.07 780.185
axi_req_o\[ar_valid\] 0 733.495 0.07 733.565
axi_req_o\[ar\]\[region\][3] 0 731.815 0.07 731.885
axi_req_o\[ar\]\[region\][2] 0 731.395 0.07 731.465
axi_req_o\[ar\]\[region\][1] 0 730.975 0.07 731.045
axi_req_o\[ar\]\[region\][0] 0 730.555 0.07 730.625
axi_req_o\[ar\]\[qos\][3] 0 730.135 0.07 730.205
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axi_req_o\[ar\]\[prot\][1] 0 728.035 0.07 728.105
axi_req_o\[ar\]\[prot\][0] 0 727.615 0.07 727.685
axi_req_o\[ar\]\[cache\][3] 0 721.735 0.07 721.805
axi_req_o\[ar\]\[cache\][2] 0 721.315 0.07 721.385
axi_req_o\[ar\]\[cache\][1] 0 720.895 0.07 720.965
axi_req_o\[ar\]\[cache\][0] 0 720.475 0.07 720.545
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axi_req_o\[ar\]\[addr\][13] 0 698.215 0.07 698.285
axi_req_o\[ar\]\[addr\][12] 0 697.795 0.07 697.865
axi_req_o\[ar\]\[addr\][11] 0 697.375 0.07 697.445
axi_req_o\[ar\]\[addr\][10] 0 696.955 0.07 697.025
axi_req_o\[ar\]\[addr\][9] 0 696.535 0.07 696.605
axi_req_o\[ar\]\[addr\][8] 0 696.115 0.07 696.185
axi_req_o\[ar\]\[addr\][7] 0 695.695 0.07 695.765
axi_req_o\[ar\]\[addr\][6] 0 695.275 0.07 695.345
axi_req_o\[ar\]\[addr\][5] 0 694.855 0.07 694.925
axi_req_o\[ar\]\[addr\][4] 0 694.435 0.07 694.505
axi_req_o\[ar\]\[addr\][3] 0 694.015 0.07 694.085
axi_req_o\[ar\]\[addr\][2] 0 693.595 0.07 693.665
axi_req_o\[ar\]\[addr\][1] 0 693.175 0.07 693.245
axi_req_o\[ar\]\[addr\][0] 0 692.755 0.07 692.825
axi_req_o\[ar\]\[id\][3] 0 723.415 0.07 723.485
axi_req_o\[ar\]\[id\][2] 0 722.995 0.07 723.065
axi_req_o\[ar\]\[id\][1] 0 722.575 0.07 722.645
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axi_req_o\[w\]\[strb\][7] 0 812.035 0.07 812.105
axi_req_o\[w\]\[strb\][6] 0 811.615 0.07 811.685
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axi_req_o\[w\]\[strb\][4] 0 810.775 0.07 810.845
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axi_req_o\[w\]\[strb\][2] 0 809.935 0.07 810.005
axi_req_o\[w\]\[strb\][1] 0 809.515 0.07 809.585
axi_req_o\[w\]\[strb\][0] 0 809.095 0.07 809.165
axi_req_o\[w\]\[data\][63] 0 808.255 0.07 808.325
axi_req_o\[w\]\[data\][62] 0 807.835 0.07 807.905
axi_req_o\[w\]\[data\][61] 0 807.415 0.07 807.485
axi_req_o\[w\]\[data\][60] 0 806.995 0.07 807.065
axi_req_o\[w\]\[data\][59] 0 806.575 0.07 806.645
axi_req_o\[w\]\[data\][58] 0 806.155 0.07 806.225
axi_req_o\[w\]\[data\][57] 0 805.735 0.07 805.805
axi_req_o\[w\]\[data\][56] 0 805.315 0.07 805.385
axi_req_o\[w\]\[data\][55] 0 804.895 0.07 804.965
axi_req_o\[w\]\[data\][54] 0 804.475 0.07 804.545
axi_req_o\[w\]\[data\][53] 0 804.055 0.07 804.125
axi_req_o\[w\]\[data\][52] 0 803.635 0.07 803.705
axi_req_o\[w\]\[data\][51] 0 803.215 0.07 803.285
axi_req_o\[w\]\[data\][50] 0 802.795 0.07 802.865
axi_req_o\[w\]\[data\][49] 0 802.375 0.07 802.445
axi_req_o\[w\]\[data\][48] 0 801.955 0.07 802.025
axi_req_o\[w\]\[data\][47] 0 801.535 0.07 801.605
axi_req_o\[w\]\[data\][46] 0 801.115 0.07 801.185
axi_req_o\[w\]\[data\][45] 0 800.695 0.07 800.765
axi_req_o\[w\]\[data\][44] 0 800.275 0.07 800.345
axi_req_o\[w\]\[data\][43] 0 799.855 0.07 799.925
axi_req_o\[w\]\[data\][42] 0 799.435 0.07 799.505
axi_req_o\[w\]\[data\][41] 0 799.015 0.07 799.085
axi_req_o\[w\]\[data\][40] 0 798.595 0.07 798.665
axi_req_o\[w\]\[data\][39] 0 798.175 0.07 798.245
axi_req_o\[w\]\[data\][38] 0 797.755 0.07 797.825
axi_req_o\[w\]\[data\][37] 0 797.335 0.07 797.405
axi_req_o\[w\]\[data\][36] 0 796.915 0.07 796.985
axi_req_o\[w\]\[data\][35] 0 796.495 0.07 796.565
axi_req_o\[w\]\[data\][34] 0 796.075 0.07 796.145
axi_req_o\[w\]\[data\][33] 0 795.655 0.07 795.725
axi_req_o\[w\]\[data\][32] 0 795.235 0.07 795.305
axi_req_o\[w\]\[data\][31] 0 794.815 0.07 794.885
axi_req_o\[w\]\[data\][30] 0 794.395 0.07 794.465
axi_req_o\[w\]\[data\][29] 0 793.975 0.07 794.045
axi_req_o\[w\]\[data\][28] 0 793.555 0.07 793.625
axi_req_o\[w\]\[data\][27] 0 793.135 0.07 793.205
axi_req_o\[w\]\[data\][26] 0 792.715 0.07 792.785
axi_req_o\[w\]\[data\][25] 0 792.295 0.07 792.365
axi_req_o\[w\]\[data\][24] 0 791.875 0.07 791.945
axi_req_o\[w\]\[data\][23] 0 791.455 0.07 791.525
axi_req_o\[w\]\[data\][22] 0 791.035 0.07 791.105
axi_req_o\[w\]\[data\][21] 0 790.615 0.07 790.685
axi_req_o\[w\]\[data\][20] 0 790.195 0.07 790.265
axi_req_o\[w\]\[data\][19] 0 789.775 0.07 789.845
axi_req_o\[w\]\[data\][18] 0 789.355 0.07 789.425
axi_req_o\[w\]\[data\][17] 0 788.935 0.07 789.005
axi_req_o\[w\]\[data\][16] 0 788.515 0.07 788.585
axi_req_o\[w\]\[data\][15] 0 788.095 0.07 788.165
axi_req_o\[w\]\[data\][14] 0 787.675 0.07 787.745
axi_req_o\[w\]\[data\][13] 0 787.255 0.07 787.325
axi_req_o\[w\]\[data\][12] 0 786.835 0.07 786.905
axi_req_o\[w\]\[data\][11] 0 786.415 0.07 786.485
axi_req_o\[w\]\[data\][10] 0 785.995 0.07 786.065
axi_req_o\[w\]\[data\][9] 0 785.435 0.07 785.505
axi_req_o\[w\]\[data\][8] 0 784.875 0.07 784.945
axi_req_o\[w\]\[data\][7] 0 784.315 0.07 784.385
axi_req_o\[w\]\[data\][6] 0 783.755 0.07 783.825
axi_req_o\[w\]\[data\][5] 0 783.195 0.07 783.265
axi_req_o\[w\]\[data\][4] 0 782.635 0.07 782.705
axi_req_o\[w\]\[data\][3] 0 782.075 0.07 782.145
axi_req_o\[w\]\[data\][2] 0 781.515 0.07 781.585
axi_req_o\[w\]\[data\][1] 0 780.955 0.07 781.025
axi_req_o\[w\]\[data\][0] 0 780.535 0.07 780.605
axi_req_o\[aw_valid\] 0 779.275 0.07 779.345
axi_req_o\[aw\]\[atop\][5] 0 764.435 0.07 764.505
axi_req_o\[aw\]\[atop\][4] 0 764.015 0.07 764.085
axi_req_o\[aw\]\[atop\][3] 0 763.595 0.07 763.665
axi_req_o\[aw\]\[atop\][2] 0 763.175 0.07 763.245
axi_req_o\[aw\]\[atop\][1] 0 762.755 0.07 762.825
axi_req_o\[aw\]\[atop\][0] 0 762.335 0.07 762.405
axi_req_o\[aw\]\[region\][3] 0 777.315 0.07 777.385
axi_req_o\[aw\]\[region\][2] 0 776.755 0.07 776.825
axi_req_o\[aw\]\[region\][1] 0 776.195 0.07 776.265
axi_req_o\[aw\]\[region\][0] 0 775.775 0.07 775.845
axi_req_o\[aw\]\[qos\][3] 0 775.355 0.07 775.425
axi_req_o\[aw\]\[qos\][2] 0 774.935 0.07 775.005
axi_req_o\[aw\]\[qos\][1] 0 774.515 0.07 774.585
axi_req_o\[aw\]\[qos\][0] 0 774.095 0.07 774.165
axi_req_o\[aw\]\[prot\][2] 0 773.675 0.07 773.745
axi_req_o\[aw\]\[prot\][1] 0 773.255 0.07 773.325
axi_req_o\[aw\]\[prot\][0] 0 772.835 0.07 772.905
axi_req_o\[aw\]\[cache\][3] 0 766.955 0.07 767.025
axi_req_o\[aw\]\[cache\][2] 0 766.535 0.07 766.605
axi_req_o\[aw\]\[cache\][1] 0 766.115 0.07 766.185
axi_req_o\[aw\]\[cache\][0] 0 765.695 0.07 765.765
axi_req_o\[aw\]\[lock\] 0 772.415 0.07 772.485
axi_req_o\[aw\]\[burst\][1] 0 765.275 0.07 765.345
axi_req_o\[aw\]\[burst\][0] 0 764.855 0.07 764.925
axi_req_o\[aw\]\[size\][2] 0 778.715 0.07 778.785
axi_req_o\[aw\]\[size\][1] 0 778.155 0.07 778.225
axi_req_o\[aw\]\[size\][0] 0 777.735 0.07 777.805
axi_req_o\[aw\]\[len\][7] 0 771.995 0.07 772.065
axi_req_o\[aw\]\[len\][6] 0 771.575 0.07 771.645
axi_req_o\[aw\]\[len\][5] 0 771.155 0.07 771.225
axi_req_o\[aw\]\[len\][4] 0 770.735 0.07 770.805
axi_req_o\[aw\]\[len\][3] 0 770.315 0.07 770.385
axi_req_o\[aw\]\[len\][2] 0 769.895 0.07 769.965
axi_req_o\[aw\]\[len\][1] 0 769.475 0.07 769.545
axi_req_o\[aw\]\[len\][0] 0 769.055 0.07 769.125
axi_req_o\[aw\]\[addr\][63] 0 761.915 0.07 761.985
axi_req_o\[aw\]\[addr\][62] 0 761.495 0.07 761.565
axi_req_o\[aw\]\[addr\][61] 0 761.075 0.07 761.145
axi_req_o\[aw\]\[addr\][60] 0 760.655 0.07 760.725
axi_req_o\[aw\]\[addr\][59] 0 760.235 0.07 760.305
axi_req_o\[aw\]\[addr\][58] 0 759.815 0.07 759.885
axi_req_o\[aw\]\[addr\][57] 0 759.395 0.07 759.465
axi_req_o\[aw\]\[addr\][56] 0 758.975 0.07 759.045
axi_req_o\[aw\]\[addr\][55] 0 758.555 0.07 758.625
axi_req_o\[aw\]\[addr\][54] 0 758.135 0.07 758.205
axi_req_o\[aw\]\[addr\][53] 0 757.715 0.07 757.785
axi_req_o\[aw\]\[addr\][52] 0 757.295 0.07 757.365
axi_req_o\[aw\]\[addr\][51] 0 756.875 0.07 756.945
axi_req_o\[aw\]\[addr\][50] 0 756.315 0.07 756.385
axi_req_o\[aw\]\[addr\][49] 0 755.755 0.07 755.825
axi_req_o\[aw\]\[addr\][48] 0 755.195 0.07 755.265
axi_req_o\[aw\]\[addr\][47] 0 754.635 0.07 754.705
axi_req_o\[aw\]\[addr\][46] 0 754.075 0.07 754.145
axi_req_o\[aw\]\[addr\][45] 0 753.515 0.07 753.585
axi_req_o\[aw\]\[addr\][44] 0 752.955 0.07 753.025
axi_req_o\[aw\]\[addr\][43] 0 752.395 0.07 752.465
axi_req_o\[aw\]\[addr\][42] 0 751.835 0.07 751.905
axi_req_o\[aw\]\[addr\][41] 0 751.415 0.07 751.485
axi_req_o\[aw\]\[addr\][40] 0 750.995 0.07 751.065
axi_req_o\[aw\]\[addr\][39] 0 750.575 0.07 750.645
axi_req_o\[aw\]\[addr\][38] 0 750.155 0.07 750.225
axi_req_o\[aw\]\[addr\][37] 0 749.595 0.07 749.665
axi_req_o\[aw\]\[addr\][36] 0 749.035 0.07 749.105
axi_req_o\[aw\]\[addr\][35] 0 748.615 0.07 748.685
axi_req_o\[aw\]\[addr\][34] 0 748.195 0.07 748.265
axi_req_o\[aw\]\[addr\][33] 0 747.775 0.07 747.845
axi_req_o\[aw\]\[addr\][32] 0 747.355 0.07 747.425
axi_req_o\[aw\]\[addr\][31] 0 746.935 0.07 747.005
axi_req_o\[aw\]\[addr\][30] 0 746.515 0.07 746.585
axi_req_o\[aw\]\[addr\][29] 0 746.095 0.07 746.165
axi_req_o\[aw\]\[addr\][28] 0 745.675 0.07 745.745
axi_req_o\[aw\]\[addr\][27] 0 745.255 0.07 745.325
axi_req_o\[aw\]\[addr\][26] 0 744.835 0.07 744.905
axi_req_o\[aw\]\[addr\][25] 0 744.415 0.07 744.485
axi_req_o\[aw\]\[addr\][24] 0 743.995 0.07 744.065
axi_req_o\[aw\]\[addr\][23] 0 743.575 0.07 743.645
axi_req_o\[aw\]\[addr\][22] 0 743.155 0.07 743.225
axi_req_o\[aw\]\[addr\][21] 0 742.735 0.07 742.805
axi_req_o\[aw\]\[addr\][20] 0 742.315 0.07 742.385
axi_req_o\[aw\]\[addr\][19] 0 741.895 0.07 741.965
axi_req_o\[aw\]\[addr\][18] 0 741.475 0.07 741.545
axi_req_o\[aw\]\[addr\][17] 0 741.055 0.07 741.125
axi_req_o\[aw\]\[addr\][16] 0 740.635 0.07 740.705
axi_req_o\[aw\]\[addr\][15] 0 740.215 0.07 740.285
axi_req_o\[aw\]\[addr\][14] 0 739.795 0.07 739.865
axi_req_o\[aw\]\[addr\][13] 0 739.375 0.07 739.445
axi_req_o\[aw\]\[addr\][12] 0 738.955 0.07 739.025
axi_req_o\[aw\]\[addr\][11] 0 738.535 0.07 738.605
axi_req_o\[aw\]\[addr\][10] 0 738.115 0.07 738.185
axi_req_o\[aw\]\[addr\][9] 0 737.695 0.07 737.765
axi_req_o\[aw\]\[addr\][8] 0 737.275 0.07 737.345
axi_req_o\[aw\]\[addr\][7] 0 736.855 0.07 736.925
axi_req_o\[aw\]\[addr\][6] 0 736.435 0.07 736.505
axi_req_o\[aw\]\[addr\][5] 0 736.015 0.07 736.085
axi_req_o\[aw\]\[addr\][4] 0 735.595 0.07 735.665
axi_req_o\[aw\]\[addr\][3] 0 735.175 0.07 735.245
axi_req_o\[aw\]\[addr\][2] 0 734.755 0.07 734.825
axi_req_o\[aw\]\[addr\][1] 0 734.335 0.07 734.405
axi_req_o\[aw\]\[addr\][0] 0 733.915 0.07 733.985
axi_req_o\[aw\]\[id\][3] 0 768.635 0.07 768.705
axi_req_o\[aw\]\[id\][2] 0 768.215 0.07 768.285
axi_req_o\[aw\]\[id\][1] 0 767.795 0.07 767.865
axi_req_o\[aw\]\[id\][0] 0 767.375 0.07 767.445
axi_resp_i\[r\]\[last\] 0 845.215 0.07 845.285
axi_resp_i\[r\]\[resp\][1] 0 846.055 0.07 846.125
axi_resp_i\[r\]\[resp\][0] 0 845.635 0.07 845.705
axi_resp_i\[r\]\[data\][63] 0 843.115 0.07 843.185
axi_resp_i\[r\]\[data\][62] 0 842.695 0.07 842.765
axi_resp_i\[r\]\[data\][61] 0 842.275 0.07 842.345
axi_resp_i\[r\]\[data\][60] 0 841.855 0.07 841.925
axi_resp_i\[r\]\[data\][59] 0 841.435 0.07 841.505
axi_resp_i\[r\]\[data\][58] 0 841.015 0.07 841.085
axi_resp_i\[r\]\[data\][57] 0 840.595 0.07 840.665
axi_resp_i\[r\]\[data\][56] 0 840.175 0.07 840.245
axi_resp_i\[r\]\[data\][55] 0 839.755 0.07 839.825
axi_resp_i\[r\]\[data\][54] 0 839.335 0.07 839.405
axi_resp_i\[r\]\[data\][53] 0 838.915 0.07 838.985
axi_resp_i\[r\]\[data\][52] 0 838.495 0.07 838.565
axi_resp_i\[r\]\[data\][51] 0 838.075 0.07 838.145
axi_resp_i\[r\]\[data\][50] 0 837.655 0.07 837.725
axi_resp_i\[r\]\[data\][49] 0 837.235 0.07 837.305
axi_resp_i\[r\]\[data\][48] 0 836.815 0.07 836.885
axi_resp_i\[r\]\[data\][47] 0 836.395 0.07 836.465
axi_resp_i\[r\]\[data\][46] 0 835.975 0.07 836.045
axi_resp_i\[r\]\[data\][45] 0 835.555 0.07 835.625
axi_resp_i\[r\]\[data\][44] 0 835.135 0.07 835.205
axi_resp_i\[r\]\[data\][43] 0 834.715 0.07 834.785
axi_resp_i\[r\]\[data\][42] 0 834.295 0.07 834.365
axi_resp_i\[r\]\[data\][41] 0 833.875 0.07 833.945
axi_resp_i\[r\]\[data\][40] 0 833.455 0.07 833.525
axi_resp_i\[r\]\[data\][39] 0 833.035 0.07 833.105
axi_resp_i\[r\]\[data\][38] 0 832.615 0.07 832.685
axi_resp_i\[r\]\[data\][37] 0 832.195 0.07 832.265
axi_resp_i\[r\]\[data\][36] 0 831.775 0.07 831.845
axi_resp_i\[r\]\[data\][35] 0 831.355 0.07 831.425
axi_resp_i\[r\]\[data\][34] 0 830.935 0.07 831.005
axi_resp_i\[r\]\[data\][33] 0 830.515 0.07 830.585
axi_resp_i\[r\]\[data\][32] 0 830.095 0.07 830.165
axi_resp_i\[r\]\[data\][31] 0 829.675 0.07 829.745
axi_resp_i\[r\]\[data\][30] 0 829.255 0.07 829.325
axi_resp_i\[r\]\[data\][29] 0 828.835 0.07 828.905
axi_resp_i\[r\]\[data\][28] 0 828.415 0.07 828.485
axi_resp_i\[r\]\[data\][27] 0 827.995 0.07 828.065
axi_resp_i\[r\]\[data\][26] 0 827.575 0.07 827.645
axi_resp_i\[r\]\[data\][25] 0 827.155 0.07 827.225
axi_resp_i\[r\]\[data\][24] 0 826.735 0.07 826.805
axi_resp_i\[r\]\[data\][23] 0 826.315 0.07 826.385
axi_resp_i\[r\]\[data\][22] 0 825.895 0.07 825.965
axi_resp_i\[r\]\[data\][21] 0 825.475 0.07 825.545
axi_resp_i\[r\]\[data\][20] 0 825.055 0.07 825.125
axi_resp_i\[r\]\[data\][19] 0 824.635 0.07 824.705
axi_resp_i\[r\]\[data\][18] 0 824.215 0.07 824.285
axi_resp_i\[r\]\[data\][17] 0 823.795 0.07 823.865
axi_resp_i\[r\]\[data\][16] 0 823.375 0.07 823.445
axi_resp_i\[r\]\[data\][15] 0 822.955 0.07 823.025
axi_resp_i\[r\]\[data\][14] 0 822.535 0.07 822.605
axi_resp_i\[r\]\[data\][13] 0 822.115 0.07 822.185
axi_resp_i\[r\]\[data\][12] 0 821.695 0.07 821.765
axi_resp_i\[r\]\[data\][11] 0 821.275 0.07 821.345
axi_resp_i\[r\]\[data\][10] 0 820.855 0.07 820.925
axi_resp_i\[r\]\[data\][9] 0 820.435 0.07 820.505
axi_resp_i\[r\]\[data\][8] 0 820.015 0.07 820.085
axi_resp_i\[r\]\[data\][7] 0 819.595 0.07 819.665
axi_resp_i\[r\]\[data\][6] 0 819.175 0.07 819.245
axi_resp_i\[r\]\[data\][5] 0 818.755 0.07 818.825
axi_resp_i\[r\]\[data\][4] 0 818.335 0.07 818.405
axi_resp_i\[r\]\[data\][3] 0 817.915 0.07 817.985
axi_resp_i\[r\]\[data\][2] 0 817.495 0.07 817.565
axi_resp_i\[r\]\[data\][1] 0 817.075 0.07 817.145
axi_resp_i\[r\]\[data\][0] 0 816.655 0.07 816.725
axi_resp_i\[r\]\[id\][3] 0 844.795 0.07 844.865
axi_resp_i\[r\]\[id\][2] 0 844.375 0.07 844.445
axi_resp_i\[r\]\[id\][1] 0 843.955 0.07 844.025
axi_resp_i\[r\]\[id\][0] 0 843.535 0.07 843.605
axi_resp_i\[r_valid\] 0 846.475 0.07 846.545
axi_resp_i\[b\]\[resp\][1] 0 815.815 0.07 815.885
axi_resp_i\[b\]\[resp\][0] 0 815.395 0.07 815.465
axi_resp_i\[b\]\[id\][3] 0 814.975 0.07 815.045
axi_resp_i\[b\]\[id\][2] 0 814.555 0.07 814.625
axi_resp_i\[b\]\[id\][1] 0 814.135 0.07 814.205
axi_resp_i\[b\]\[id\][0] 0 813.715 0.07 813.785
axi_resp_i\[b_valid\] 0 816.235 0.07 816.305
axi_resp_i\[w_ready\] 0 846.895 0.07 846.965
axi_resp_i\[ar_ready\] 0 812.875 0.07 812.945
axi_resp_i\[aw_ready\] 0 813.295 0.07 813.365
CodeElements/Clustering/test/rtl_mp/ariane.hgr.macro_pin deleted 100644 → 0
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CodeElements/Clustering/test/rtl_mp/ariane.hgr.net deleted 100644 → 0
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CodeElements/FormatTranslators/src/FormatTranslators.py
......@@ -43,6 +43,13 @@ class Port:
self.str += "node {\n"
self.str += ' name: "' + self.name + '"\n'
for sink in self.sinks:
sink_new = ''
for char in sink:
if char == '\\':
sink_new += '\\\\'
else:
sink_new += char
sink = sink_new
self.str += ' input: "' + sink + '"\n'
self.str += " attr {\n"
self.str += ' key: "type"\n'
......@@ -108,6 +115,13 @@ class StandardCell:
self.str += "node {\n"
self.str += ' name: "' + self.name + '"\n'
for sink in self.sinks:
sink_new = ''
for char in sink:
if char == '\\':
sink_new += '\\\\'
else:
sink_new += char
sink = sink_new
self.str += ' input: "' + sink + '"\n'
self.str += " attr {\n"
self.str += ' key: "type"\n'
......@@ -263,6 +277,13 @@ class MacroPin:
self.str += "node {\n"
self.str += ' name: "' + self.name + '"\n'
for sink in self.sinks:
sink_new = ''
for char in sink:
if char == '\\':
sink_new += '\\\\'
else:
sink_new += char
sink = sink_new
self.str += ' input: "' + sink + '"\n'
self.str += " attr {\n"
self.str += ' key: "macro_name"\n'
......
CodeElements/FormatTranslators/test/LefDef2ProtocolBufferFormat/ariane.pb.txt 0 → 100644
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README.md
# **MacroPlacement**
**MacroPlacement** is an open, transparent effort to provide a public, baseline implementation of [Google Brain's Circuit Training](https://github.com/google-research/circuit_training) (Morpheus) deep RL-based placement method. We will provide (1) testcases in open enablements, along with multiple EDA tool flows; (2) implementations of missing or binarized elements of Circuit Training; (3) reproducible example macro placement solutions produced by our implementation; and (4) post-routing results obtained by full completion of the place-and-route flow using both proprietary and open-source tools.
**MacroPlacement** is an open, transparent effort to provide a public, baseline implementation of [Google Brain's Circuit Training](https://github.com/google-research/circuit_training) (Morpheus) deep RL-based placement method. We will provide (1) testcases in open enablements, along with multiple EDA tool flows; (2) implementations of missing or binarized elements of Circuit Training; (3) reproducible example macro placement solutions produced by our implementation; and (4) post-routing results obtained by full completion of the synthesis-place-and-route flow using both proprietary and open-source tools.
## **Table of Contents**
<!-- - [Reproducible Example Solutions](#reproducible-example-solutions) -->
- [Testcases](#testcases)
- [Enablements](#enablements)
- [Flows](#flows)
- [Code Elements](#code-elements)
- [Testcases](#testcases) contains open-source designs such as Ariane, MemPool and NVDLA.
- [Enablements](#enablements) contains PDKs for open-source enablements such as NanGate45, ASAP7 and SKY130HD with FakeStack. Memories required by the designs are also included.
- [Flows](#flows) contains tool setups and runscripts for both proprietary and open-source SP&R tools such as Cadence Genus/Innovus and OpenROAD.
- [Code Elements](#code-elements) contains implementation of engines such as Clustering, Grouping, Gridding, Format translators required by Circuit Training flow.
- [FAQ](#faq)
- [Related Links](#related-links)
## **Testcases**
The list of available testcases
The list of available testcases is as follows.
- Ariane (RTL)
- [RTL files for Ariane design with 136 macros](./Testcases/ariane136/), which are generated by instantiating 16-bit memories in Ariane netlist availabe in [lowRISC](https://github.com/lowRISC/ariane) GitHub repository.
- [RTL files for Ariane designs with 133 macros](./Testcases/ariane133/), which are generated by updating the memory connection of 136 macro version.
- [RTL files for Ariane design with 136 macros](./Testcases/ariane136/), which are generated by instantiating 16-bit memories in Ariane netlist available in the [lowRISC](https://github.com/lowRISC/ariane) GitHub repository.
- [RTL files for Ariane design with 133 macros](./Testcases/ariane133/), which are generated by updating the memory connections of the 136 macro version.
- MemPool (RTL)
- [RTL files for Mempool tile design](./Testcases/mempool_tile/)
- RTL files for Mempool group design
- [RTL files for Mempool tile design](./Testcases/mempool/)
- [RTL files for Mempool group design](./Testcases/mempool/)
- NVDLA (RTL)
- [RTL files for NVDLA Partition *c*](./Testcases/nvdla/)
In the [Nature Paper](https://www.nature.com/articles/s41586-021-03544-w), the authors report results for an Ariane design with 133 memory (256x16, single ported SRAM) macros. We observe that synthesizing from the available Ariane RTL in the [lowRISC](https://github.com/lowRISC/ariane) GitHub repository using 256x16 memories results in an Ariane design that has 136 memory macros. We outline the steps instantiate memories for Ariane 136 [here](./Testcases/ariane136/) and we show how we convert the Ariane 136 design to an Ariane 133 design that matches Google's SRAM count [here](./Testcases/ariane133/).
In the [Nature Paper](https://www.nature.com/articles/s41586-021-03544-w), the authors report results for an Ariane design with 133 memory (256x16, single ported SRAM) macros. We observe that synthesizing from the available Ariane RTL in the [lowRISC](https://github.com/lowRISC/ariane) GitHub repository using 256x16 memories results in an Ariane design that has 136 memory macros. We outline the steps to instantiate the memories for Ariane 136 [here](./Testcases/ariane136/) and we show how we convert the Ariane 136 design to an Ariane 133 design that matches Google's memory macros count [here](./Testcases/ariane133/).
All the testcases are available under the [Testcases](./Testcases/) directory. Details of the sub-directories of each testcases:
- *rtl*: directory contains all the required rtl files to synthesize the testcase.
- *sv2v*: If the main repository contains multiple Verilog files or the SystemVerilog files, then we convert it to a single Verilog file. This is availabe in the *sv2v* sub-drectory.
All the testcases are available in the [Testcases](./Testcases/) directory. Details of the sub-directories are
- *rtl*: directory contains all the required rtl files to synthesize the design.
- *sv2v*: If the main repository contains multiple Verilog files or SystemVerilog files, then we convert it to a single synthesizable Verilog RTL. This is available in the *sv2v* sub-drectory.
## **Enablements**
The list of available enablements
The list of available enablements is as follows.
- [NanGate45](./Enablements/NanGate45/)
- [ASAP7](./Enablements/ASAP7/)
- [SKY130HD FakeStack](./Enablements/SKY130HD/)
Open-source enablements NanGate45, ASAP7 and SKY130DH are utilized in our SP&R flow. All the enablements are available under [Enablements](./Enablements) directory. Details of the sub-directories of each enablements:
- *lib* directory contains all the required liberty files.
Open-source enablements NanGate45, ASAP7 and SKY130HD are utilized in our SP&R flow. All the enablements are available under the [Enablements](./Enablements) directory. Details of the sub-directories are:
- *lib* directory contains all the required liberty files for standard cells and hard macros.
- *lef* directory contains all the required lef files.
- *qrc* directory contains all the required qrc tech files.
Also, we provide steps to generate the fakerams.
We also provide the steps to generate the fakeram models for each of the enablements based on the required memory configurations.
## **Flows**
We provide multiple flows for each of the testcases and enablements. They are logical synthesis-based SP&R flow using Cadence Genus and Innovus ([Flow-1](./Flows/figures/flow-1.PNG)), physical synthesis-based SP&R flow using Cadence Genus iSpatial and Innovus ([Flow-2](./Flows/figures/flow-2.PNG)), logical synthesis-based SP&R flow using Yosys and OpenROAD ([Flow-3](./Flows/figures/flow-3.PNG)), and input data for Physical synthesis based CircuitTraining using Genus iSpatial ([Flow-4](./Flows/figures/flow-4.PNG)).
We provide multiple flows for each of the testcases and enablements. They are: (1) a logical synthesis-based SP&R flow using Cadence Genus and Innovus ([Flow-1](./Flows/figures/flow-1.PNG)), (2) a physical synthesis-based SP&R flow using Cadence Genus iSpatial and Innovus ([Flow-2](./Flows/figures/flow-2.PNG)), (3) a logical synthesis-based SP&R flow using Yosys and OpenROAD ([Flow-3](./Flows/figures/flow-3.PNG)), and (4) creation of input data for Physical synthesis-based Circuit Training using Genus iSpatial ([Flow-4](./Flows/figures/flow-4.PNG)).
The details of each flow are shown below:
The details of each flow are are given in the following.
- **Flow-1:**
<img src="./Flows/figures/flow-1.PNG" alt="Flow-1" width="800"/>
- **Flow-2:**
<img src="./Flows/figures/flow-2.PNG" alt="Flow-2" width="800"/>
- **Flow-3:**
......@@ -57,7 +56,7 @@ The details of each flow are shown below:
<img src="./Flows/figures/flow-4.PNG" alt="Flow-4" width="800"/>
In the table below, we provide the details of each testcase on each of the enablements for the different flows.
In the following table, we provide the status details of each testcase on each of the enablements for the different flows.
<table class="tg">
<thead>
<tr>
......@@ -146,7 +145,7 @@ In the table below, we provide the details of each testcase on each of the enabl
</table>
The directory structure is as follows *./FLows/\<enablement\>/\<testcase\>/<constraint\|def\|netlist\|scripts\|run>/*. Details of the sub-directories for each testcase on each enablement:
The directory structure is : *./Flows/\<enablement\>/\<testcase\>/<constraint\|def\|netlist\|scripts\|run>/*. Details of the sub-directories for each testcase on each enablement are as follows.
- *constraint* directory contains the *.sdc* file.
- *def* directory contains the def file with pin placement and die area information.
- *scripts* directory contains required scripts to run SP&R using the Cadence and OpenROAD tools.
......@@ -186,7 +185,7 @@ while allowing soft macros (standard-cell clusters) to also find good locations.
- simulated annealing on the gridded canvas: documentation and implementation
- donated cloud resources (credits) for experimental studies
- relevant testcases with reference implementations and implementation flows (Cadence, OpenROAD preferred since scripts can be shared)
- protobuf, lef/def, Bookshelf: detailed and confirmed documentation, plus translators
- protobuf, lef/def, Bookshelf: detailed and confirmed documentation, plus tests and other help to improve our initial versions of translators
- "fakeram" generator for the ASAP7 research PDK
- qrctechfile for NanGate45
......
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