Updated run_invs.tcl and extract_report.tcl to include postSynthesis report

Signed-off-by: sakundu <sakundu@ucsd.edu>

Updated run_invs.tcl and extract_report.tcl to include postSynthesis report
Signed-off-by: sakundu <sakundu@ucsd.edu>
bd96fa01 · sakundu · fd2bceab · bd96fa01 · bd96fa01 · bd96fa01
Commit bd96fa01 authored Sep 21, 2022 by sakundu
21 changed files
--- a/Flows/ASAP7/ariane133/scripts/cadence/run_genus_hybrid.tcl
+++ b/Flows/ASAP7/ariane133/scripts/cadence/run_genus_hybrid.tcl
@@ -136,6 +136,7 @@ write_reports -directory ${REPORTS_PATH} -tag final

 if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+    exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
 } else {
    write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
    write_hdl > ${HANDOFF_PATH}/${DESIGN}.v

--- a/Flows/ASAP7/ariane133/scripts/cadence/run_invs.tcl
+++ b/Flows/ASAP7/ariane133/scripts/cadence/run_invs.tcl
@@ -3,7 +3,6 @@
 setLibraryUnit -time 1.0ps
 source lib_setup.tcl
 source design_setup.tcl
-source mmmc_setup.tcl

 setMultiCpuUsage -localCpu 16
 set util 0.3
@@ -12,6 +11,7 @@ set handoff_dir  "./syn_handoff"

 set netlist ${handoff_dir}/${DESIGN}.v
 set sdc ${handoff_dir}/${DESIGN}.sdc 
+source mmmc_setup.tcl

 set rptDir summaryReport/ 
 set encDir enc/
@@ -69,6 +69,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    #snapFPlan -pin
 }

+### Write postSynth report ###
+echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_post_synth [extract_report postSynth]
+echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
+
 ### Write out the def files ###
 source ../../../../util/write_required_def.tcl

@@ -86,8 +92,6 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc

-echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
-source ../../../../util/extract_report.tcl
 set rpt_pre_cts [extract_report preCTS]
 echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt


--- a/Flows/ASAP7/ariane136/scripts/cadence/run_genus_hybrid.tcl
+++ b/Flows/ASAP7/ariane136/scripts/cadence/run_genus_hybrid.tcl
@@ -136,6 +136,7 @@ write_reports -directory ${REPORTS_PATH} -tag final

 if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+    exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
 } else {
    write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
    write_hdl > ${HANDOFF_PATH}/${DESIGN}.v

--- a/Flows/ASAP7/ariane136/scripts/cadence/run_invs.tcl
+++ b/Flows/ASAP7/ariane136/scripts/cadence/run_invs.tcl
@@ -3,7 +3,6 @@
 setLibraryUnit -time 1.0ps
 source lib_setup.tcl
 source design_setup.tcl
-source mmmc_setup.tcl

 setMultiCpuUsage -localCpu 16
 set util 0.3
@@ -12,6 +11,7 @@ set handoff_dir  "./syn_handoff"

 set netlist ${handoff_dir}/${DESIGN}.v
 set sdc ${handoff_dir}/${DESIGN}.sdc 
+source mmmc_setup.tcl

 set rptDir summaryReport/ 
 set encDir enc/
@@ -69,6 +69,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    #snapFPlan -pin
 }

+### Write postSynth report ###
+echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_post_synth [extract_report postSynth]
+echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
+
 ### Write out the def files ###
 source ../../../../util/write_required_def.tcl

@@ -86,8 +92,6 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc

-echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
-source ../../../../util/extract_report.tcl
 set rpt_pre_cts [extract_report preCTS]
 echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt


--- a/Flows/ASAP7/mempool_tile/scripts/cadence/run_genus_hybrid.tcl
+++ b/Flows/ASAP7/mempool_tile/scripts/cadence/run_genus_hybrid.tcl
@@ -136,6 +136,7 @@ write_reports -directory ${REPORTS_PATH} -tag final

 if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+    exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
 } else {
    write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
    write_hdl > ${HANDOFF_PATH}/${DESIGN}.v

--- a/Flows/ASAP7/nvdla/scripts/cadence/run_genus_hybrid.tcl
+++ b/Flows/ASAP7/nvdla/scripts/cadence/run_genus_hybrid.tcl
@@ -137,6 +137,7 @@ write_reports -directory ${REPORTS_PATH} -tag final

 if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+    exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
 } else {
    write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
    write_hdl > ${HANDOFF_PATH}/${DESIGN}.v

--- a/Flows/ASAP7/nvdla/scripts/cadence/run_invs.tcl
+++ b/Flows/ASAP7/nvdla/scripts/cadence/run_invs.tcl
@@ -3,7 +3,6 @@
 setLibraryUnit -time 1.0ps
 source lib_setup.tcl
 source design_setup.tcl
-source mmmc_setup.tcl

 setMultiCpuUsage -localCpu 16
 set util 0.3
@@ -12,6 +11,7 @@ set handoff_dir  "./syn_handoff"

 set netlist ${handoff_dir}/${DESIGN}.v
 set sdc ${handoff_dir}/${DESIGN}.sdc 
+source mmmc_setup.tcl

 set rptDir summaryReport/ 
 set encDir enc/
@@ -69,6 +69,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    #snapFPlan -pin
 }

+### Write postSynth report ###
+echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_post_synth [extract_report postSynth]
+echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
+
 ### Write out the def files ###
 source ../../../../util/write_required_def.tcl

@@ -86,8 +92,6 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc

-echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
-source ../../../../util/extract_report.tcl
 set rpt_pre_cts [extract_report preCTS]
 echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt


--- a/Flows/NanGate45/ariane133/constraints/ariane.sdc
+++ b/Flows/NanGate45/ariane133/constraints/ariane.sdc
 #period set in nano-seconds - currently: 4ns = 250 MHz freq
-create_clock [get_ports clk_i]  -name core_clock  -period 4
+create_clock [get_ports clk_i]  -name core_clock  -period 1.3
--- a/Flows/NanGate45/ariane133/scripts/cadence/run_genus_hybrid.tcl
+++ b/Flows/NanGate45/ariane133/scripts/cadence/run_genus_hybrid.tcl
@@ -136,6 +136,7 @@ write_reports -directory ${REPORTS_PATH} -tag final

 if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+    exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
 } else {
    write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
    write_hdl > ${HANDOFF_PATH}/${DESIGN}.v

--- a/Flows/NanGate45/ariane133/scripts/cadence/run_invs.tcl
+++ b/Flows/NanGate45/ariane133/scripts/cadence/run_invs.tcl
@@ -68,6 +68,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    refine_macro_place
 }

+### Write postSynth report ###
+echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_post_synth [extract_report postSynth]
+echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
+
 ### Write out the def files ###
 source ../../../../util/write_required_def.tcl

@@ -85,8 +91,6 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc

-echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
-source ../../../../util/extract_report.tcl
 set rpt_pre_cts [extract_report preCTS]
 echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt


--- a/Flows/NanGate45/ariane136/scripts/cadence/run_genus_hybrid.tcl
+++ b/Flows/NanGate45/ariane136/scripts/cadence/run_genus_hybrid.tcl
@@ -136,6 +136,7 @@ write_reports -directory ${REPORTS_PATH} -tag final

 if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+    exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
 } else {
    write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
    write_hdl > ${HANDOFF_PATH}/${DESIGN}.v

--- a/Flows/NanGate45/ariane136/scripts/cadence/run_invs.tcl
+++ b/Flows/NanGate45/ariane136/scripts/cadence/run_invs.tcl
@@ -2,7 +2,6 @@
 # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
 source lib_setup.tcl
 source design_setup.tcl
-source mmmc_setup.tcl

 setMultiCpuUsage -localCpu 16
 set util 0.3
@@ -11,6 +10,7 @@ set handoff_dir  "./syn_handoff"

 set netlist ${handoff_dir}/${DESIGN}.v
 set sdc ${handoff_dir}/${DESIGN}.sdc 
+source mmmc_setup.tcl

 set rptDir summaryReport/ 
 set encDir enc/
@@ -66,6 +66,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    refine_macro_place
 }

+### Write postSynth report ###
+echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_post_synth [extract_report postSynth]
+echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
+
 ### Write out the def files ###
 source ../../../../util/write_required_def.tcl

@@ -83,8 +89,6 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc

-echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
-source ../../../../util/extract_report.tcl
 set rpt_pre_cts [extract_report preCTS]
 echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt


--- a/Flows/NanGate45/mempool_tile/scripts/cadence/run_genus_hybrid.tcl
+++ b/Flows/NanGate45/mempool_tile/scripts/cadence/run_genus_hybrid.tcl
@@ -136,6 +136,7 @@ write_reports -directory ${REPORTS_PATH} -tag final

 if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+    exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
 } else {
    write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
    write_hdl > ${HANDOFF_PATH}/${DESIGN}.v

--- a/Flows/NanGate45/nvdla/scripts/cadence/run_genus_hybrid.tcl
+++ b/Flows/NanGate45/nvdla/scripts/cadence/run_genus_hybrid.tcl
@@ -139,6 +139,7 @@ write_reports -directory ${REPORTS_PATH} -tag final

 if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+    exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
 } else {
    write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
    write_hdl > ${HANDOFF_PATH}/${DESIGN}.v

--- a/Flows/NanGate45/nvdla/scripts/cadence/run_invs.tcl
+++ b/Flows/NanGate45/nvdla/scripts/cadence/run_invs.tcl
@@ -2,7 +2,6 @@
 # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
 source lib_setup.tcl
 source design_setup.tcl
-source mmmc_setup.tcl

 setMultiCpuUsage -localCpu 16
 set util 0.3
@@ -11,6 +10,7 @@ set handoff_dir  "./syn_handoff"

 set netlist ${handoff_dir}/${DESIGN}.v
 set sdc ${handoff_dir}/${DESIGN}.sdc 
+source mmmc_setup.tcl

 set rptDir summaryReport/ 
 set encDir enc/
@@ -66,6 +66,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    refine_macro_place
 }

+### Write postSynth report ###
+echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_post_synth [extract_report postSynth]
+echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
+
 ### Write out the def files ###
 source ../../../../util/write_required_def.tcl

@@ -83,8 +89,6 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc

-echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
-source ../../../../util/extract_report.tcl
 set rpt_pre_cts [extract_report preCTS]
 echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt


--- a/Flows/SKY130HD/ariane133/scripts/cadence/run_genus_hybrid.tcl
+++ b/Flows/SKY130HD/ariane133/scripts/cadence/run_genus_hybrid.tcl
@@ -136,6 +136,7 @@ write_reports -directory ${REPORTS_PATH} -tag final

 if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+    exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
 } else {
    write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
    write_hdl > ${HANDOFF_PATH}/${DESIGN}.v

--- a/Flows/SKY130HD/ariane133/scripts/cadence/run_invs.tcl
+++ b/Flows/SKY130HD/ariane133/scripts/cadence/run_invs.tcl
@@ -2,7 +2,6 @@
 # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
 source lib_setup.tcl
 source design_setup.tcl
-source mmmc_setup.tcl

 setMultiCpuUsage -localCpu 16
 set util 0.3
@@ -11,6 +10,7 @@ set handoff_dir  "./syn_handoff"

 set netlist ${handoff_dir}/${DESIGN}.v
 set sdc ${handoff_dir}/${DESIGN}.sdc 
+source mmmc_setup.tcl

 set rptDir summaryReport/ 
 set encDir enc/
@@ -66,6 +66,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    refine_macro_place
 }

+### Write postSynth report ###
+echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_post_synth [extract_report postSynth]
+echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
+
 ### Write out the def files ###
 source ../../../../util/write_required_def.tcl

@@ -83,8 +89,6 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc

-echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
-source ../../../../util/extract_report.tcl
 set rpt_pre_cts [extract_report preCTS]
 echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt


--- a/Flows/SKY130HD/ariane136/scripts/cadence/run_genus_hybrid.tcl
+++ b/Flows/SKY130HD/ariane136/scripts/cadence/run_genus_hybrid.tcl
@@ -136,6 +136,7 @@ write_reports -directory ${REPORTS_PATH} -tag final

 if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+    exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
 } else {
    write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
    write_hdl > ${HANDOFF_PATH}/${DESIGN}.v

--- a/Flows/SKY130HD/ariane136/scripts/cadence/run_invs.tcl
+++ b/Flows/SKY130HD/ariane136/scripts/cadence/run_invs.tcl
@@ -2,7 +2,6 @@
 # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
 source lib_setup.tcl
 source design_setup.tcl
-source mmmc_setup.tcl

 setMultiCpuUsage -localCpu 16
 set util 0.3
@@ -11,6 +10,7 @@ set handoff_dir  "./syn_handoff"

 set netlist ${handoff_dir}/${DESIGN}.v
 set sdc ${handoff_dir}/${DESIGN}.sdc 
+source mmmc_setup.tcl

 set rptDir summaryReport/ 
 set encDir enc/
@@ -66,6 +66,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    refine_macro_place
 }

+### Write postSynth report ###
+echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_post_synth [extract_report postSynth]
+echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
+
 ### Write out the def files ###
 source ../../../../util/write_required_def.tcl

@@ -83,8 +89,6 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc

-echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
-source ../../../../util/extract_report.tcl
 set rpt_pre_cts [extract_report preCTS]
 echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt


--- a/Flows/SKY130HD/nvdla/scripts/cadence/run_invs.tcl
+++ b/Flows/SKY130HD/nvdla/scripts/cadence/run_invs.tcl
@@ -2,7 +2,6 @@
 # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
 source lib_setup.tcl
 source design_setup.tcl
-source mmmc_setup.tcl

 setMultiCpuUsage -localCpu 16
 set util 0.3
@@ -11,6 +10,7 @@ set handoff_dir  "./syn_handoff"

 set netlist ${handoff_dir}/${DESIGN}.v
 set sdc ${handoff_dir}/${DESIGN}.sdc 
+source mmmc_setup.tcl

 set rptDir summaryReport/ 
 set encDir enc/
@@ -66,6 +66,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
    refine_macro_place
 }

+### Write postSynth report ###
+echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_post_synth [extract_report postSynth]
+echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
+
 ### Write out the def files ###
 source ../../../../util/write_required_def.tcl

@@ -83,8 +89,6 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc

-echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
-source ../../../../util/extract_report.tcl
 set rpt_pre_cts [extract_report preCTS]
 echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt


--- a/Flows/util/extract_report.tcl
+++ b/Flows/util/extract_report.tcl
@@ -64,7 +64,10 @@ proc extract_report {stage} {
       timeDesign -postRoute -prefix ${stage}
    } elseif { $stage == "postRouetOpt" } {
       timeDesign -postRoute -prefix ${stage}
+    } elseif { $stage == "postSynth" } {
+       timeDesign -prePlace -prefix ${stage}
    }
+
    set rpt1 [extract_from_timing_rpt timingReports/${stage}.summary.gz]
    report_power > power_${stage}.rpt
    set rpt2 [extract_from_power_rpt power_${stage}.rpt]