add halo_width to gridding

CodeElements/CodeFlowIntegration/flow.py

@@ -24,13 +24,14 @@ macro_lefs = ["./lefs/fakeram45_256x16.lef"]
 ##############################################
 gridding_src_dir = '../Gridding/src'
 tolerance = 0.01
-min_n_rows = 30
-min_n_cols = 30
+min_n_rows = 10
+min_n_cols = 10
 max_n_rows = 50
 max_n_cols = 50
 max_rows_times_cols = 3000
+halo_width = 5
 
-gridding = GriddingLefDefInterface(gridding_src_dir, design, setup_file, tolerance,
+gridding = GriddingLefDefInterface(gridding_src_dir, design, setup_file, tolerance, halo_width,
                                    min_n_rows, min_n_cols, max_n_rows, max_n_cols,
                                    max_rows_times_cols)
 num_rows = gridding.GetNumRows()

CodeElements/Gridding/src/gridding.py

@@ -187,12 +187,13 @@ def Gridding(macro_width_list, macro_height_list,
 
 class GriddingLefDefInterface:
     def __init__(self, src_dir, design, setup_file = "setup.tcl", tolerance = 0.01,
-                 min_n_rows = 10, min_n_cols = 10, max_n_rows = 100, max_n_cols = 100,
-                 max_rows_times_cols = 3000):
+                 halo_width = 5.0, min_n_rows = 10, min_n_cols = 10, max_n_rows = 100,
+                 max_n_cols = 100, max_rows_times_cols = 3000):
         self.src_dir = src_dir
         self.design = design
         self.setup_file = setup_file
         self.tolerance = tolerance
+        self.halo_width = halo_width
         self.min_n_rows = min_n_rows
         self.min_n_cols = min_n_cols
         self.max_n_rows = max_n_rows
@@ -267,8 +268,8 @@ class GriddingLefDefInterface:
         for line in content:
             items = line.split()
             if (items[1] == "1"):
-                self.macro_width_list.append(float(items[4]) - float(items[2]))
-                self.macro_height_list.append(float(items[5]) - float(items[3]))
+                self.macro_width_list.append(float(items[4]) - float(items[2]) + 2 * self.halo_width)
+                self.macro_height_list.append(float(items[5]) - float(items[3]) + 2 * self.halo_width)
             else:
                 self.num_std_cells += 1
 
@@ -276,15 +277,6 @@ class GriddingLefDefInterface:
         shutil.rmtree(rpt_dir)
 
 
-if __name__ == "__main__":
-    # Just test
-    macro_width_list = [1, 2, 3.5, 3.5, 2.5]
-    macro_height_list = [1, 2, 3.5, 3.5, 2.5]
-    chip_width = 10
-    chip_height = 10
-    tolerance = 0.01
-    Gridding(macro_width_list, macro_height_list, chip_width, chip_height, tolerance)
-
 
 
 

CodeElements/Gridding/test/test_gridding.py

@@ -11,6 +11,7 @@ if __name__ == '__main__':
     design = "ariane"
     src_dir = "../src"
     setup_file = "setup.tcl"
-    tolerance = 0.1
-    GriddingLefDefInterface(src_dir, design, setup_file, tolerance)
+    tolerance = 0.01
+    halo_width = 5.0
+    GriddingLefDefInterface(src_dir, design, setup_file, tolerance, halo_width)
 

Flows/NanGate45/ariane133/scripts/OpenROAD/ariane133/config.mk

+export DESIGN_NICKNAME = ariane133
+export DESIGN_NAME = ariane
+export PLATFORM    = nangate45
+
+export VERILOG_FILES = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/ariane.v \
+                       ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v
+
+export SDC_FILE      = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+export ABC_CLOCK_PERIOD_IN_PS = 2000
+
+export ADDITIONAL_LEFS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fakeram45_256x16.lef
+export ADDITIONAL_LIBS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fakeram45_256x16.lib
+
+# These values must be multiples of placement site
+export DIE_AREA    = 0.0 0.0 2072.14 2119.88 
+export CORE_AREA   = 10.07 9.94 2062.07 2109.94
+export PLACE_PINS_ARGS = -exclude left:0-600 -exclude left:1500-2119.88 -exclude right:* -exclude top:* -exclude bottom:*
+#export PLACE_PINS_ARGS = -exclude left:0-600 -exclude left:800-1560 -exclude right:* -exclude top:* -exclude bottom:*
+
+export PLACE_DENSITY_LB_ADDON ?= 0.20
+
+## Adding dont touch for this mdoules
+export PRESERVE_CELLS = SyncSpRamBeNx64_00000008_00000100_0_2 \
+						limping_SyncSpRamBeNx64_00000008_00000100_0_2 \
+						SyncSpRamBeNx64_00000008_00000100_0_2_d45 \
+						SyncSpRamBeNx64_00000008_00000100_0_2_d44

Flows/NanGate45/ariane133/scripts/OpenROAD/ariane133/config_hier.mk

+include $(dir $(DESIGN_CONFIG))/config.mk
+
+#export FLOW_VARIANT = hier
+export FLOW_VARIANT ?= hier_rtlmp
+export SYNTH_HIERARCHICAL = 1
+export MAX_UNGROUP_SIZE = 100
+export RTLMP_FLOW = True
+
+export SDC_FILE      = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_hier.sdc
+
+export FLOORPLAN_DEF = ./results/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)/2_2_floorplan_io.def
+export ABC_CLOCK_PERIOD_IN_PS = 4000
+#
+# RTL_MP Settings
+export RTLMP_MAX_INST = 5000
+export RTLMP_MIN_INST = 1000
+export RTLMP_MAX_MACRO = 12
+export RTLMP_MIN_MACRO = 4
+
+# These values must be multiples of placement site
+export DIE_AREA    = 0 0 2000 2000
+export CORE_AREA   = 10 10 1990 1990
+export PLACE_PINS_ARGS = -exclude left:0-600 -exclude left:1400-2000 -exclude right:* -exclude top:* -exclude bottom:*
+
+export MACRO_PLACE_HALO = 5 5
+export MACRO_PLACE_CHANNEL = 10 10
+
+export PLACE_DENSITY = 0.55
+
+export PRESERVE_CELLS = SyncSpRamBeNx64_00000008_00000100_0_2 \
+						limping_SyncSpRamBeNx64_00000008_00000100_0_2 \
+						SyncSpRamBeNx64_00000008_00000100_0_2_d45 \
+						SyncSpRamBeNx64_00000008_00000100_0_2_d44
+

Flows/NanGate45/ariane133/scripts/OpenROAD/ariane133/macros.v

+module SyncSpRamBeNx64_00000008_00000100_0_2
+  (
+   Clk_CI,
+   Rst_RBI,
+   CSel_SI,
+   WrEn_SI,
+   BEn_SI,
+   WrData_DI,
+   Addr_DI,
+   RdData_DO
+   );
+
+   input [7:0]   BEn_SI; // byte-enable: ignore or use as needed
+   input [63:0]  WrData_DI;
+   input [7:0] 	 Addr_DI;
+   output [63:0] RdData_DO;
+   input 	 Clk_CI;
+   input 	 Rst_RBI; // reset: ignore or use as needed
+   input 	 CSel_SI;
+   input 	 WrEn_SI;
+   wire [63:0] 	 RdData_DO;
+   wire 	 csel_b,wren_b;
+   wire [15:0] WMaskIn, NotWMaskIn;
+
+   assign NotWMaskIn = 16'b0;
+   assign WMaskIn = ~NotWMaskIn;
+   assign wren_b = ~WrEn_SI; // active-low global-write-enable
+   assign csel_b = ~CSel_SI; // active-low chip-select-enable
+
+   fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
+   fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
+   fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[47:32]));
+   fakeram45_256x16 macro_mem_3 (.clk(Clk_CI),.rd_out(RdData_DO[63:48]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[63:48]));
+
+endmodule // SyncSpRamBeNx64_00000008_00000100_0_2
+
+// The valid_dirty_sram should be 4 macros, each 256x16. Instead, they only instantiated 1 256x16 macro
+module limping_SyncSpRamBeNx64_00000008_00000100_0_2
+  (
+   Clk_CI,
+   Rst_RBI,
+   CSel_SI,
+   WrEn_SI,
+   BEn_SI,
+   WrData_DI,
+   Addr_DI,
+   RdData_DO
+   );
+
+   input [7:0]   BEn_SI; // byte-enable: ignore or use as needed
+   input [63:0]  WrData_DI;
+   input [7:0] 	 Addr_DI;
+   output [63:0] RdData_DO;
+   input 	 Clk_CI;
+   input 	 Rst_RBI; // reset: ignore or use as needed
+   input 	 CSel_SI;
+   input 	 WrEn_SI;
+   wire [63:0] 	 RdData_DO;
+   wire 	 csel_b,wren_b;
+   wire [15:0] WMaskIn, NotWMaskIn;
+
+   assign NotWMaskIn = 16'b0;
+   assign WMaskIn = ~NotWMaskIn;
+   assign wren_b = ~WrEn_SI; // active-low global-write-enable
+   assign csel_b = ~CSel_SI; // active-low chip-select-enable
+
+   fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
+   // fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
+   // fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[47:32]));
+   // fakeram45_256x16 macro_mem_3 (.clk(Clk_CI),.rd_out(RdData_DO[63:48]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[63:48]));
+   assign RdData_DO[63:16] = 48'h0;
+
+endmodule // limping_SyncSpRamBeNx64_00000008_00000100_0_2
+
+module SyncSpRamBeNx64_00000008_00000100_0_2_d45
+  (
+   Clk_CI,
+   Rst_RBI,
+   CSel_SI,
+   WrEn_SI,
+   BEn_SI,
+   WrData_DI,
+   Addr_DI,
+   RdData_DO
+   );
+
+   input [7:0]   BEn_SI; // byte-enable: ignore or use as needed
+   input [44:0]  WrData_DI;
+   input [7:0] 	 Addr_DI;
+   output [44:0] RdData_DO;
+   input 	 Clk_CI;
+   input 	 Rst_RBI; // reset: ignore or use as needed
+   input 	 CSel_SI;
+   input 	 WrEn_SI;
+   wire [47:0] 	 RdData_DO_wire;
+   wire 	 csel_b,wren_b;
+   wire [15:0] WMaskIn, NotWMaskIn;
+
+   assign NotWMaskIn = 16'b0;
+   assign WMaskIn = ~NotWMaskIn;
+   assign wren_b = ~WrEn_SI; // active-low global-write-enable
+   assign csel_b = ~CSel_SI; // active-low chip-select-enable
+   assign RdData_DO = RdData_DO_wire[44:0];
+
+   fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO_wire[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
+   fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO_wire[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
+   fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO_wire[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in({3'b000, WrData_DI[44:32]}));
+
+endmodule // SyncSpRamBeNx64_00000008_00000100_0_2_d45
+
+module SyncSpRamBeNx64_00000008_00000100_0_2_d44
+  (
+   Clk_CI,
+   Rst_RBI,
+   CSel_SI,
+   WrEn_SI,
+   BEn_SI,
+   WrData_DI,
+   Addr_DI,
+   RdData_DO
+   );
+
+   input [7:0]   BEn_SI; // byte-enable: ignore or use as needed
+   input [43:0]  WrData_DI;
+   input [7:0] 	 Addr_DI;
+   output [43:0] RdData_DO;
+   input 	 Clk_CI;
+   input 	 Rst_RBI; // reset: ignore or use as needed
+   input 	 CSel_SI;
+   input 	 WrEn_SI;
+   wire [47:0] 	 RdData_DO_wire;
+   wire 	 csel_b,wren_b;
+   wire [15:0] WMaskIn, NotWMaskIn;
+
+   assign NotWMaskIn = 16'b0;
+   assign WMaskIn = ~NotWMaskIn;
+   assign wren_b = ~WrEn_SI; // active-low global-write-enable
+   assign csel_b = ~CSel_SI; // active-low chip-select-enable
+   assign RdData_DO = RdData_DO_wire[43:0];
+
+   fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO_wire[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
+   fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO_wire[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
+   fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO_wire[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in({4'b0000, WrData_DI[43:32]}));
+
+endmodule // SyncSpRamBeNx64_00000008_00000100_0_2_d44
+