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macroplacement
Commit 853c5fe9 by Ravi Varadarajan
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Merge branch 'flow_scripts' of github.com:TILOS-AI-Institute/MacroPlacement into flow_scripts

parents 7d35fccb 7a6e4352
Showing with 287 additions and 18 deletions
CodeElements/Clustering/test/rtl_mp/ariane.hgr.fix 0 → 100644
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CodeElements/CodeFlowIntegration/flow.py
......@@ -24,13 +24,14 @@ macro_lefs = ["./lefs/fakeram45_256x16.lef"]
##############################################
gridding_src_dir = '../Gridding/src'
tolerance = 0.01
min_n_rows = 30
min_n_cols = 30
min_n_rows = 10
min_n_cols = 10
max_n_rows = 50
max_n_cols = 50
max_rows_times_cols = 3000
halo_width = 5
gridding = GriddingLefDefInterface(gridding_src_dir, design, setup_file, tolerance,
gridding = GriddingLefDefInterface(gridding_src_dir, design, setup_file, tolerance, halo_width,
min_n_rows, min_n_cols, max_n_rows, max_n_cols,
max_rows_times_cols)
num_rows = gridding.GetNumRows()
......
CodeElements/Gridding/src/gridding.py
......@@ -187,12 +187,13 @@ def Gridding(macro_width_list, macro_height_list,
class GriddingLefDefInterface:
def __init__(self, src_dir, design, setup_file = "setup.tcl", tolerance = 0.01,
min_n_rows = 10, min_n_cols = 10, max_n_rows = 100, max_n_cols = 100,
max_rows_times_cols = 3000):
halo_width = 5.0, min_n_rows = 10, min_n_cols = 10, max_n_rows = 100,
max_n_cols = 100, max_rows_times_cols = 3000):
self.src_dir = src_dir
self.design = design
self.setup_file = setup_file
self.tolerance = tolerance
self.halo_width = halo_width
self.min_n_rows = min_n_rows
self.min_n_cols = min_n_cols
self.max_n_rows = max_n_rows
......@@ -267,8 +268,8 @@ class GriddingLefDefInterface:
for line in content:
items = line.split()
if (items[1] == "1"):
self.macro_width_list.append(float(items[4]) - float(items[2]))
self.macro_height_list.append(float(items[5]) - float(items[3]))
self.macro_width_list.append(float(items[4]) - float(items[2]) + 2 * self.halo_width)
self.macro_height_list.append(float(items[5]) - float(items[3]) + 2 * self.halo_width)
else:
self.num_std_cells += 1
......@@ -276,15 +277,6 @@ class GriddingLefDefInterface:
shutil.rmtree(rpt_dir)
if __name__ == "__main__":
# Just test
macro_width_list = [1, 2, 3.5, 3.5, 2.5]
macro_height_list = [1, 2, 3.5, 3.5, 2.5]
chip_width = 10
chip_height = 10
tolerance = 0.01
Gridding(macro_width_list, macro_height_list, chip_width, chip_height, tolerance)
......
CodeElements/Gridding/test/test_gridding.py
......@@ -11,6 +11,7 @@ if __name__ == '__main__':
design = "ariane"
src_dir = "../src"
setup_file = "setup.tcl"
tolerance = 0.1
GriddingLefDefInterface(src_dir, design, setup_file, tolerance)
tolerance = 0.01
halo_width = 5.0
GriddingLefDefInterface(src_dir, design, setup_file, tolerance, halo_width)
Flows/NanGate45/ariane133/README.md
We implement [Ariane design with 133 macros](../../../Testcases/ariane133) on the [NanGate45](../../../Enablements/NanGate45) platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R).
## *Macro Placement Generated by Cadence Flow-1*
The screenshot of the design using Cadence Flow-1 on Nangate45 enablement is shown below
<img src="./screenshots/Ariane133_Innovus.png" alt="ariane133_cadence" width="400"/>
## *Macro Placement Generated by ORFS*
The screenshot of the design using ORFS on Nangate45 enablement is shown below
<img src="./screenshots/Ariane133_ORFS.png" alt="ariane136_orfs" width="400"/>
## *Baseline Macro Placement Generated by Human*
The screenshot of the design using Cadence tool for standard cell placement and routing on Nangate45 enablement is shown below
<img src="./screenshots/manual_ariane133_Innovus.png" alt="ariane133_cadence" width="400"/>
The manual macro placement is provided in [manual_floorplan.def](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/Flows/NanGate45/ariane133/def/manual_floorplan.def).
We generate the manual macro placement in two steps:
(1) we call the [gridding](https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/CodeElements/Gridding) scripts to generate grid cells (27 x 27 in our case); (2) we manually place macros on the center of grid cells.
The macro placement can be a competitive baseline for [Circuit Training](https://github.com/google-research/circuit_training).
The metrics after different physical design stages are shown below.
Note that (1) we set the activity factor to 0.2 in our flow; (2) the standard cell area does not include physical cells; (3) In order to match [Nature paper](https://www.nature.com/articles/s41586-021-03544-w), we adjust the pin positions to occupy about 60% of the left boundary.
<table class="tg">
<thead>
<tr>
<th class="tg-0lax">Stage in Physcial Design</th>
<th class="tg-0lax">Core Area (um^2)</th>
<th class="tg-0lax">Standard Cell Area (um^2)</th>
<th class="tg-0lax">Total Power (mW)</th>
<th class="tg-0lax">Wirelength (m)</th>
<th class="tg-0lax">WNS (ps)</th>
<th class="tg-0lax">TNS (ns)</th>
</tr>
</thead>
<tbody>
<tr>
<td class="tg-0lax">Post-placement</td>
<td class="tg-0lax">2560080</td>
<td class="tg-0lax">215189</td>
<td class="tg-0lax">0.29</td>
<td class="tg-0lax">4.47</td>
<td class="tg-0lax">-2</td>
<td class="tg-0lax">-0.05</td>
</tr>
</tbody>
<tbody>
<tr>
<td class="tg-0lax">Post-CTS</td>
<td class="tg-0lax">2560080</td>
<td class="tg-0lax">216326</td>
<td class="tg-0lax">0.30</td>
<td class="tg-0lax">4.47</td>
<td class="tg-0lax">1</td>
<td class="tg-0lax">0</td>
</tr>
</tbody>
<tbody>
<tr>
<td class="tg-0lax">Post-Routing</td>
<td class="tg-0lax">2560080</td>
<td class="tg-0lax">216326</td>
<td class="tg-0lax">0.30</td>
<td class="tg-0lax">4.59</td>
<td class="tg-0lax">62</td>
<td class="tg-0lax">0</td>
</tr>
</tbody>
</table>
Flows/NanGate45/ariane133/def/manual_floorplan.def 0 → 100644
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Flows/NanGate45/ariane133/scripts/OpenROAD/ariane133/ariane.v 0 → 100644
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Flows/NanGate45/ariane133/scripts/OpenROAD/ariane133/config.mk 0 → 100644
export DESIGN_NICKNAME = ariane133
export DESIGN_NAME = ariane
export PLATFORM = nangate45
export VERILOG_FILES = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/ariane.v \
./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export ABC_CLOCK_PERIOD_IN_PS = 2000
export ADDITIONAL_LEFS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fakeram45_256x16.lef
export ADDITIONAL_LIBS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fakeram45_256x16.lib
# These values must be multiples of placement site
export DIE_AREA = 0.0 0.0 2072.14 2119.88
export CORE_AREA = 10.07 9.94 2062.07 2109.94
export PLACE_PINS_ARGS = -exclude left:0-600 -exclude left:1500-2119.88 -exclude right:* -exclude top:* -exclude bottom:*
#export PLACE_PINS_ARGS = -exclude left:0-600 -exclude left:800-1560 -exclude right:* -exclude top:* -exclude bottom:*
export PLACE_DENSITY_LB_ADDON ?= 0.20
## Adding dont touch for this mdoules
export PRESERVE_CELLS = SyncSpRamBeNx64_00000008_00000100_0_2 \
limping_SyncSpRamBeNx64_00000008_00000100_0_2 \
SyncSpRamBeNx64_00000008_00000100_0_2_d45 \
SyncSpRamBeNx64_00000008_00000100_0_2_d44
Flows/NanGate45/ariane133/scripts/OpenROAD/ariane133/config_hier.mk 0 → 100644
include $(dir $(DESIGN_CONFIG))/config.mk
#export FLOW_VARIANT = hier
export FLOW_VARIANT ?= hier_rtlmp
export SYNTH_HIERARCHICAL = 1
export MAX_UNGROUP_SIZE = 100
export RTLMP_FLOW = True
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_hier.sdc
export FLOORPLAN_DEF = ./results/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)/2_2_floorplan_io.def
export ABC_CLOCK_PERIOD_IN_PS = 4000
#
# RTL_MP Settings
export RTLMP_MAX_INST = 5000
export RTLMP_MIN_INST = 1000
export RTLMP_MAX_MACRO = 12
export RTLMP_MIN_MACRO = 4
# These values must be multiples of placement site
export DIE_AREA = 0 0 2000 2000
export CORE_AREA = 10 10 1990 1990
export PLACE_PINS_ARGS = -exclude left:0-600 -exclude left:1400-2000 -exclude right:* -exclude top:* -exclude bottom:*
export MACRO_PLACE_HALO = 5 5
export MACRO_PLACE_CHANNEL = 10 10
export PLACE_DENSITY = 0.55
export PRESERVE_CELLS = SyncSpRamBeNx64_00000008_00000100_0_2 \
limping_SyncSpRamBeNx64_00000008_00000100_0_2 \
SyncSpRamBeNx64_00000008_00000100_0_2_d45 \
SyncSpRamBeNx64_00000008_00000100_0_2_d44
Flows/NanGate45/ariane133/scripts/OpenROAD/ariane133/macros.v 0 → 100644
module SyncSpRamBeNx64_00000008_00000100_0_2
(
Clk_CI,
Rst_RBI,
CSel_SI,
WrEn_SI,
BEn_SI,
WrData_DI,
Addr_DI,
RdData_DO
);
input [7:0] BEn_SI; // byte-enable: ignore or use as needed
input [63:0] WrData_DI;
input [7:0] Addr_DI;
output [63:0] RdData_DO;
input Clk_CI;
input Rst_RBI; // reset: ignore or use as needed
input CSel_SI;
input WrEn_SI;
wire [63:0] RdData_DO;
wire csel_b,wren_b;
wire [15:0] WMaskIn, NotWMaskIn;
assign NotWMaskIn = 16'b0;
assign WMaskIn = ~NotWMaskIn;
assign wren_b = ~WrEn_SI; // active-low global-write-enable
assign csel_b = ~CSel_SI; // active-low chip-select-enable
fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[47:32]));
fakeram45_256x16 macro_mem_3 (.clk(Clk_CI),.rd_out(RdData_DO[63:48]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[63:48]));
endmodule // SyncSpRamBeNx64_00000008_00000100_0_2
// The valid_dirty_sram should be 4 macros, each 256x16. Instead, they only instantiated 1 256x16 macro
module limping_SyncSpRamBeNx64_00000008_00000100_0_2
(
Clk_CI,
Rst_RBI,
CSel_SI,
WrEn_SI,
BEn_SI,
WrData_DI,
Addr_DI,
RdData_DO
);
input [7:0] BEn_SI; // byte-enable: ignore or use as needed
input [63:0] WrData_DI;
input [7:0] Addr_DI;
output [63:0] RdData_DO;
input Clk_CI;
input Rst_RBI; // reset: ignore or use as needed
input CSel_SI;
input WrEn_SI;
wire [63:0] RdData_DO;
wire csel_b,wren_b;
wire [15:0] WMaskIn, NotWMaskIn;
assign NotWMaskIn = 16'b0;
assign WMaskIn = ~NotWMaskIn;
assign wren_b = ~WrEn_SI; // active-low global-write-enable
assign csel_b = ~CSel_SI; // active-low chip-select-enable
fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
// fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
// fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[47:32]));
// fakeram45_256x16 macro_mem_3 (.clk(Clk_CI),.rd_out(RdData_DO[63:48]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[63:48]));
assign RdData_DO[63:16] = 48'h0;
endmodule // limping_SyncSpRamBeNx64_00000008_00000100_0_2
module SyncSpRamBeNx64_00000008_00000100_0_2_d45
(
Clk_CI,
Rst_RBI,
CSel_SI,
WrEn_SI,
BEn_SI,
WrData_DI,
Addr_DI,
RdData_DO
);
input [7:0] BEn_SI; // byte-enable: ignore or use as needed
input [44:0] WrData_DI;
input [7:0] Addr_DI;
output [44:0] RdData_DO;
input Clk_CI;
input Rst_RBI; // reset: ignore or use as needed
input CSel_SI;
input WrEn_SI;
wire [47:0] RdData_DO_wire;
wire csel_b,wren_b;
wire [15:0] WMaskIn, NotWMaskIn;
assign NotWMaskIn = 16'b0;
assign WMaskIn = ~NotWMaskIn;
assign wren_b = ~WrEn_SI; // active-low global-write-enable
assign csel_b = ~CSel_SI; // active-low chip-select-enable
assign RdData_DO = RdData_DO_wire[44:0];
fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO_wire[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO_wire[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO_wire[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in({3'b000, WrData_DI[44:32]}));
endmodule // SyncSpRamBeNx64_00000008_00000100_0_2_d45
module SyncSpRamBeNx64_00000008_00000100_0_2_d44
(
Clk_CI,
Rst_RBI,
CSel_SI,
WrEn_SI,
BEn_SI,
WrData_DI,
Addr_DI,
RdData_DO
);
input [7:0] BEn_SI; // byte-enable: ignore or use as needed
input [43:0] WrData_DI;
input [7:0] Addr_DI;
output [43:0] RdData_DO;
input Clk_CI;
input Rst_RBI; // reset: ignore or use as needed
input CSel_SI;
input WrEn_SI;
wire [47:0] RdData_DO_wire;
wire csel_b,wren_b;
wire [15:0] WMaskIn, NotWMaskIn;
assign NotWMaskIn = 16'b0;
assign WMaskIn = ~NotWMaskIn;
assign wren_b = ~WrEn_SI; // active-low global-write-enable
assign csel_b = ~CSel_SI; // active-low chip-select-enable
assign RdData_DO = RdData_DO_wire[43:0];
fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO_wire[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO_wire[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO_wire[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in({4'b0000, WrData_DI[43:32]}));
endmodule // SyncSpRamBeNx64_00000008_00000100_0_2_d44
README.md
......@@ -7,6 +7,7 @@
- [Enablements](#enablements) contains PDKs for open-source enablements such as NanGate45, ASAP7 and SKY130HD with FakeStack. Memories required by the designs are also included.
- [Flows](#flows) contains tool setups and runscripts for both proprietary and open-source SP&R tools such as Cadence Genus/Innovus and OpenROAD.
- [Code Elements](#code-elements) contains implementation of engines such as Clustering, Grouping, Gridding, Format translators required by Circuit Training flow.
- [Baseline for Circuit Training](#baseline-for-circuit-training) provides a competitive baseline for [Google Brain's Circuit Training](https://github.com/google-research/circuit_training).
- [FAQ](#faq)
- [Related Links](#related-links)
......@@ -173,6 +174,12 @@ while allowing soft macros (standard-cell clusters) to also find good locations.
<!--## **Reproducible Example Solutions** -->
## **Baseline for Circuit Training**
We provide a competitive baseline for [Google Brain's Circuit Training](https://github.com/google-research/circuit_training) by placing macros manually following similar rules as the RL agent. The example for Ariane133 implemented on NanGate45 is shown [here](https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/Flows/NanGate45/ariane133). We generate the manual macro placement in two steps:
(1) we call the [gridding](https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/CodeElements/Gridding) scripts to generate grid cells (27 x 27 in our case); (2) we manually place macros on the center of grid cells.
## **FAQ**
**Why are you doing this?**
- The challenges of data and benchmarking in EDA research have, in our view, been contributing factors in the controversy regarding the Nature work. The mission of the [TILOS AI Institute](https://tilos.ai/) includes finding solutions to these challenges -- in high-stakes applied optimization domains (such as IC EDA), and at community-scale. We hope that our effort will become an existence proof for transparency, reproducibility, and democratization of research in EDA. [We applaud and thank Cadence Design Systems for allowing their tool runscripts to be shared openly by researchers, enabling reproducibility of results obtained via use of Cadence tools.]
......
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