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macroplacement
Commit 853c5fe9 by Ravi Varadarajan
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Merge branch 'flow_scripts' of github.com:TILOS-AI-Institute/MacroPlacement into flow_scripts

parents 7d35fccb 7a6e4352
Showing with 2524 additions and 109 deletions
CodeElements/Clustering/test/rtl_mp/ariane.hgr.fix 0 → 100644
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CodeElements/Gridding/test/rtl_mp/ariane.hgr.instance → CodeElements/Clustering/test/rtl_mp/ariane.hgr.instance
......@@ -42,95 +42,95 @@ i_cache_subsystem/i_icache/sram_block\[3\].data_sram/macro_mem\[7\].i_ram 1 130
i_cache_subsystem/i_icache/sram_block\[3\].tag_sram/macro_mem\[0\].i_ram 1 1434.84 1423.04 1492.41 1556.04 W
i_cache_subsystem/i_icache/sram_block\[3\].tag_sram/macro_mem\[1\].i_ram 1 1434.84 1482.67 1492.41 1615.67 W
i_cache_subsystem/i_icache/sram_block\[3\].tag_sram/macro_mem\[2\].i_ram 1 1434.84 1542.3 1492.41 1675.3 W
i_cache_subsystem/i_nbdcache/sram_block\[0\].data_sram/macro_mem\[0\].i_ram 1 3.99 0 61.56 133
i_cache_subsystem/i_nbdcache/sram_block\[0\].data_sram/macro_mem\[1\].i_ram 1 3.99 59.63 61.56 192.63
i_cache_subsystem/i_nbdcache/sram_block\[0\].data_sram/macro_mem\[2\].i_ram 1 136.99 0 194.56 133
i_cache_subsystem/i_nbdcache/sram_block\[0\].data_sram/macro_mem\[3\].i_ram 1 136.99 59.63 194.56 192.63
i_cache_subsystem/i_nbdcache/sram_block\[0\].data_sram/macro_mem\[4\].i_ram 1 269.99 0 327.56 133
i_cache_subsystem/i_nbdcache/sram_block\[0\].data_sram/macro_mem\[5\].i_ram 1 3.99 119.26 61.56 252.26
i_cache_subsystem/i_nbdcache/sram_block\[0\].data_sram/macro_mem\[6\].i_ram 1 136.99 119.26 194.56 252.26
i_cache_subsystem/i_nbdcache/sram_block\[0\].data_sram/macro_mem\[7\].i_ram 1 269.99 119.26 327.56 252.26
i_cache_subsystem/i_nbdcache/sram_block\[0\].tag_sram/macro_mem\[0\].i_ram 1 3.99 178.89 61.56 311.89
i_cache_subsystem/i_nbdcache/sram_block\[0\].tag_sram/macro_mem\[1\].i_ram 1 136.99 178.89 194.56 311.89
i_cache_subsystem/i_nbdcache/sram_block\[0\].tag_sram/macro_mem\[2\].i_ram 1 269.99 178.89 327.56 311.89
i_cache_subsystem/i_nbdcache/sram_block\[1\].data_sram/macro_mem\[0\].i_ram 1 3.99 238.52 61.56 371.52
i_cache_subsystem/i_nbdcache/sram_block\[1\].data_sram/macro_mem\[1\].i_ram 1 3.99 298.15 61.56 431.15
i_cache_subsystem/i_nbdcache/sram_block\[1\].data_sram/macro_mem\[2\].i_ram 1 136.99 238.52 194.56 371.52
i_cache_subsystem/i_nbdcache/sram_block\[1\].data_sram/macro_mem\[3\].i_ram 1 136.99 298.15 194.56 431.15
i_cache_subsystem/i_nbdcache/sram_block\[1\].data_sram/macro_mem\[4\].i_ram 1 269.99 238.52 327.56 371.52
i_cache_subsystem/i_nbdcache/sram_block\[1\].data_sram/macro_mem\[5\].i_ram 1 3.99 357.78 61.56 490.78
i_cache_subsystem/i_nbdcache/sram_block\[1\].data_sram/macro_mem\[6\].i_ram 1 136.99 357.78 194.56 490.78
i_cache_subsystem/i_nbdcache/sram_block\[1\].data_sram/macro_mem\[7\].i_ram 1 269.99 357.78 327.56 490.78
i_cache_subsystem/i_nbdcache/sram_block\[1\].tag_sram/macro_mem\[0\].i_ram 1 3.99 417.41 61.56 550.41
i_cache_subsystem/i_nbdcache/sram_block\[1\].tag_sram/macro_mem\[1\].i_ram 1 136.99 417.41 194.56 550.41
i_cache_subsystem/i_nbdcache/sram_block\[1\].tag_sram/macro_mem\[2\].i_ram 1 269.99 417.41 327.56 550.41
i_cache_subsystem/i_nbdcache/sram_block\[2\].data_sram/macro_mem\[0\].i_ram 1 402.99 0 460.56 133
i_cache_subsystem/i_nbdcache/sram_block\[2\].data_sram/macro_mem\[1\].i_ram 1 402.99 59.63 460.56 192.63
i_cache_subsystem/i_nbdcache/sram_block\[2\].data_sram/macro_mem\[2\].i_ram 1 535.99 0 593.56 133
i_cache_subsystem/i_nbdcache/sram_block\[2\].data_sram/macro_mem\[3\].i_ram 1 535.99 59.63 593.56 192.63
i_cache_subsystem/i_nbdcache/sram_block\[2\].data_sram/macro_mem\[4\].i_ram 1 668.99 0 726.56 133
i_cache_subsystem/i_nbdcache/sram_block\[2\].data_sram/macro_mem\[5\].i_ram 1 402.99 119.26 460.56 252.26
i_cache_subsystem/i_nbdcache/sram_block\[2\].data_sram/macro_mem\[6\].i_ram 1 535.99 119.26 593.56 252.26
i_cache_subsystem/i_nbdcache/sram_block\[2\].data_sram/macro_mem\[7\].i_ram 1 668.99 119.26 726.56 252.26
i_cache_subsystem/i_nbdcache/sram_block\[2\].tag_sram/macro_mem\[0\].i_ram 1 402.99 178.89 460.56 311.89
i_cache_subsystem/i_nbdcache/sram_block\[2\].tag_sram/macro_mem\[1\].i_ram 1 535.99 178.89 593.56 311.89
i_cache_subsystem/i_nbdcache/sram_block\[2\].tag_sram/macro_mem\[2\].i_ram 1 668.99 178.89 726.56 311.89
i_cache_subsystem/i_nbdcache/sram_block\[3\].data_sram/macro_mem\[0\].i_ram 1 402.99 238.52 460.56 371.52
i_cache_subsystem/i_nbdcache/sram_block\[3\].data_sram/macro_mem\[1\].i_ram 1 402.99 298.15 460.56 431.15
i_cache_subsystem/i_nbdcache/sram_block\[3\].data_sram/macro_mem\[2\].i_ram 1 535.99 238.52 593.56 371.52
i_cache_subsystem/i_nbdcache/sram_block\[3\].data_sram/macro_mem\[3\].i_ram 1 535.99 298.15 593.56 431.15
i_cache_subsystem/i_nbdcache/sram_block\[3\].data_sram/macro_mem\[4\].i_ram 1 668.99 238.52 726.56 371.52
i_cache_subsystem/i_nbdcache/sram_block\[3\].data_sram/macro_mem\[5\].i_ram 1 402.99 357.78 460.56 490.78
i_cache_subsystem/i_nbdcache/sram_block\[3\].data_sram/macro_mem\[6\].i_ram 1 535.99 357.78 593.56 490.78
i_cache_subsystem/i_nbdcache/sram_block\[3\].data_sram/macro_mem\[7\].i_ram 1 668.99 357.78 726.56 490.78
i_cache_subsystem/i_nbdcache/sram_block\[3\].tag_sram/macro_mem\[0\].i_ram 1 402.99 417.41 460.56 550.41
i_cache_subsystem/i_nbdcache/sram_block\[3\].tag_sram/macro_mem\[1\].i_ram 1 535.99 417.41 593.56 550.41
i_cache_subsystem/i_nbdcache/sram_block\[3\].tag_sram/macro_mem\[2\].i_ram 1 668.99 417.41 726.56 550.41
i_cache_subsystem/i_nbdcache/sram_block\[4\].data_sram/macro_mem\[0\].i_ram 1 801.99 0 859.56 133
i_cache_subsystem/i_nbdcache/sram_block\[4\].data_sram/macro_mem\[1\].i_ram 1 801.99 59.63 859.56 192.63
i_cache_subsystem/i_nbdcache/sram_block\[4\].data_sram/macro_mem\[2\].i_ram 1 934.99 0 992.56 133
i_cache_subsystem/i_nbdcache/sram_block\[4\].data_sram/macro_mem\[3\].i_ram 1 934.99 59.63 992.56 192.63
i_cache_subsystem/i_nbdcache/sram_block\[4\].data_sram/macro_mem\[4\].i_ram 1 1067.99 0 1125.56 133
i_cache_subsystem/i_nbdcache/sram_block\[4\].data_sram/macro_mem\[5\].i_ram 1 801.99 119.26 859.56 252.26
i_cache_subsystem/i_nbdcache/sram_block\[4\].data_sram/macro_mem\[6\].i_ram 1 934.99 119.26 992.56 252.26
i_cache_subsystem/i_nbdcache/sram_block\[4\].data_sram/macro_mem\[7\].i_ram 1 1067.99 119.26 1125.56 252.26
i_cache_subsystem/i_nbdcache/sram_block\[4\].tag_sram/macro_mem\[0\].i_ram 1 801.99 178.89 859.56 311.89
i_cache_subsystem/i_nbdcache/sram_block\[4\].tag_sram/macro_mem\[1\].i_ram 1 934.99 178.89 992.56 311.89
i_cache_subsystem/i_nbdcache/sram_block\[4\].tag_sram/macro_mem\[2\].i_ram 1 1067.99 178.89 1125.56 311.89
i_cache_subsystem/i_nbdcache/sram_block\[5\].data_sram/macro_mem\[0\].i_ram 1 801.99 238.52 859.56 371.52
i_cache_subsystem/i_nbdcache/sram_block\[5\].data_sram/macro_mem\[1\].i_ram 1 801.99 298.15 859.56 431.15
i_cache_subsystem/i_nbdcache/sram_block\[5\].data_sram/macro_mem\[2\].i_ram 1 934.99 238.52 992.56 371.52
i_cache_subsystem/i_nbdcache/sram_block\[5\].data_sram/macro_mem\[3\].i_ram 1 934.99 298.15 992.56 431.15
i_cache_subsystem/i_nbdcache/sram_block\[5\].data_sram/macro_mem\[4\].i_ram 1 1067.99 238.52 1125.56 371.52
i_cache_subsystem/i_nbdcache/sram_block\[5\].data_sram/macro_mem\[5\].i_ram 1 801.99 357.78 859.56 490.78
i_cache_subsystem/i_nbdcache/sram_block\[5\].data_sram/macro_mem\[6\].i_ram 1 934.99 357.78 992.56 490.78
i_cache_subsystem/i_nbdcache/sram_block\[5\].data_sram/macro_mem\[7\].i_ram 1 1067.99 357.78 1125.56 490.78
i_cache_subsystem/i_nbdcache/sram_block\[5\].tag_sram/macro_mem\[0\].i_ram 1 801.99 417.41 859.56 550.41
i_cache_subsystem/i_nbdcache/sram_block\[5\].tag_sram/macro_mem\[1\].i_ram 1 934.99 417.41 992.56 550.41
i_cache_subsystem/i_nbdcache/sram_block\[5\].tag_sram/macro_mem\[2\].i_ram 1 1067.99 417.41 1125.56 550.41
i_cache_subsystem/i_nbdcache/sram_block\[6\].data_sram/macro_mem\[0\].i_ram 1 1200.99 0 1258.56 133
i_cache_subsystem/i_nbdcache/sram_block\[6\].data_sram/macro_mem\[1\].i_ram 1 1200.99 59.63 1258.56 192.63
i_cache_subsystem/i_nbdcache/sram_block\[6\].data_sram/macro_mem\[2\].i_ram 1 1333.99 0 1391.56 133
i_cache_subsystem/i_nbdcache/sram_block\[6\].data_sram/macro_mem\[3\].i_ram 1 1333.99 59.63 1391.56 192.63
i_cache_subsystem/i_nbdcache/sram_block\[6\].data_sram/macro_mem\[4\].i_ram 1 1466.99 0 1524.56 133
i_cache_subsystem/i_nbdcache/sram_block\[6\].data_sram/macro_mem\[5\].i_ram 1 1200.99 119.26 1258.56 252.26
i_cache_subsystem/i_nbdcache/sram_block\[6\].data_sram/macro_mem\[6\].i_ram 1 1333.99 119.26 1391.56 252.26
i_cache_subsystem/i_nbdcache/sram_block\[6\].data_sram/macro_mem\[7\].i_ram 1 1466.99 119.26 1524.56 252.26
i_cache_subsystem/i_nbdcache/sram_block\[6\].tag_sram/macro_mem\[0\].i_ram 1 1200.99 178.89 1258.56 311.89
i_cache_subsystem/i_nbdcache/sram_block\[6\].tag_sram/macro_mem\[1\].i_ram 1 1333.99 178.89 1391.56 311.89
i_cache_subsystem/i_nbdcache/sram_block\[6\].tag_sram/macro_mem\[2\].i_ram 1 1466.99 178.89 1524.56 311.89
i_cache_subsystem/i_nbdcache/sram_block\[7\].data_sram/macro_mem\[0\].i_ram 1 1200.99 238.52 1258.56 371.52
i_cache_subsystem/i_nbdcache/sram_block\[7\].data_sram/macro_mem\[1\].i_ram 1 1333.99 238.52 1391.56 371.52
i_cache_subsystem/i_nbdcache/sram_block\[7\].data_sram/macro_mem\[2\].i_ram 1 1466.99 238.52 1524.56 371.52
i_cache_subsystem/i_nbdcache/sram_block\[7\].data_sram/macro_mem\[3\].i_ram 1 1200.99 298.15 1258.56 431.15
i_cache_subsystem/i_nbdcache/sram_block\[7\].data_sram/macro_mem\[4\].i_ram 1 1333.99 298.15 1391.56 431.15
i_cache_subsystem/i_nbdcache/sram_block\[7\].data_sram/macro_mem\[5\].i_ram 1 1466.99 298.15 1524.56 431.15
i_cache_subsystem/i_nbdcache/sram_block\[7\].data_sram/macro_mem\[6\].i_ram 1 1200.99 357.78 1258.56 490.78
i_cache_subsystem/i_nbdcache/sram_block\[7\].data_sram/macro_mem\[7\].i_ram 1 1333.99 357.78 1391.56 490.78
i_cache_subsystem/i_nbdcache/sram_block\[7\].tag_sram/macro_mem\[0\].i_ram 1 1466.99 357.78 1524.56 490.78
i_cache_subsystem/i_nbdcache/sram_block\[7\].tag_sram/macro_mem\[1\].i_ram 1 1200.99 417.41 1258.56 550.41
i_cache_subsystem/i_nbdcache/sram_block\[7\].tag_sram/macro_mem\[2\].i_ram 1 1333.99 417.41 1391.56 550.41
i_cache_subsystem/i_nbdcache/valid_dirty_sram/macro_mem\[0\].i_ram 1 1466.99 417.41 1524.56 550.41
i_cache_subsystem/i_nbdcache/sram_block\[0\].data_sram/macro_mem\[0\].i_ram 1 3.99 0 61.56 133 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[0\].data_sram/macro_mem\[1\].i_ram 1 3.99 59.63 61.56 192.63 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[0\].data_sram/macro_mem\[2\].i_ram 1 136.99 0 194.56 133 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[0\].data_sram/macro_mem\[3\].i_ram 1 136.99 59.63 194.56 192.63 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[0\].data_sram/macro_mem\[4\].i_ram 1 269.99 0 327.56 133 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[0\].data_sram/macro_mem\[5\].i_ram 1 3.99 119.26 61.56 252.26 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[0\].data_sram/macro_mem\[6\].i_ram 1 136.99 119.26 194.56 252.26 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[0\].data_sram/macro_mem\[7\].i_ram 1 269.99 119.26 327.56 252.26 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[0\].tag_sram/macro_mem\[0\].i_ram 1 3.99 178.89 61.56 311.89 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[0\].tag_sram/macro_mem\[1\].i_ram 1 136.99 178.89 194.56 311.89 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[0\].tag_sram/macro_mem\[2\].i_ram 1 269.99 178.89 327.56 311.89 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[1\].data_sram/macro_mem\[0\].i_ram 1 3.99 238.52 61.56 371.52 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[1\].data_sram/macro_mem\[1\].i_ram 1 3.99 298.15 61.56 431.15 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[1\].data_sram/macro_mem\[2\].i_ram 1 136.99 238.52 194.56 371.52 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[1\].data_sram/macro_mem\[3\].i_ram 1 136.99 298.15 194.56 431.15 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[1\].data_sram/macro_mem\[4\].i_ram 1 269.99 238.52 327.56 371.52 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[1\].data_sram/macro_mem\[5\].i_ram 1 3.99 357.78 61.56 490.78 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[1\].data_sram/macro_mem\[6\].i_ram 1 136.99 357.78 194.56 490.78 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[1\].data_sram/macro_mem\[7\].i_ram 1 269.99 357.78 327.56 490.78 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[1\].tag_sram/macro_mem\[0\].i_ram 1 3.99 417.41 61.56 550.41 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[1\].tag_sram/macro_mem\[1\].i_ram 1 136.99 417.41 194.56 550.41 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[1\].tag_sram/macro_mem\[2\].i_ram 1 269.99 417.41 327.56 550.41 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[2\].data_sram/macro_mem\[0\].i_ram 1 402.99 0 460.56 133 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[2\].data_sram/macro_mem\[1\].i_ram 1 402.99 59.63 460.56 192.63 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[2\].data_sram/macro_mem\[2\].i_ram 1 535.99 0 593.56 133 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[2\].data_sram/macro_mem\[3\].i_ram 1 535.99 59.63 593.56 192.63 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[2\].data_sram/macro_mem\[4\].i_ram 1 668.99 0 726.56 133 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[2\].data_sram/macro_mem\[5\].i_ram 1 402.99 119.26 460.56 252.26 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[2\].data_sram/macro_mem\[6\].i_ram 1 535.99 119.26 593.56 252.26 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[2\].data_sram/macro_mem\[7\].i_ram 1 668.99 119.26 726.56 252.26 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[2\].tag_sram/macro_mem\[0\].i_ram 1 402.99 178.89 460.56 311.89 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[2\].tag_sram/macro_mem\[1\].i_ram 1 535.99 178.89 593.56 311.89 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[2\].tag_sram/macro_mem\[2\].i_ram 1 668.99 178.89 726.56 311.89 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[3\].data_sram/macro_mem\[0\].i_ram 1 402.99 238.52 460.56 371.52 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[3\].data_sram/macro_mem\[1\].i_ram 1 402.99 298.15 460.56 431.15 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[3\].data_sram/macro_mem\[2\].i_ram 1 535.99 238.52 593.56 371.52 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[3\].data_sram/macro_mem\[3\].i_ram 1 535.99 298.15 593.56 431.15 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[3\].data_sram/macro_mem\[4\].i_ram 1 668.99 238.52 726.56 371.52 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[3\].data_sram/macro_mem\[5\].i_ram 1 402.99 357.78 460.56 490.78 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[3\].data_sram/macro_mem\[6\].i_ram 1 535.99 357.78 593.56 490.78 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[3\].data_sram/macro_mem\[7\].i_ram 1 668.99 357.78 726.56 490.78 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[3\].tag_sram/macro_mem\[0\].i_ram 1 402.99 417.41 460.56 550.41 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[3\].tag_sram/macro_mem\[1\].i_ram 1 535.99 417.41 593.56 550.41 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[3\].tag_sram/macro_mem\[2\].i_ram 1 668.99 417.41 726.56 550.41 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[4\].data_sram/macro_mem\[0\].i_ram 1 801.99 0 859.56 133 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[4\].data_sram/macro_mem\[1\].i_ram 1 801.99 59.63 859.56 192.63 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[4\].data_sram/macro_mem\[2\].i_ram 1 934.99 0 992.56 133 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[4\].data_sram/macro_mem\[3\].i_ram 1 934.99 59.63 992.56 192.63 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[4\].data_sram/macro_mem\[4\].i_ram 1 1067.99 0 1125.56 133 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[4\].data_sram/macro_mem\[5\].i_ram 1 801.99 119.26 859.56 252.26 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[4\].data_sram/macro_mem\[6\].i_ram 1 934.99 119.26 992.56 252.26 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[4\].data_sram/macro_mem\[7\].i_ram 1 1067.99 119.26 1125.56 252.26 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[4\].tag_sram/macro_mem\[0\].i_ram 1 801.99 178.89 859.56 311.89 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[4\].tag_sram/macro_mem\[1\].i_ram 1 934.99 178.89 992.56 311.89 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[4\].tag_sram/macro_mem\[2\].i_ram 1 1067.99 178.89 1125.56 311.89 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[5\].data_sram/macro_mem\[0\].i_ram 1 801.99 238.52 859.56 371.52 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[5\].data_sram/macro_mem\[1\].i_ram 1 801.99 298.15 859.56 431.15 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[5\].data_sram/macro_mem\[2\].i_ram 1 934.99 238.52 992.56 371.52 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[5\].data_sram/macro_mem\[3\].i_ram 1 934.99 298.15 992.56 431.15 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[5\].data_sram/macro_mem\[4\].i_ram 1 1067.99 238.52 1125.56 371.52 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[5\].data_sram/macro_mem\[5\].i_ram 1 801.99 357.78 859.56 490.78 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[5\].data_sram/macro_mem\[6\].i_ram 1 934.99 357.78 992.56 490.78 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[5\].data_sram/macro_mem\[7\].i_ram 1 1067.99 357.78 1125.56 490.78 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[5\].tag_sram/macro_mem\[0\].i_ram 1 801.99 417.41 859.56 550.41 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[5\].tag_sram/macro_mem\[1\].i_ram 1 934.99 417.41 992.56 550.41 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[5\].tag_sram/macro_mem\[2\].i_ram 1 1067.99 417.41 1125.56 550.41 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[6\].data_sram/macro_mem\[0\].i_ram 1 1200.99 0 1258.56 133 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[6\].data_sram/macro_mem\[1\].i_ram 1 1200.99 59.63 1258.56 192.63 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[6\].data_sram/macro_mem\[2\].i_ram 1 1333.99 0 1391.56 133 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[6\].data_sram/macro_mem\[3\].i_ram 1 1333.99 59.63 1391.56 192.63 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[6\].data_sram/macro_mem\[4\].i_ram 1 1466.99 0 1524.56 133 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[6\].data_sram/macro_mem\[5\].i_ram 1 1200.99 119.26 1258.56 252.26 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[6\].data_sram/macro_mem\[6\].i_ram 1 1333.99 119.26 1391.56 252.26 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[6\].data_sram/macro_mem\[7\].i_ram 1 1466.99 119.26 1524.56 252.26 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[6\].tag_sram/macro_mem\[0\].i_ram 1 1200.99 178.89 1258.56 311.89 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[6\].tag_sram/macro_mem\[1\].i_ram 1 1333.99 178.89 1391.56 311.89 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[6\].tag_sram/macro_mem\[2\].i_ram 1 1466.99 178.89 1524.56 311.89 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[7\].data_sram/macro_mem\[0\].i_ram 1 1200.99 238.52 1258.56 371.52 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[7\].data_sram/macro_mem\[1\].i_ram 1 1333.99 238.52 1391.56 371.52 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[7\].data_sram/macro_mem\[2\].i_ram 1 1466.99 238.52 1524.56 371.52 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[7\].data_sram/macro_mem\[3\].i_ram 1 1200.99 298.15 1258.56 431.15 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[7\].data_sram/macro_mem\[4\].i_ram 1 1333.99 298.15 1391.56 431.15 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[7\].data_sram/macro_mem\[5\].i_ram 1 1466.99 298.15 1524.56 431.15 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[7\].data_sram/macro_mem\[6\].i_ram 1 1200.99 357.78 1258.56 490.78 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[7\].data_sram/macro_mem\[7\].i_ram 1 1333.99 357.78 1391.56 490.78 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[7\].tag_sram/macro_mem\[0\].i_ram 1 1466.99 357.78 1524.56 490.78 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[7\].tag_sram/macro_mem\[1\].i_ram 1 1200.99 417.41 1258.56 550.41 MYR90
i_cache_subsystem/i_nbdcache/sram_block\[7\].tag_sram/macro_mem\[2\].i_ram 1 1333.99 417.41 1391.56 550.41 MYR90
i_cache_subsystem/i_nbdcache/valid_dirty_sram/macro_mem\[0\].i_ram 1 1466.99 417.41 1524.56 550.41 MYR90
commit_stage_i/FE_OFC3833_FE_DBTN21_csr_commit_commit_ex 0 546.63 774.2 547.2 775.6 N
commit_stage_i/FE_OFC3737_debug_mode 0 458.85 779.8 459.23 781.2 N
commit_stage_i/FE_OFC3665_commit_instr_id_commit_0__op__6 0 547.39 781.2 547.77 782.6 FS
CodeElements/CodeFlowIntegration/flow.py
......@@ -24,13 +24,14 @@ macro_lefs = ["./lefs/fakeram45_256x16.lef"]
##############################################
gridding_src_dir = '../Gridding/src'
tolerance = 0.01
min_n_rows = 30
min_n_cols = 30
min_n_rows = 10
min_n_cols = 10
max_n_rows = 50
max_n_cols = 50
max_rows_times_cols = 3000
halo_width = 5
gridding = GriddingLefDefInterface(gridding_src_dir, design, setup_file, tolerance,
gridding = GriddingLefDefInterface(gridding_src_dir, design, setup_file, tolerance, halo_width,
min_n_rows, min_n_cols, max_n_rows, max_n_cols,
max_rows_times_cols)
num_rows = gridding.GetNumRows()
......
CodeElements/Gridding/src/gridding.py
......@@ -187,12 +187,13 @@ def Gridding(macro_width_list, macro_height_list,
class GriddingLefDefInterface:
def __init__(self, src_dir, design, setup_file = "setup.tcl", tolerance = 0.01,
min_n_rows = 10, min_n_cols = 10, max_n_rows = 100, max_n_cols = 100,
max_rows_times_cols = 3000):
halo_width = 5.0, min_n_rows = 10, min_n_cols = 10, max_n_rows = 100,
max_n_cols = 100, max_rows_times_cols = 3000):
self.src_dir = src_dir
self.design = design
self.setup_file = setup_file
self.tolerance = tolerance
self.halo_width = halo_width
self.min_n_rows = min_n_rows
self.min_n_cols = min_n_cols
self.max_n_rows = max_n_rows
......@@ -267,8 +268,8 @@ class GriddingLefDefInterface:
for line in content:
items = line.split()
if (items[1] == "1"):
self.macro_width_list.append(float(items[4]) - float(items[2]))
self.macro_height_list.append(float(items[5]) - float(items[3]))
self.macro_width_list.append(float(items[4]) - float(items[2]) + 2 * self.halo_width)
self.macro_height_list.append(float(items[5]) - float(items[3]) + 2 * self.halo_width)
else:
self.num_std_cells += 1
......@@ -276,15 +277,6 @@ class GriddingLefDefInterface:
shutil.rmtree(rpt_dir)
if __name__ == "__main__":
# Just test
macro_width_list = [1, 2, 3.5, 3.5, 2.5]
macro_height_list = [1, 2, 3.5, 3.5, 2.5]
chip_width = 10
chip_height = 10
tolerance = 0.01
Gridding(macro_width_list, macro_height_list, chip_width, chip_height, tolerance)
......
CodeElements/Gridding/test/test_gridding.py
......@@ -11,6 +11,7 @@ if __name__ == '__main__':
design = "ariane"
src_dir = "../src"
setup_file = "setup.tcl"
tolerance = 0.1
GriddingLefDefInterface(src_dir, design, setup_file, tolerance)
tolerance = 0.01
halo_width = 5.0
GriddingLefDefInterface(src_dir, design, setup_file, tolerance, halo_width)
Flows/NanGate45/ariane133/README.md
We implement [Ariane design with 133 macros](../../../Testcases/ariane133) on the [NanGate45](../../../Enablements/NanGate45) platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R).
## *Macro Placement Generated by Cadence Flow-1*
The screenshot of the design using Cadence Flow-1 on Nangate45 enablement is shown below
<img src="./screenshots/Ariane133_Innovus.png" alt="ariane133_cadence" width="400"/>
## *Macro Placement Generated by ORFS*
The screenshot of the design using ORFS on Nangate45 enablement is shown below
<img src="./screenshots/Ariane133_ORFS.png" alt="ariane136_orfs" width="400"/>
## *Baseline Macro Placement Generated by Human*
The screenshot of the design using Cadence tool for standard cell placement and routing on Nangate45 enablement is shown below
<img src="./screenshots/manual_ariane133_Innovus.png" alt="ariane133_cadence" width="400"/>
The manual macro placement is provided in [manual_floorplan.def](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/Flows/NanGate45/ariane133/def/manual_floorplan.def).
We generate the manual macro placement in two steps:
(1) we call the [gridding](https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/CodeElements/Gridding) scripts to generate grid cells (27 x 27 in our case); (2) we manually place macros on the center of grid cells.
The macro placement can be a competitive baseline for [Circuit Training](https://github.com/google-research/circuit_training).
The metrics after different physical design stages are shown below.
Note that (1) we set the activity factor to 0.2 in our flow; (2) the standard cell area does not include physical cells; (3) In order to match [Nature paper](https://www.nature.com/articles/s41586-021-03544-w), we adjust the pin positions to occupy about 60% of the left boundary.
<table class="tg">
<thead>
<tr>
<th class="tg-0lax">Stage in Physcial Design</th>
<th class="tg-0lax">Core Area (um^2)</th>
<th class="tg-0lax">Standard Cell Area (um^2)</th>
<th class="tg-0lax">Total Power (mW)</th>
<th class="tg-0lax">Wirelength (m)</th>
<th class="tg-0lax">WNS (ps)</th>
<th class="tg-0lax">TNS (ns)</th>
</tr>
</thead>
<tbody>
<tr>
<td class="tg-0lax">Post-placement</td>
<td class="tg-0lax">2560080</td>
<td class="tg-0lax">215189</td>
<td class="tg-0lax">0.29</td>
<td class="tg-0lax">4.47</td>
<td class="tg-0lax">-2</td>
<td class="tg-0lax">-0.05</td>
</tr>
</tbody>
<tbody>
<tr>
<td class="tg-0lax">Post-CTS</td>
<td class="tg-0lax">2560080</td>
<td class="tg-0lax">216326</td>
<td class="tg-0lax">0.30</td>
<td class="tg-0lax">4.47</td>
<td class="tg-0lax">1</td>
<td class="tg-0lax">0</td>
</tr>
</tbody>
<tbody>
<tr>
<td class="tg-0lax">Post-Routing</td>
<td class="tg-0lax">2560080</td>
<td class="tg-0lax">216326</td>
<td class="tg-0lax">0.30</td>
<td class="tg-0lax">4.59</td>
<td class="tg-0lax">62</td>
<td class="tg-0lax">0</td>
</tr>
</tbody>
</table>
Flows/NanGate45/ariane133/def/manual_floorplan.def 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/NanGate45/ariane133/scripts/OpenROAD/ariane133/ariane.v 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/NanGate45/ariane133/scripts/OpenROAD/ariane133/config.mk 0 → 100644
export DESIGN_NICKNAME = ariane133
export DESIGN_NAME = ariane
export PLATFORM = nangate45
export VERILOG_FILES = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/ariane.v \
./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export ABC_CLOCK_PERIOD_IN_PS = 2000
export ADDITIONAL_LEFS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fakeram45_256x16.lef
export ADDITIONAL_LIBS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fakeram45_256x16.lib
# These values must be multiples of placement site
export DIE_AREA = 0.0 0.0 2072.14 2119.88
export CORE_AREA = 10.07 9.94 2062.07 2109.94
export PLACE_PINS_ARGS = -exclude left:0-600 -exclude left:1500-2119.88 -exclude right:* -exclude top:* -exclude bottom:*
#export PLACE_PINS_ARGS = -exclude left:0-600 -exclude left:800-1560 -exclude right:* -exclude top:* -exclude bottom:*
export PLACE_DENSITY_LB_ADDON ?= 0.20
## Adding dont touch for this mdoules
export PRESERVE_CELLS = SyncSpRamBeNx64_00000008_00000100_0_2 \
limping_SyncSpRamBeNx64_00000008_00000100_0_2 \
SyncSpRamBeNx64_00000008_00000100_0_2_d45 \
SyncSpRamBeNx64_00000008_00000100_0_2_d44
Flows/NanGate45/ariane133/scripts/OpenROAD/ariane133/config_hier.mk 0 → 100644
include $(dir $(DESIGN_CONFIG))/config.mk
#export FLOW_VARIANT = hier
export FLOW_VARIANT ?= hier_rtlmp
export SYNTH_HIERARCHICAL = 1
export MAX_UNGROUP_SIZE = 100
export RTLMP_FLOW = True
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_hier.sdc
export FLOORPLAN_DEF = ./results/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)/2_2_floorplan_io.def
export ABC_CLOCK_PERIOD_IN_PS = 4000
#
# RTL_MP Settings
export RTLMP_MAX_INST = 5000
export RTLMP_MIN_INST = 1000
export RTLMP_MAX_MACRO = 12
export RTLMP_MIN_MACRO = 4
# These values must be multiples of placement site
export DIE_AREA = 0 0 2000 2000
export CORE_AREA = 10 10 1990 1990
export PLACE_PINS_ARGS = -exclude left:0-600 -exclude left:1400-2000 -exclude right:* -exclude top:* -exclude bottom:*
export MACRO_PLACE_HALO = 5 5
export MACRO_PLACE_CHANNEL = 10 10
export PLACE_DENSITY = 0.55
export PRESERVE_CELLS = SyncSpRamBeNx64_00000008_00000100_0_2 \
limping_SyncSpRamBeNx64_00000008_00000100_0_2 \
SyncSpRamBeNx64_00000008_00000100_0_2_d45 \
SyncSpRamBeNx64_00000008_00000100_0_2_d44
Flows/NanGate45/ariane133/scripts/OpenROAD/ariane133/constraint.sdc 0 → 100644
#period set in nano-seconds - currently: 4ns = 250 MHz freq
create_clock [get_ports clk_i] -name core_clock -period 4
#
#set_input_delay -clock core_clock 0 [get_ports clk_i]
set_input_delay -clock core_clock 0 [get_ports rst_ni]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[63]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[62]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[61]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[60]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[59]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[58]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[57]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[56]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[55]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[54]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[53]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[52]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[51]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[50]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[49]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[48]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[47]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[46]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[45]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[44]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[43]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[42]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[41]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[40]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[39]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[38]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[37]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[36]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[35]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[34]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[33]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[32]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[31]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[30]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[29]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[28]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[27]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[26]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[25]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[24]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[23]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[22]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[21]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[20]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[19]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[18]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[17]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[16]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[15]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[14]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[13]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[12]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[11]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[10]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[9]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[8]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[7]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[6]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[5]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[4]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[3]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[2]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[1]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[0]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[63]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[62]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[61]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[60]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[59]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[58]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[57]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[56]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[55]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[54]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[53]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[52]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[51]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[50]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[49]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[48]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[47]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[46]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[45]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[44]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[43]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[42]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[41]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[40]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[39]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[38]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[37]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[36]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[35]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[34]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[33]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[32]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[31]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[30]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[29]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[28]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[27]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[26]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[25]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[24]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[23]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[22]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[21]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[20]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[19]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[18]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[17]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[16]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[15]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[14]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[13]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[12]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[11]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[10]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[9]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[8]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[7]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[6]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[5]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[4]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[3]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[2]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[1]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[0]}]
set_input_delay -clock core_clock 0 [get_ports {irq_i[1]}]
set_input_delay -clock core_clock 0 [get_ports {irq_i[0]}]
set_input_delay -clock core_clock 0 [get_ports ipi_i]
set_input_delay -clock core_clock 0 [get_ports time_irq_i]
set_input_delay -clock core_clock 0 [get_ports debug_req_i]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[81]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[80]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[79]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[78]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[77]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[76]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[75]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[74]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[73]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[72]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[71]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[70]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[69]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[68]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[67]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[66]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[65]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[64]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[63]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[62]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[61]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[60]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[59]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[58]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[57]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[56]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[55]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[54]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[53]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[52]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[51]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[50]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[49]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[48]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[47]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[46]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[45]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[44]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[43]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[42]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[41]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[40]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[39]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[38]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[37]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[36]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[35]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[34]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[33]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[32]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[31]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[30]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[29]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[28]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[27]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[26]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[25]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[24]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[23]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[22]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[21]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[20]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[19]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[18]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[17]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[16]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[15]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[14]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[13]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[12]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[11]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[10]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[9]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[8]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[7]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[6]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[5]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[4]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[3]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[2]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[1]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[0]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[277]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[276]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[275]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[274]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[273]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[272]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[271]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[270]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[269]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[268]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[267]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[266]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[265]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[264]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[263]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[262]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[261]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[260]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[259]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[258]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[257]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[256]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[255]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[254]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[253]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[252]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[251]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[250]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[249]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[248]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[247]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[246]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[245]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[244]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[243]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[242]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[241]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[240]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[239]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[238]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[237]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[236]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[235]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[234]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[233]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[232]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[231]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[230]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[229]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[228]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[227]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[226]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[225]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[224]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[223]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[222]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[221]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[220]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[219]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[218]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[217]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[216]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[215]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[214]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[213]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[212]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[211]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[210]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[209]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[208]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[207]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[206]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[205]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[204]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[203]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[202]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[201]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[200]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[199]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[198]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[197]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[196]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[195]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[194]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[193]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[192]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[191]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[190]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[189]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[188]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[187]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[186]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[185]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[184]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[183]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[182]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[181]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[180]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[179]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[178]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[177]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[176]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[175]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[174]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[173]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[172]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[171]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[170]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[169]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[168]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[167]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[166]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[165]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[164]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[163]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[162]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[161]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[160]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[159]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[158]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[157]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[156]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[155]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[154]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[153]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[152]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[151]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[150]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[149]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[148]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[147]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[146]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[145]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[144]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[143]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[142]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[141]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[140]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[139]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[138]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[137]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[136]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[135]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[134]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[133]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[132]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[131]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[130]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[129]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[128]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[127]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[126]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[125]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[124]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[123]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[122]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[121]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[120]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[119]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[118]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[117]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[116]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[115]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[114]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[113]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[112]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[111]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[110]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[109]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[108]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[107]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[106]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[105]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[104]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[103]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[102]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[101]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[100]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[99]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[98]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[97]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[96]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[95]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[94]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[93]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[92]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[91]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[90]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[89]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[88]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[87]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[86]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[85]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[84]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[83]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[82]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[81]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[80]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[79]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[78]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[77]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[76]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[75]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[74]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[73]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[72]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[71]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[70]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[69]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[68]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[67]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[66]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[65]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[64]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[63]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[62]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[61]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[60]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[59]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[58]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[57]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[56]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[55]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[54]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[53]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[52]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[51]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[50]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[49]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[48]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[47]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[46]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[45]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[44]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[43]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[42]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[41]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[40]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[39]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[38]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[37]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[36]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[35]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[34]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[33]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[32]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[31]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[30]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[29]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[28]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[27]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[26]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[25]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[24]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[23]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[22]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[21]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[20]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[19]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[18]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[17]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[16]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[15]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[14]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[13]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[12]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[11]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[10]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[9]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[8]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[7]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[6]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[5]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[4]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[3]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[2]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[1]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[0]}]
Flows/NanGate45/ariane133/scripts/OpenROAD/ariane133/constraint_hier.sdc 0 → 100644
create_clock [get_ports clk_i] -name core_clock -period 4 -waveform {0 2}
set_input_delay -clock core_clock 0 [get_ports clk_i]
set_input_delay -clock core_clock 0 [get_ports rst_ni]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[63]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[62]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[61]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[60]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[59]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[58]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[57]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[56]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[55]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[54]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[53]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[52]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[51]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[50]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[49]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[48]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[47]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[46]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[45]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[44]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[43]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[42]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[41]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[40]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[39]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[38]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[37]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[36]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[35]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[34]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[33]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[32]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[31]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[30]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[29]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[28]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[27]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[26]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[25]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[24]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[23]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[22]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[21]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[20]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[19]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[18]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[17]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[16]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[15]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[14]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[13]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[12]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[11]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[10]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[9]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[8]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[7]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[6]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[5]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[4]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[3]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[2]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[1]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[0]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[63]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[62]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[61]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[60]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[59]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[58]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[57]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[56]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[55]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[54]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[53]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[52]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[51]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[50]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[49]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[48]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[47]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[46]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[45]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[44]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[43]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[42]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[41]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[40]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[39]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[38]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[37]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[36]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[35]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[34]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[33]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[32]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[31]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[30]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[29]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[28]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[27]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[26]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[25]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[24]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[23]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[22]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[21]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[20]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[19]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[18]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[17]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[16]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[15]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[14]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[13]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[12]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[11]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[10]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[9]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[8]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[7]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[6]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[5]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[4]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[3]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[2]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[1]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[0]}]
set_input_delay -clock core_clock 0 [get_ports {irq_i[1]}]
set_input_delay -clock core_clock 0 [get_ports {irq_i[0]}]
set_input_delay -clock core_clock 0 [get_ports ipi_i]
set_input_delay -clock core_clock 0 [get_ports time_irq_i]
set_input_delay -clock core_clock 0 [get_ports debug_req_i]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[81]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[80]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[79]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[78]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[77]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[76]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[75]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[74]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[73]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[72]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[71]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[70]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[69]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[68]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[67]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[66]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[65]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[64]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[63]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[62]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[61]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[60]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[59]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[58]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[57]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[56]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[55]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[54]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[53]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[52]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[51]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[50]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[49]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[48]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[47]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[46]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[45]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[44]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[43]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[42]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[41]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[40]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[39]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[38]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[37]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[36]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[35]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[34]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[33]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[32]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[31]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[30]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[29]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[28]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[27]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[26]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[25]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[24]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[23]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[22]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[21]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[20]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[19]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[18]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[17]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[16]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[15]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[14]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[13]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[12]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[11]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[10]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[9]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[8]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[7]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[6]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[5]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[4]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[3]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[2]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[1]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[0]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[277]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[276]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[275]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[274]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[273]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[272]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[271]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[270]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[269]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[268]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[267]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[266]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[265]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[264]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[263]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[262]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[261]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[260]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[259]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[258]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[257]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[256]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[255]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[254]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[253]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[252]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[251]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[250]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[249]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[248]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[247]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[246]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[245]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[244]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[243]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[242]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[241]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[240]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[239]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[238]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[237]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[236]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[235]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[234]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[233]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[232]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[231]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[230]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[229]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[228]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[227]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[226]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[225]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[224]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[223]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[222]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[221]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[220]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[219]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[218]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[217]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[216]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[215]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[214]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[213]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[212]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[211]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[210]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[209]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[208]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[207]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[206]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[205]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[204]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[203]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[202]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[201]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[200]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[199]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[198]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[197]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[196]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[195]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[194]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[193]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[192]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[191]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[190]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[189]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[188]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[187]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[186]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[185]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[184]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[183]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[182]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[181]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[180]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[179]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[178]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[177]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[176]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[175]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[174]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[173]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[172]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[171]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[170]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[169]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[168]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[167]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[166]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[165]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[164]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[163]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[162]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[161]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[160]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[159]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[158]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[157]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[156]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[155]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[154]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[153]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[152]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[151]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[150]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[149]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[148]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[147]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[146]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[145]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[144]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[143]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[142]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[141]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[140]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[139]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[138]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[137]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[136]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[135]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[134]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[133]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[132]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[131]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[130]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[129]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[128]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[127]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[126]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[125]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[124]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[123]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[122]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[121]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[120]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[119]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[118]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[117]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[116]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[115]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[114]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[113]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[112]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[111]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[110]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[109]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[108]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[107]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[106]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[105]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[104]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[103]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[102]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[101]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[100]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[99]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[98]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[97]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[96]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[95]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[94]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[93]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[92]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[91]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[90]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[89]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[88]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[87]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[86]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[85]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[84]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[83]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[82]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[81]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[80]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[79]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[78]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[77]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[76]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[75]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[74]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[73]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[72]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[71]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[70]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[69]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[68]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[67]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[66]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[65]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[64]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[63]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[62]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[61]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[60]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[59]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[58]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[57]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[56]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[55]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[54]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[53]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[52]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[51]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[50]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[49]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[48]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[47]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[46]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[45]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[44]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[43]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[42]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[41]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[40]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[39]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[38]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[37]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[36]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[35]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[34]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[33]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[32]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[31]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[30]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[29]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[28]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[27]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[26]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[25]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[24]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[23]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[22]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[21]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[20]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[19]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[18]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[17]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[16]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[15]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[14]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[13]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[12]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[11]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[10]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[9]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[8]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[7]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[6]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[5]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[4]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[3]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[2]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[1]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[0]}]
Flows/NanGate45/ariane133/scripts/OpenROAD/ariane133/fakeram45_256x16.lef 0 → 100644
VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO fakeram45_256x16
FOREIGN fakeram45_256x16 0 0 ;
SYMMETRY X Y R90 ;
SIZE 57.570 BY 133.000 ;
CLASS BLOCK ;
PIN w_mask_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.065 0.070 2.135 ;
END
END w_mask_in[0]
PIN w_mask_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 4.165 0.070 4.235 ;
END
END w_mask_in[1]
PIN w_mask_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.265 0.070 6.335 ;
END
END w_mask_in[2]
PIN w_mask_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.365 0.070 8.435 ;
END
END w_mask_in[3]
PIN w_mask_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.465 0.070 10.535 ;
END
END w_mask_in[4]
PIN w_mask_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.565 0.070 12.635 ;
END
END w_mask_in[5]
PIN w_mask_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.665 0.070 14.735 ;
END
END w_mask_in[6]
PIN w_mask_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.765 0.070 16.835 ;
END
END w_mask_in[7]
PIN w_mask_in[8]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 18.865 0.070 18.935 ;
END
END w_mask_in[8]
PIN w_mask_in[9]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.965 0.070 21.035 ;
END
END w_mask_in[9]
PIN w_mask_in[10]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.065 0.070 23.135 ;
END
END w_mask_in[10]
PIN w_mask_in[11]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 25.165 0.070 25.235 ;
END
END w_mask_in[11]
PIN w_mask_in[12]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 27.265 0.070 27.335 ;
END
END w_mask_in[12]
PIN w_mask_in[13]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 29.365 0.070 29.435 ;
END
END w_mask_in[13]
PIN w_mask_in[14]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 31.465 0.070 31.535 ;
END
END w_mask_in[14]
PIN w_mask_in[15]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 33.565 0.070 33.635 ;
END
END w_mask_in[15]
PIN rd_out[0]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 34.615 0.070 34.685 ;
END
END rd_out[0]
PIN rd_out[1]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 36.715 0.070 36.785 ;
END
END rd_out[1]
PIN rd_out[2]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 38.815 0.070 38.885 ;
END
END rd_out[2]
PIN rd_out[3]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 40.915 0.070 40.985 ;
END
END rd_out[3]
PIN rd_out[4]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 43.015 0.070 43.085 ;
END
END rd_out[4]
PIN rd_out[5]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 45.115 0.070 45.185 ;
END
END rd_out[5]
PIN rd_out[6]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 47.215 0.070 47.285 ;
END
END rd_out[6]
PIN rd_out[7]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 49.315 0.070 49.385 ;
END
END rd_out[7]
PIN rd_out[8]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 51.415 0.070 51.485 ;
END
END rd_out[8]
PIN rd_out[9]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 53.515 0.070 53.585 ;
END
END rd_out[9]
PIN rd_out[10]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 55.615 0.070 55.685 ;
END
END rd_out[10]
PIN rd_out[11]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 57.715 0.070 57.785 ;
END
END rd_out[11]
PIN rd_out[12]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 59.815 0.070 59.885 ;
END
END rd_out[12]
PIN rd_out[13]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 61.915 0.070 61.985 ;
END
END rd_out[13]
PIN rd_out[14]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 64.015 0.070 64.085 ;
END
END rd_out[14]
PIN rd_out[15]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 66.115 0.070 66.185 ;
END
END rd_out[15]
PIN wd_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 67.165 0.070 67.235 ;
END
END wd_in[0]
PIN wd_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 69.265 0.070 69.335 ;
END
END wd_in[1]
PIN wd_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 71.365 0.070 71.435 ;
END
END wd_in[2]
PIN wd_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 73.465 0.070 73.535 ;
END
END wd_in[3]
PIN wd_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 75.565 0.070 75.635 ;
END
END wd_in[4]
PIN wd_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 77.665 0.070 77.735 ;
END
END wd_in[5]
PIN wd_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 79.765 0.070 79.835 ;
END
END wd_in[6]
PIN wd_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 81.865 0.070 81.935 ;
END
END wd_in[7]
PIN wd_in[8]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 83.965 0.070 84.035 ;
END
END wd_in[8]
PIN wd_in[9]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 86.065 0.070 86.135 ;
END
END wd_in[9]
PIN wd_in[10]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 88.165 0.070 88.235 ;
END
END wd_in[10]
PIN wd_in[11]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 90.265 0.070 90.335 ;
END
END wd_in[11]
PIN wd_in[12]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 92.365 0.070 92.435 ;
END
END wd_in[12]
PIN wd_in[13]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 94.465 0.070 94.535 ;
END
END wd_in[13]
PIN wd_in[14]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 96.565 0.070 96.635 ;
END
END wd_in[14]
PIN wd_in[15]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 98.665 0.070 98.735 ;
END
END wd_in[15]
PIN addr_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 99.715 0.070 99.785 ;
END
END addr_in[0]
PIN addr_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 101.815 0.070 101.885 ;
END
END addr_in[1]
PIN addr_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 103.915 0.070 103.985 ;
END
END addr_in[2]
PIN addr_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 106.015 0.070 106.085 ;
END
END addr_in[3]
PIN addr_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 108.115 0.070 108.185 ;
END
END addr_in[4]
PIN addr_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 110.215 0.070 110.285 ;
END
END addr_in[5]
PIN addr_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 112.315 0.070 112.385 ;
END
END addr_in[6]
PIN addr_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 114.415 0.070 114.485 ;
END
END addr_in[7]
PIN we_in
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 115.465 0.070 115.535 ;
END
END we_in
PIN ce_in
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 117.565 0.070 117.635 ;
END
END ce_in
PIN clk
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 119.665 0.070 119.735 ;
END
END clk
PIN VSS
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER metal4 ;
RECT 1.960 2.100 2.240 130.900 ;
RECT 5.320 2.100 5.600 130.900 ;
RECT 8.680 2.100 8.960 130.900 ;
RECT 12.040 2.100 12.320 130.900 ;
RECT 15.400 2.100 15.680 130.900 ;
RECT 18.760 2.100 19.040 130.900 ;
RECT 22.120 2.100 22.400 130.900 ;
RECT 25.480 2.100 25.760 130.900 ;
RECT 28.840 2.100 29.120 130.900 ;
RECT 32.200 2.100 32.480 130.900 ;
RECT 35.560 2.100 35.840 130.900 ;
RECT 38.920 2.100 39.200 130.900 ;
RECT 42.280 2.100 42.560 130.900 ;
RECT 45.640 2.100 45.920 130.900 ;
RECT 49.000 2.100 49.280 130.900 ;
RECT 52.360 2.100 52.640 130.900 ;
END
END VSS
PIN VDD
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER metal4 ;
RECT 3.640 2.100 3.920 130.900 ;
RECT 7.000 2.100 7.280 130.900 ;
RECT 10.360 2.100 10.640 130.900 ;
RECT 13.720 2.100 14.000 130.900 ;
RECT 17.080 2.100 17.360 130.900 ;
RECT 20.440 2.100 20.720 130.900 ;
RECT 23.800 2.100 24.080 130.900 ;
RECT 27.160 2.100 27.440 130.900 ;
RECT 30.520 2.100 30.800 130.900 ;
RECT 33.880 2.100 34.160 130.900 ;
RECT 37.240 2.100 37.520 130.900 ;
RECT 40.600 2.100 40.880 130.900 ;
RECT 43.960 2.100 44.240 130.900 ;
RECT 47.320 2.100 47.600 130.900 ;
RECT 50.680 2.100 50.960 130.900 ;
RECT 54.040 2.100 54.320 130.900 ;
END
END VDD
OBS
LAYER metal1 ;
RECT 0 0 57.570 133.000 ;
LAYER metal2 ;
RECT 0 0 57.570 133.000 ;
LAYER metal3 ;
RECT 0.070 0 57.570 133.000 ;
RECT 0 0.000 0.070 2.065 ;
RECT 0 2.135 0.070 4.165 ;
RECT 0 4.235 0.070 6.265 ;
RECT 0 6.335 0.070 8.365 ;
RECT 0 8.435 0.070 10.465 ;
RECT 0 10.535 0.070 12.565 ;
RECT 0 12.635 0.070 14.665 ;
RECT 0 14.735 0.070 16.765 ;
RECT 0 16.835 0.070 18.865 ;
RECT 0 18.935 0.070 20.965 ;
RECT 0 21.035 0.070 23.065 ;
RECT 0 23.135 0.070 25.165 ;
RECT 0 25.235 0.070 27.265 ;
RECT 0 27.335 0.070 29.365 ;
RECT 0 29.435 0.070 31.465 ;
RECT 0 31.535 0.070 33.565 ;
RECT 0 33.635 0.070 34.615 ;
RECT 0 34.685 0.070 36.715 ;
RECT 0 36.785 0.070 38.815 ;
RECT 0 38.885 0.070 40.915 ;
RECT 0 40.985 0.070 43.015 ;
RECT 0 43.085 0.070 45.115 ;
RECT 0 45.185 0.070 47.215 ;
RECT 0 47.285 0.070 49.315 ;
RECT 0 49.385 0.070 51.415 ;
RECT 0 51.485 0.070 53.515 ;
RECT 0 53.585 0.070 55.615 ;
RECT 0 55.685 0.070 57.715 ;
RECT 0 57.785 0.070 59.815 ;
RECT 0 59.885 0.070 61.915 ;
RECT 0 61.985 0.070 64.015 ;
RECT 0 64.085 0.070 66.115 ;
RECT 0 66.185 0.070 67.165 ;
RECT 0 67.235 0.070 69.265 ;
RECT 0 69.335 0.070 71.365 ;
RECT 0 71.435 0.070 73.465 ;
RECT 0 73.535 0.070 75.565 ;
RECT 0 75.635 0.070 77.665 ;
RECT 0 77.735 0.070 79.765 ;
RECT 0 79.835 0.070 81.865 ;
RECT 0 81.935 0.070 83.965 ;
RECT 0 84.035 0.070 86.065 ;
RECT 0 86.135 0.070 88.165 ;
RECT 0 88.235 0.070 90.265 ;
RECT 0 90.335 0.070 92.365 ;
RECT 0 92.435 0.070 94.465 ;
RECT 0 94.535 0.070 96.565 ;
RECT 0 96.635 0.070 98.665 ;
RECT 0 98.735 0.070 99.715 ;
RECT 0 99.785 0.070 101.815 ;
RECT 0 101.885 0.070 103.915 ;
RECT 0 103.985 0.070 106.015 ;
RECT 0 106.085 0.070 108.115 ;
RECT 0 108.185 0.070 110.215 ;
RECT 0 110.285 0.070 112.315 ;
RECT 0 112.385 0.070 114.415 ;
RECT 0 114.485 0.070 115.465 ;
RECT 0 115.535 0.070 117.565 ;
RECT 0 117.635 0.070 119.665 ;
RECT 0 119.735 0.070 133.000 ;
LAYER metal4 ;
RECT 0 0 57.570 2.100 ;
RECT 0 130.900 57.570 133.000 ;
RECT 0.000 2.100 1.960 130.900 ;
RECT 2.240 2.100 3.640 130.900 ;
RECT 3.920 2.100 5.320 130.900 ;
RECT 5.600 2.100 7.000 130.900 ;
RECT 7.280 2.100 8.680 130.900 ;
RECT 8.960 2.100 10.360 130.900 ;
RECT 10.640 2.100 12.040 130.900 ;
RECT 12.320 2.100 13.720 130.900 ;
RECT 14.000 2.100 15.400 130.900 ;
RECT 15.680 2.100 17.080 130.900 ;
RECT 17.360 2.100 18.760 130.900 ;
RECT 19.040 2.100 20.440 130.900 ;
RECT 20.720 2.100 22.120 130.900 ;
RECT 22.400 2.100 23.800 130.900 ;
RECT 24.080 2.100 25.480 130.900 ;
RECT 25.760 2.100 27.160 130.900 ;
RECT 27.440 2.100 28.840 130.900 ;
RECT 29.120 2.100 30.520 130.900 ;
RECT 30.800 2.100 32.200 130.900 ;
RECT 32.480 2.100 33.880 130.900 ;
RECT 34.160 2.100 35.560 130.900 ;
RECT 35.840 2.100 37.240 130.900 ;
RECT 37.520 2.100 38.920 130.900 ;
RECT 39.200 2.100 40.600 130.900 ;
RECT 40.880 2.100 42.280 130.900 ;
RECT 42.560 2.100 43.960 130.900 ;
RECT 44.240 2.100 45.640 130.900 ;
RECT 45.920 2.100 47.320 130.900 ;
RECT 47.600 2.100 49.000 130.900 ;
RECT 49.280 2.100 50.680 130.900 ;
RECT 50.960 2.100 52.360 130.900 ;
RECT 52.640 2.100 54.040 130.900 ;
RECT 54.320 2.100 57.570 130.900 ;
LAYER OVERLAP ;
RECT 0 0 57.570 133.000 ;
END
END fakeram45_256x16
END LIBRARY
Flows/NanGate45/ariane133/scripts/OpenROAD/ariane133/fakeram45_256x16.lib 0 → 100644
library(fakeram45_256x16) {
technology (cmos);
delay_model : table_lookup;
revision : 1.0;
date : "2022-05-18 16:05:50Z";
comment : "SRAM";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
leakage_power_unit : "1uW";
nom_process : 1;
nom_temperature : 25.000;
nom_voltage : 1.1;
capacitive_load_unit (1,pf);
pulling_resistance_unit : "1kohm";
operating_conditions(tt_1.0_25.0) {
process : 1;
temperature : 25.000;
voltage : 1.1;
tree_type : balanced_tree;
}
/* default attributes */
default_cell_leakage_power : 0;
default_fanout_load : 1;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_max_transition : 0.227;
default_operating_conditions : tt_1.0_25.0;
default_leakage_power_density : 0.0;
/* additional header data */
slew_derate_from_library : 1.000;
slew_lower_threshold_pct_fall : 20.000;
slew_upper_threshold_pct_fall : 80.000;
slew_lower_threshold_pct_rise : 20.000;
slew_upper_threshold_pct_rise : 80.000;
input_threshold_pct_fall : 50.000;
input_threshold_pct_rise : 50.000;
output_threshold_pct_fall : 50.000;
output_threshold_pct_rise : 50.000;
lu_table_template(fakeram45_256x16_mem_out_delay_template) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1000, 1001");
index_2 ("1000, 1001");
}
lu_table_template(fakeram45_256x16_mem_out_slew_template) {
variable_1 : total_output_net_capacitance;
index_1 ("1000, 1001");
}
lu_table_template(fakeram45_256x16_constraint_template) {
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1 ("1000, 1001");
index_2 ("1000, 1001");
}
power_lut_template(fakeram45_256x16_energy_template_clkslew) {
variable_1 : input_transition_time;
index_1 ("1000, 1001");
}
power_lut_template(fakeram45_256x16_energy_template_sigslew) {
variable_1 : input_transition_time;
index_1 ("1000, 1001");
}
library_features(report_delay_calculation);
type (fakeram45_256x16_DATA) {
base_type : array ;
data_type : bit ;
bit_width : 16;
bit_from : 15;
bit_to : 0 ;
downto : true ;
}
type (fakeram45_256x16_ADDRESS) {
base_type : array ;
data_type : bit ;
bit_width : 8;
bit_from : 7;
bit_to : 0 ;
downto : true ;
}
cell(fakeram45_256x16) {
area : 7656.810;
interface_timing : true;
memory() {
type : ram;
address_width : 8;
word_width : 16;
}
pin(clk) {
direction : input;
capacitance : 0.025;
clock : true;
min_period : 0.210 ;
internal_power(){
rise_power(fakeram45_256x16_energy_template_clkslew) {
index_1 ("0.009, 0.227");
values ("2.355, 2.355")
}
fall_power(fakeram45_256x16_energy_template_clkslew) {
index_1 ("0.009, 0.227");
values ("2.355, 2.355")
}
}
}
bus(rd_out) {
bus_type : fakeram45_256x16_DATA;
direction : output;
max_capacitance : 0.500;
memory_read() {
address : addr_in;
}
timing() {
related_pin : "clk" ;
timing_type : rising_edge;
timing_sense : non_unate;
cell_rise(fakeram45_256x16_mem_out_delay_template) {
index_1 ("0.009, 0.227");
index_2 ("0.005, 0.500");
values ( \
"0.261, 0.261", \
"0.261, 0.261" \
)
}
cell_fall(fakeram45_256x16_mem_out_delay_template) {
index_1 ("0.009, 0.227");
index_2 ("0.005, 0.500");
values ( \
"0.261, 0.261", \
"0.261, 0.261" \
)
}
rise_transition(fakeram45_256x16_mem_out_slew_template) {
index_1 ("0.005, 0.500");
values ("0.009, 0.227")
}
fall_transition(fakeram45_256x16_mem_out_slew_template) {
index_1 ("0.005, 0.500");
values ("0.009, 0.227")
}
}
}
pin(we_in){
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
fall_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
}
}
pin(ce_in){
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
fall_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
}
}
bus(addr_in) {
bus_type : fakeram45_256x16_ADDRESS;
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
fall_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
}
}
bus(wd_in) {
bus_type : fakeram45_256x16_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
fall_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
}
internal_power(){
when : "(we_in)";
rise_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
fall_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
}
}
bus(w_mask_in) {
bus_type : fakeram45_256x16_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
fall_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
}
internal_power(){
when : "(we_in)";
rise_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
fall_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
}
}
cell_leakage_power : 432.350;
}
}
Flows/NanGate45/ariane133/scripts/OpenROAD/ariane133/macros.v 0 → 100644
module SyncSpRamBeNx64_00000008_00000100_0_2
(
Clk_CI,
Rst_RBI,
CSel_SI,
WrEn_SI,
BEn_SI,
WrData_DI,
Addr_DI,
RdData_DO
);
input [7:0] BEn_SI; // byte-enable: ignore or use as needed
input [63:0] WrData_DI;
input [7:0] Addr_DI;
output [63:0] RdData_DO;
input Clk_CI;
input Rst_RBI; // reset: ignore or use as needed
input CSel_SI;
input WrEn_SI;
wire [63:0] RdData_DO;
wire csel_b,wren_b;
wire [15:0] WMaskIn, NotWMaskIn;
assign NotWMaskIn = 16'b0;
assign WMaskIn = ~NotWMaskIn;
assign wren_b = ~WrEn_SI; // active-low global-write-enable
assign csel_b = ~CSel_SI; // active-low chip-select-enable
fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[47:32]));
fakeram45_256x16 macro_mem_3 (.clk(Clk_CI),.rd_out(RdData_DO[63:48]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[63:48]));
endmodule // SyncSpRamBeNx64_00000008_00000100_0_2
// The valid_dirty_sram should be 4 macros, each 256x16. Instead, they only instantiated 1 256x16 macro
module limping_SyncSpRamBeNx64_00000008_00000100_0_2
(
Clk_CI,
Rst_RBI,
CSel_SI,
WrEn_SI,
BEn_SI,
WrData_DI,
Addr_DI,
RdData_DO
);
input [7:0] BEn_SI; // byte-enable: ignore or use as needed
input [63:0] WrData_DI;
input [7:0] Addr_DI;
output [63:0] RdData_DO;
input Clk_CI;
input Rst_RBI; // reset: ignore or use as needed
input CSel_SI;
input WrEn_SI;
wire [63:0] RdData_DO;
wire csel_b,wren_b;
wire [15:0] WMaskIn, NotWMaskIn;
assign NotWMaskIn = 16'b0;
assign WMaskIn = ~NotWMaskIn;
assign wren_b = ~WrEn_SI; // active-low global-write-enable
assign csel_b = ~CSel_SI; // active-low chip-select-enable
fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
// fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
// fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[47:32]));
// fakeram45_256x16 macro_mem_3 (.clk(Clk_CI),.rd_out(RdData_DO[63:48]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[63:48]));
assign RdData_DO[63:16] = 48'h0;
endmodule // limping_SyncSpRamBeNx64_00000008_00000100_0_2
module SyncSpRamBeNx64_00000008_00000100_0_2_d45
(
Clk_CI,
Rst_RBI,
CSel_SI,
WrEn_SI,
BEn_SI,
WrData_DI,
Addr_DI,
RdData_DO
);
input [7:0] BEn_SI; // byte-enable: ignore or use as needed
input [44:0] WrData_DI;
input [7:0] Addr_DI;
output [44:0] RdData_DO;
input Clk_CI;
input Rst_RBI; // reset: ignore or use as needed
input CSel_SI;
input WrEn_SI;
wire [47:0] RdData_DO_wire;
wire csel_b,wren_b;
wire [15:0] WMaskIn, NotWMaskIn;
assign NotWMaskIn = 16'b0;
assign WMaskIn = ~NotWMaskIn;
assign wren_b = ~WrEn_SI; // active-low global-write-enable
assign csel_b = ~CSel_SI; // active-low chip-select-enable
assign RdData_DO = RdData_DO_wire[44:0];
fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO_wire[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO_wire[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO_wire[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in({3'b000, WrData_DI[44:32]}));
endmodule // SyncSpRamBeNx64_00000008_00000100_0_2_d45
module SyncSpRamBeNx64_00000008_00000100_0_2_d44
(
Clk_CI,
Rst_RBI,
CSel_SI,
WrEn_SI,
BEn_SI,
WrData_DI,
Addr_DI,
RdData_DO
);
input [7:0] BEn_SI; // byte-enable: ignore or use as needed
input [43:0] WrData_DI;
input [7:0] Addr_DI;
output [43:0] RdData_DO;
input Clk_CI;
input Rst_RBI; // reset: ignore or use as needed
input CSel_SI;
input WrEn_SI;
wire [47:0] RdData_DO_wire;
wire csel_b,wren_b;
wire [15:0] WMaskIn, NotWMaskIn;
assign NotWMaskIn = 16'b0;
assign WMaskIn = ~NotWMaskIn;
assign wren_b = ~WrEn_SI; // active-low global-write-enable
assign csel_b = ~CSel_SI; // active-low chip-select-enable
assign RdData_DO = RdData_DO_wire[43:0];
fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO_wire[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO_wire[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO_wire[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in({4'b0000, WrData_DI[43:32]}));
endmodule // SyncSpRamBeNx64_00000008_00000100_0_2_d44
README.md
......@@ -7,6 +7,7 @@
- [Enablements](#enablements) contains PDKs for open-source enablements such as NanGate45, ASAP7 and SKY130HD with FakeStack. Memories required by the designs are also included.
- [Flows](#flows) contains tool setups and runscripts for both proprietary and open-source SP&R tools such as Cadence Genus/Innovus and OpenROAD.
- [Code Elements](#code-elements) contains implementation of engines such as Clustering, Grouping, Gridding, Format translators required by Circuit Training flow.
- [Baseline for Circuit Training](#baseline-for-circuit-training) provides a competitive baseline for [Google Brain's Circuit Training](https://github.com/google-research/circuit_training).
- [FAQ](#faq)
- [Related Links](#related-links)
......@@ -173,6 +174,12 @@ while allowing soft macros (standard-cell clusters) to also find good locations.
<!--## **Reproducible Example Solutions** -->
## **Baseline for Circuit Training**
We provide a competitive baseline for [Google Brain's Circuit Training](https://github.com/google-research/circuit_training) by placing macros manually following similar rules as the RL agent. The example for Ariane133 implemented on NanGate45 is shown [here](https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/Flows/NanGate45/ariane133). We generate the manual macro placement in two steps:
(1) we call the [gridding](https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/CodeElements/Gridding) scripts to generate grid cells (27 x 27 in our case); (2) we manually place macros on the center of grid cells.
## **FAQ**
**Why are you doing this?**
- The challenges of data and benchmarking in EDA research have, in our view, been contributing factors in the controversy regarding the Nature work. The mission of the [TILOS AI Institute](https://tilos.ai/) includes finding solutions to these challenges -- in high-stakes applied optimization domains (such as IC EDA), and at community-scale. We hope that our effort will become an existence proof for transparency, reproducibility, and democratization of research in EDA. [We applaud and thank Cadence Design Systems for allowing their tool runscripts to be shared openly by researchers, enabling reproducibility of results obtained via use of Cadence tools.]
......@@ -210,4 +217,4 @@ while allowing soft macros (standard-cell clusters) to also find good locations.
*arXiv:2004.10746*, 2020. \[[paper](https://arxiv.org/pdf/2004.10746.pdf)\]
- Z. Jiang, E. Songhori, S. Wang, A. Goldie, A. Mirhoseini, et al., "Delving into Macro Placement with Reinforcement Learning", *MLCAD*, 2021. \[[paper](https://arxiv.org/pdf/2109.02587)\]
- A Gentle Introduction to Graph Neural Networks. [[Link](https://distill.pub/2021/gnn-intro/)]
- TILOS AI Institute. \[[link](https://tilos.ai/)\]
\ No newline at end of file
- TILOS AI Institute. \[[link](https://tilos.ai/)\]
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