-[136 macro (RTL files)](./Testcases/ariane136/) version is generated by instantiating 16-bit memories in Ariane netlist availabe in [lowRISC](https://github.com/lowRISC/ariane) GitHub repository.
-[RTL files for Ariane design with 136 macros](./Testcases/ariane136/) version is generated by instantiating 16-bit memories in Ariane netlist availabe in [lowRISC](https://github.com/lowRISC/ariane) GitHub repository.
-[133 macro (RTL files)](./Testcases/ariane133/) version is generated by updating the memory connection of 136 macro version.
-[RTL files for Ariane designs with 133 macros](./Testcases/ariane133/) version is generated by updating the memory connection of 136 macro version.
- MemPool (RTL)
- MemPool (RTL)
-[tile](./Testcases/mempool_tile/)
-[RTL files for Mempool tile design](./Testcases/mempool_tile/)
-group
-RTL files for Mempool group design
In this [Nature Paper](https://www.nature.com/articles/s41586-021-03544-w), authors have used Ariane design with 133 memory (256x16, single ported SRAM) macros as one of the test cases. We noticed synthesizing the available Ariane netlist in [lowRISC](https://github.com/lowRISC/ariane) GitHub repository with 256x16 memory results in Ariane design with 136 memory macros ([Here](./Testcases/ariane136/) we show how we instantiate memories for Ariane 136). [Here](./Testcases/ariane133/) we show how we convert the Ariane 136 design to Ariane 133 design. So, we added these two versions to our testcase list.
In this [Nature Paper](https://www.nature.com/articles/s41586-021-03544-w), authors have used Ariane design with 133 memory (256x16, single ported SRAM) macros as one of the test cases. We noticed synthesizing the available Ariane netlist in [lowRISC](https://github.com/lowRISC/ariane) GitHub repository with 256x16 memory results in Ariane design with 136 memory macros ([Here](./Testcases/ariane136/) we show how we instantiate memories for Ariane 136). [Here](./Testcases/ariane133/) we show how we convert the Ariane 136 design to Ariane 133 design. So, we added these two versions to our testcase list.
MemPool tile design is another testcase and we will be adding MemPool group in this list.
MemPool tile design is another testcase and we will be adding MemPool group in this list.
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@@ -28,8 +28,8 @@ Here we provide the detailed steps to generate the netlist for each test case. T
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@@ -28,8 +28,8 @@ Here we provide the detailed steps to generate the netlist for each test case. T
Open-source enablements NanGate45 and ASAP7 (will be adding) are utilized in our SP&R flow. The directory structure is *./Enablements/\<enablement\>/<lib\|lef>/*. Here
Open-source enablements NanGate45 and ASAP7 (will be adding) are utilized in our SP&R flow. The directory structure is *./Enablements/\<enablement\>/<lib\|lef>/*. Here
-*lib* directory contains all the required liberty files.
-*lib* directory contains all the required liberty files.
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@@ -40,9 +40,9 @@ Also, we provide steps to generate the fakerams.
...
@@ -40,9 +40,9 @@ Also, we provide steps to generate the fakerams.
## **Flows**
## **Flows**
Synthesis, place and route (SP&R) flow is available for each test case on each enablement. Here is the list
Synthesis, place and route (SP&R) flow is available for each test case on each enablement. Here is the list
- NanGate45
- NanGate45
-[Ariane 136](./Flows/NanGate45/ariane136/)
-[SP&R flows for Ariane design with 136 macros](./Flows/NanGate45/ariane136/)
-[Ariane 133](./Flows/NanGate45/ariane133/)
-[SP&R flows for Ariane design with 133 macros](./Flows/NanGate45/ariane133/)
-[MemPool tile](./Flows/NanGate45/mempool_tile/)
-[SP&R flows for MemPool tile design](./Flows/NanGate45/mempool_tile/)
- MemPool group
- MemPool group
Here we provide detailed information to run SP&R for each test case using the open-source tools Yosys (synthesis) and OpenROAD (P&R), and the commercial tools Cadence Genus (synthesis) and Innovus (P&R).
Here we provide detailed information to run SP&R for each test case using the open-source tools Yosys (synthesis) and OpenROAD (P&R), and the commercial tools Cadence Genus (synthesis) and Innovus (P&R).
