Merge pull request #13 from TILOS-AI-Institute/flow_scripts

Flow scripts

Enablements/SKY130HD/README.md

 # SKY130HD FakeStack (SKY130HD library, bsg_fakeram memory generation, 9M FakeStack)
 
-The SKY130HD enablement available in the OpenROAD-flow-script [GitHub repo](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd) is a five-metal stack enablement. However, memory macro has blockage till metal four, so a five-metal stack is not enough to route our macro dominant testcases.  
+The SKY130HD enablement available in the OpenROAD-flow-scripts [GitHub repo](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd) is a five-metal stack enablement. However, memory macros have blockages till metal four, so a five-metal stack is not enough to route our macro dominant testcases. So we extended SKY130HD to a nine-metal fake layer stack in the OpenROAD-flow-scripts [GitHub repo](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd_fakestack).   
 
 In this enablement, each of the five routing layers and four cut layers have different lef properties (.e.g, minimum spacing, width, enclosure, etc.). Consider the five layers of the metal stack are Ma, Mb, Mc, Md and Me, and the stack configuration is named as 1Ma_1Mb_1Mc_1Md_1Me. We replicate the first four metal layers to generate the nine-metal layer FakeStack where the configuration is 2Ma_2Mb_2Mc_2Md_1Me. We use this nine-metal layer FakeStack of SKY130HD as one of the enablements. The [getTechLef.tcl](./lef/genTechLef.tcl) can be used to generate a FakeStack of layer configuration x<sub>1</sub>Ma_x<sub>2</sub>Mb_x<sub>3</sub>Mc_x<sub>4</sub>Md_1Me, where x<sub>i</sub> is greater or equal to one.  
 

ExperimentalData/ASAP7/ariane133/flow-1.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,96097.520016,14798.94786,18679.584,122.83026656,846351.237004,0.017,0.000,0.00%,0.00%
+postCTS,96097.520016,14885.10108,18679.584,125.75048906,846693.813004,0.003,0.000,0.00%,0.00%
+postRoute,96097.520016,14885.10108,18679.584,125.39560805,882979.093001,0.392,0.000,,

ExperimentalData/ASAP7/ariane133/flow-2.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,96097.520016,15058.76346,18679.584,122.18595672,784606.016003,0.166,0.000,0.00%,0.00%
+postCTS,96097.520016,15147.6723,18679.584,125.92068189,787093.305003,0.093,0.000,0.00%,0.00%
+postRoute,96097.520016,15147.6723,18679.584,125.59083598,829020.993001,0.439,0.000,,

ExperimentalData/ASAP7/ariane136/flow-1.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,96097.520016,15400.91232,19100.928,495.49598741,785454.678004,-0.029,-24.435,0.00%,0.00%
+postCTS,96097.520016,15475.44528,19100.928,509.22803665,787571.523004,-0.009,-0.203,0.00%,0.00%
+postRoute,96097.520016,15475.44528,19100.928,507.75469510,822034.544001,0.158,0.000,,

ExperimentalData/ASAP7/ariane136/flow-2.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,96097.520016,15511.92444,19100.928,498.51691144,781280.586003,-0.001,-0.003,0.00%,0.00%
+postCTS,96097.520016,15607.13184,19100.928,512.15903633,784012.156003,0.000,0.000,0.00%,0.00%
+postRoute,96097.520016,15607.13184,19100.928,510.69447024,822271.292001,0.136,0.000,,

ExperimentalData/ASAP7/mempool_tile/flow-1.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,36103.040064,15180.44814,5056.128,21.24471568,762873.381997,0.000,0.000,0.00%,0.00%
+postCTS,36103.040064,15247.5453,5056.128,22.52928006,761193.433997,0.000,0.000,0.00%,0.00%
+postRoute,36103.040064,15247.5453,5056.128,22.27399583,774972.879001,0.000,0.000,,

ExperimentalData/ASAP7/mempool_tile/flow-2.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,36103.040064,15574.09356,5056.128,21.54321413,753412.272998,0.000,0.000,0.00%,0.01%
+postCTS,36103.040064,15643.37772,5056.128,22.82731511,753280.279998,0.000,0.000,0.00%,0.00%
+postRoute,36103.040064,15643.37772,5056.128,22.57264301,773204.674001,0.000,0.000,,

ExperimentalData/ASAP7/nvdla/flow-1.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,197173.27152,23798.4966,71909.376,531.91699806,1715148.49801,0.003,0.000,0.06%,0.03%
+postCTS,197173.27152,23945.37552,71909.376,551.64892826,1722068.03101,0.000,0.000,0.06%,0.04%
+postRoute,197173.27152,23945.37552,71909.376,550.96423932,1942449.882,0.057,0.000,,

ExperimentalData/ASAP7/nvdla/flow-2.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,197173.27152,24036.2235,71909.376,532.39541824,1743138.63398,0.002,0.000,0.01%,0.02%
+postCTS,197173.27152,24184.16676,71909.376,552.14891863,1750930.26298,-0.000,-0.000,0.01%,0.02%
+postRoute,197173.27152,24184.16676,71909.376,551.40287402,1976193.12301,0.007,0.000,,

ExperimentalData/NanGate45/ariane133/flow-1.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,2560079.9994,213764.25,1018355.73,284.62852769,3488909.35499,0.009,0.000,0.00%,0.00%
+postCTS,2560079.9994,214817.61,1018355.73,297.35888240,3492065.95099,0.000,0.000,0.00%,0.00%
+postRoute,2560079.9994,214817.61,1018355.73,296.83364873,3598577.48998,0.189,0.000,,

ExperimentalData/NanGate45/ariane133/flow-2.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,2560079.9994,214158.728,1018355.73,285.23630732,3350989.66049,-0.001,-0.001,0.00%,0.00%
+postCTS,2560079.9994,215579.168,1018355.73,298.54181245,3357757.07999,0.001,0.000,0.00%,0.00%
+postRoute,2560079.9994,215579.168,1018355.73,297.86236538,3456139.25998,0.219,0.000,,

ExperimentalData/NanGate45/ariane133/human-mp.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,2560079.9994,215188.946,1018355.73,285.96527395,4470831.80449,-0.002,-0.005,0.00%,0.00%
+postCTS,2560079.9994,216322.904,1018355.73,299.62675349,4472865.57499,0.001,0.000,0.00%,0.00%
+postRoute,2560079.9994,216322.904,1018355.73,298.60714372,4587140.94498,0.284,0.000,,

ExperimentalData/NanGate45/ariane136/flow-2.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,2889201.028,213695.356,1041326.16,287.97332711,3330254.53699,0.002,0.000,0.00%,0.00%
+postCTS,2889201.028,214793.138,1041326.16,301.29985160,3332648.92699,0.002,0.000,0.00%,0.00%
+postRoute,2889201.028,214793.138,1041326.16,300.65375412,3432693.12998,0.324,0.000,,

ExperimentalData/NanGate45/mempool_tile/flow-1.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,774461.5802,264248.124,187190.584,140.51533221,3506271.37999,-0.010,-1.299,0.02%,0.01%
+postCTS,774461.5802,266045.752,187190.584,150.20556938,3552128.46799,-0.002,-0.007,0.03%,0.02%
+postRoute,774461.5802,266045.752,187190.584,148.61808887,3659098.47498,0.000,0.000,,

ExperimentalData/NanGate45/mempool_tile/flow-2.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,774461.5802,268690.59,187190.584,130.05086857,3341855.36099,-0.016,-15.336,0.01%,0.00%
+postCTS,774461.5802,267433.474,187190.584,138.90206424,3371094.08449,-0.002,-0.014,0.02%,0.01%
+postRoute,774461.5802,267433.474,187190.584,137.36243913,3469346.77498,0.000,0.000,,

ExperimentalData/NanGate45/nvdla/flow-1.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,5443285.148,398495.398001,2325682.688,2299.63098715,8367478.37248,-0.004,-0.054,0.00%,0.22%
+postCTS,5443285.148,400072.512001,2325682.688,2379.80636434,8402350.48648,-0.001,-0.001,0.00%,0.23%
+postRoute,5443285.148,400072.512001,2325682.688,2360.43205487,8660699.94999,0.273,0.000,,

ExperimentalData/NanGate45/nvdla/flow-2.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,5443285.148,390273.072,2325682.688,2267.69844618,8107557.91799,-0.004,-0.076,0.00%,0.22%
+postCTS,5443285.148,392565.194,2325682.688,2348.70808302,8145767.35698,-0.001,-0.001,0.00%,0.23%
+postRoute,5443285.148,392565.194,2325682.688,2330.25575095,8392045.17499,0.252,0.000,,

ExperimentalData/SKY130HD/ariane133/flow-1.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,16744299.1104,1183218.5504,7130484.9504,866.68773608,8056999.11097,-0.448,-644.631,0.01%,0.01%
+postCTS,16744299.1104,1213501.344,7130484.9504,932.46432220,8073266.87797,-0.473,-352.170,0.01%,0.01%
+postRoute,16744299.1104,1213501.344,7130484.9504,939.59460138,8261537.56494,0.586,0.000,,

ExperimentalData/SKY130HD/ariane133/flow-2.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,16744299.1104,1170433.7888,7130484.9504,863.84345911,8709935.87598,-0.324,-368.436,0.01%,0.02%
+postCTS,16744299.1104,1207391.7344,7130484.9504,931.86777622,8738245.04698,-0.195,-59.482,0.01%,0.02%
+postRoute,16744299.1104,1207391.7344,7130484.9504,938.81119126,8956664.99497,0.230,0.000,,

ExperimentalData/SKY130HD/ariane136/flow-1.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,16654723.2,1189178.016,7291322.9568,875.81007243,8710676.93298,-0.292,-363.329,0.02%,0.01%
+postCTS,16654723.2,1231025.6512,7291322.9568,944.90255386,8744009.48298,-0.181,-99.309,0.02%,0.01%
+postRoute,16654723.2,1231025.6512,7291322.9568,951.73854496,8959640.94997,0.111,0.000,,

ExperimentalData/SKY130HD/ariane136/flow-2.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,16654723.2,1194319.1968,7291322.9568,874.19169168,8611445.37498,-0.229,-244.934,0.01%,0.01%
+postCTS,16654723.2,1225235.0976,7291322.9568,942.06029613,8627524.53198,-0.091,-22.313,0.01%,0.01%
+postRoute,16654723.2,1225235.0976,7291322.9568,948.62977664,8861308.97496,0.541,0.000,,

ExperimentalData/SKY130HD/mempool_tile/flow-1.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,6429976.8576,1447708.4672,1820533.536,184.04020440,8333707.76797,-1.179,-5196.1,0.10%,0.02%
+postCTS,6429976.8576,1412686.128,1820533.536,198.11752162,8351270.51697,-0.003,-0.005,0.10%,0.02%
+postRoute,6429976.8576,1412686.128,1820533.536,202.07672594,8595911.71992,-0.463,-1.429,,

ExperimentalData/SKY130HD/mempool_tile/flow-2.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,6429976.8576,1528768.7104,1820533.536,190.35360197,8661521.77797,-1.168,-5007.8,0.11%,0.02%
+postCTS,6429976.8576,1451291.904,1820533.536,201.37648037,8720119.31498,-0.006,-0.006,0.08%,0.02%
+postRoute,6429976.8576,1451291.904,1820533.536,205.43231067,9016989.62493,0.000,0.000,,

ExperimentalData/SKY130HD/nvdla/flow-1.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,45619217.4464,1744231.6064,20750141.0304,1849.74032724,18569558.0371,-0.009,-0.017,0.01%,0.21%
+postCTS,45619217.4464,1781506.1056,20750141.0304,1957.40155413,18609488.1811,0.000,0.000,0.01%,0.25%
+postRoute,45619217.4464,1781506.1056,20750141.0304,1967.99827737,19723347.4952,0.103,0.000,,

ExperimentalData/SKY130HD/nvdla/flow-2.csv

+Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)
+preCTS,45619217.4464,1743188.1056,20750141.0304,1849.49951078,18472179.3741,-0.005,-0.005,0.01%,0.23%
+postCTS,45619217.4464,1779942.1056,20750141.0304,1957.50349965,18526250.0451,-0.000,-0.000,0.01%,0.27%
+postRoute,45619217.4464,1779942.1056,20750141.0304,1967.56964849,19632402.9702,0.243,0.000,,

Flows/ASAP7/ariane133/scripts/cadence/run_invs.tcl

 # This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
 # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+setLibraryUnit -time 1.0ps
 source lib_setup.tcl
 source design_setup.tcl
 source mmmc_setup.tcl
@@ -76,6 +77,11 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc
 
+echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_pre_cts [extract_report preCTS]
+echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
+
 set_ccopt_property post_conditioning_enable_routing_eco 1
 set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
 setOptMode -unfixClkInstForOpt false
@@ -87,6 +93,11 @@ set_interactive_constraint_modes [all_constraint_modes -active]
 set_propagated_clock [all_clocks]
 set_clock_propagation propagated
 
+saveDesign $encDir/${DESIGN}_cts.enc
+set rpt_post_cts [extract_report postCTS]
+echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
+
+
 # ------------------------------------------------------------------------------
 # Routing
 # ------------------------------------------------------------------------------
@@ -112,6 +123,10 @@ setNanoRouteMode -grouteExpWithTimingDriven false
 routeDesign
 #route_opt_design
 saveDesign ${encDir}/${DESIGN}_route.enc
+
+set rpt_post_route [extract_report postRoute]
+echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
+
 defOut -netlist -floorplan -routing ${DESIGN}_route.def
 
 summaryReport -noHtml -outfile summaryReport/post_route.sum

Flows/ASAP7/ariane136/scripts/cadence/run_invs.tcl

 # This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
 # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+setLibraryUnit -time 1.0ps
 source lib_setup.tcl
 source design_setup.tcl
 source mmmc_setup.tcl
@@ -76,6 +77,11 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc
 
+echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_pre_cts [extract_report preCTS]
+echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
+
 set_ccopt_property post_conditioning_enable_routing_eco 1
 set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
 setOptMode -unfixClkInstForOpt false
@@ -87,6 +93,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
 set_propagated_clock [all_clocks]
 set_clock_propagation propagated
 
+saveDesign $encDir/${DESIGN}_cts.enc
+set rpt_post_cts [extract_report postCTS]
+echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
+
 # ------------------------------------------------------------------------------
 # Routing
 # ------------------------------------------------------------------------------
@@ -112,6 +122,10 @@ setNanoRouteMode -grouteExpWithTimingDriven false
 routeDesign
 #route_opt_design
 saveDesign ${encDir}/${DESIGN}_route.enc
+
+set rpt_post_route [extract_report postRoute]
+echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
+
 defOut -netlist -floorplan -routing ${DESIGN}_route.def
 
 summaryReport -noHtml -outfile summaryReport/post_route.sum

Flows/ASAP7/mempool_tile/scripts/cadence/run_invs.tcl

 # This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
 # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+setLibraryUnit -time 1.0ps
 source lib_setup.tcl
 source design_setup.tcl
 source mmmc_setup.tcl
@@ -76,6 +77,11 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc
 
+echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_pre_cts [extract_report preCTS]
+echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
+
 set_ccopt_property post_conditioning_enable_routing_eco 1
 set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
 setOptMode -unfixClkInstForOpt false
@@ -87,6 +93,11 @@ set_interactive_constraint_modes [all_constraint_modes -active]
 set_propagated_clock [all_clocks]
 set_clock_propagation propagated
 
+saveDesign $encDir/${DESIGN}_cts.enc
+set rpt_post_cts [extract_report postCTS]
+echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
+
+
 # ------------------------------------------------------------------------------
 # Routing
 # ------------------------------------------------------------------------------
@@ -112,6 +123,10 @@ setNanoRouteMode -grouteExpWithTimingDriven false
 routeDesign
 #route_opt_design
 saveDesign ${encDir}/${DESIGN}_route.enc
+
+set rpt_post_route [extract_report postRoute]
+echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
+
 defOut -netlist -floorplan -routing ${DESIGN}_route.def
 
 summaryReport -noHtml -outfile summaryReport/post_route.sum

Flows/ASAP7/nvdla/constraints/NV_NVDLA_partition_c.sdc

@@ -12,11 +12,11 @@ set_ideal_network [get_ports direct_reset_]
 set_ideal_network [get_ports dla_reset_rstn]
 set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
 set_ideal_network [get_ports test_mode]
-create_clock [get_ports nvdla_core_clk]  -period 0.9  -waveform {0 0.45}
-set_clock_transition -max -rise 0.05 [get_clocks nvdla_core_clk]
-set_clock_transition -max -fall 0.05 [get_clocks nvdla_core_clk]
-set_clock_transition -min -rise 0.05 [get_clocks nvdla_core_clk]
-set_clock_transition -min -fall 0.05 [get_clocks nvdla_core_clk]
+create_clock [get_ports nvdla_core_clk]  -period 900.0  -waveform {0 450.0}
+set_clock_transition -max -rise 50 [get_clocks nvdla_core_clk]
+set_clock_transition -max -fall 50 [get_clocks nvdla_core_clk]
+set_clock_transition -min -rise 50 [get_clocks nvdla_core_clk]
+set_clock_transition -min -fall 50 [get_clocks nvdla_core_clk]
 set_false_path   -from [get_ports direct_reset_]
 set_false_path   -from [get_ports dla_reset_rstn]
 set_false_path   -from [get_ports test_mode]

Flows/ASAP7/nvdla/scripts/cadence/run_invs.tcl

 # This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
 # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+setLibraryUnit -time 1.0ps
 source lib_setup.tcl
 source design_setup.tcl
 source mmmc_setup.tcl
@@ -76,6 +77,11 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc
 
+echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_pre_cts [extract_report preCTS]
+echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
+
 set_ccopt_property post_conditioning_enable_routing_eco 1
 set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
 setOptMode -unfixClkInstForOpt false
@@ -87,6 +93,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
 set_propagated_clock [all_clocks]
 set_clock_propagation propagated
 
+saveDesign $encDir/${DESIGN}_cts.enc
+set rpt_post_cts [extract_report postCTS]
+echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
+
 # ------------------------------------------------------------------------------
 # Routing
 # ------------------------------------------------------------------------------
@@ -112,6 +122,10 @@ setNanoRouteMode -grouteExpWithTimingDriven false
 routeDesign
 #route_opt_design
 saveDesign ${encDir}/${DESIGN}_route.enc
+
+set rpt_post_route [extract_report postRoute]
+echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
+
 defOut -netlist -floorplan -routing ${DESIGN}_route.def
 
 summaryReport -noHtml -outfile summaryReport/post_route.sum

Flows/NanGate45/ariane133/scripts/cadence/run_invs.tcl

@@ -75,6 +75,11 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc
 
+echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_pre_cts [extract_report preCTS]
+echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
+
 set_ccopt_property post_conditioning_enable_routing_eco 1
 set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
 setOptMode -unfixClkInstForOpt false
@@ -86,6 +91,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
 set_propagated_clock [all_clocks]
 set_clock_propagation propagated
 
+saveDesign $encDir/${DESIGN}_cts.enc
+set rpt_post_cts [extract_report postCTS]
+echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
+
 # ------------------------------------------------------------------------------
 # Routing
 # ------------------------------------------------------------------------------
@@ -111,6 +120,8 @@ setNanoRouteMode -grouteExpWithTimingDriven false
 routeDesign
 #route_opt_design
 saveDesign ${encDir}/${DESIGN}_route.enc
+set rpt_post_route [extract_report postRoute]
+echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
 defOut -netlist -floorplan -routing ${DESIGN}_route.def
 
 summaryReport -noHtml -outfile summaryReport/post_route.sum

Flows/NanGate45/ariane136/scripts/cadence/run_invs.tcl

@@ -75,6 +75,11 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc
 
+echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_pre_cts [extract_report preCTS]
+echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
+
 set_ccopt_property post_conditioning_enable_routing_eco 1
 set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
 setOptMode -unfixClkInstForOpt false
@@ -86,6 +91,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
 set_propagated_clock [all_clocks]
 set_clock_propagation propagated
 
+saveDesign $encDir/${DESIGN}_cts.enc
+set rpt_post_cts [extract_report postCTS]
+echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
+
 # ------------------------------------------------------------------------------
 # Routing
 # ------------------------------------------------------------------------------
@@ -111,6 +120,8 @@ setNanoRouteMode -grouteExpWithTimingDriven false
 routeDesign
 #route_opt_design
 saveDesign ${encDir}/${DESIGN}_route.enc
+set rpt_post_route [extract_report postRoute]
+echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
 defOut -netlist -floorplan -routing ${DESIGN}_route.def
 
 summaryReport -noHtml -outfile summaryReport/post_route.sum

Flows/NanGate45/mempool_tile/scripts/cadence/run_invs.tcl

@@ -75,6 +75,11 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc
 
+echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_pre_cts [extract_report preCTS]
+echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
+
 set_ccopt_property post_conditioning_enable_routing_eco 1
 set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
 setOptMode -unfixClkInstForOpt false
@@ -86,6 +91,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
 set_propagated_clock [all_clocks]
 set_clock_propagation propagated
 
+saveDesign $encDir/${DESIGN}_cts.enc
+set rpt_post_cts [extract_report postCTS]
+echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
+
 # ------------------------------------------------------------------------------
 # Routing
 # ------------------------------------------------------------------------------
@@ -111,6 +120,8 @@ setNanoRouteMode -grouteExpWithTimingDriven false
 routeDesign
 #route_opt_design
 saveDesign ${encDir}/${DESIGN}_route.enc
+set rpt_post_route [extract_report postRoute]
+echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
 defOut -netlist -floorplan -routing ${DESIGN}_route.def
 
 summaryReport -noHtml -outfile summaryReport/post_route.sum

Flows/NanGate45/nvdla/scripts/cadence/run_invs.tcl

@@ -75,6 +75,11 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc
 
+echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_pre_cts [extract_report preCTS]
+echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
+
 set_ccopt_property post_conditioning_enable_routing_eco 1
 set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
 setOptMode -unfixClkInstForOpt false
@@ -86,6 +91,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
 set_propagated_clock [all_clocks]
 set_clock_propagation propagated
 
+saveDesign $encDir/${DESIGN}_cts.enc
+set rpt_post_cts [extract_report postCTS]
+echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
+
 # ------------------------------------------------------------------------------
 # Routing
 # ------------------------------------------------------------------------------
@@ -111,6 +120,8 @@ setNanoRouteMode -grouteExpWithTimingDriven false
 routeDesign
 #route_opt_design
 saveDesign ${encDir}/${DESIGN}_route.enc
+set rpt_post_route [extract_report postRoute]
+echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
 defOut -netlist -floorplan -routing ${DESIGN}_route.def
 
 summaryReport -noHtml -outfile summaryReport/post_route.sum

Flows/SKY130HD/ariane133/constraints/ariane.sdc

 #period set in nano-seconds - currently: 4ns = 250 MHz freq
-create_clock [get_ports clk_i]  -name core_clock  -period 4
+create_clock [get_ports clk_i]  -name core_clock  -period 6

Flows/SKY130HD/ariane133/scripts/cadence/run_invs.tcl

@@ -74,6 +74,11 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc
 
+echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_pre_cts [extract_report preCTS]
+echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
+
 set_ccopt_property post_conditioning_enable_routing_eco 1
 set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
 setOptMode -unfixClkInstForOpt false
@@ -85,6 +90,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
 set_propagated_clock [all_clocks]
 set_clock_propagation propagated
 
+saveDesign $encDir/${DESIGN}_cts.enc
+set rpt_post_cts [extract_report postCTS]
+echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
+
 # ------------------------------------------------------------------------------
 # Routing
 # ------------------------------------------------------------------------------
@@ -110,6 +119,10 @@ setNanoRouteMode -grouteExpWithTimingDriven false
 routeDesign
 #route_opt_design
 saveDesign ${encDir}/${DESIGN}_route.enc
+
+set rpt_post_route [extract_report postRoute]
+echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
+
 defOut -netlist -floorplan -routing ${DESIGN}_route.def
 
 summaryReport -noHtml -outfile summaryReport/post_route.sum

Flows/SKY130HD/ariane136/constraints/ariane.sdc

-# ####################################################################
-
-#  Created by Genus(TM) Synthesis Solution 21.10-p002_1 on Fri Jul 01 20:44:40 PDT 2022
-
-# ####################################################################
-
-set sdc_version 2.0
-
-set_units -capacitance 1000fF
-set_units -time 1000ps
-
-# Set the current design
-current_design ariane
-
-create_clock -name "core_clock" -period 8.0 -waveform {0.0 4.0} [get_ports clk_i]
-set_clock_gating_check -setup 0.0 
-set_wire_load_mode "top"
+#period set in nano-seconds - currently: 4ns = 250 MHz freq
+create_clock [get_ports clk_i]  -name core_clock  -period 6

Flows/SKY130HD/ariane136/scripts/cadence/run_invs.tcl

@@ -74,6 +74,11 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc
 
+echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_pre_cts [extract_report preCTS]
+echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
+
 set_ccopt_property post_conditioning_enable_routing_eco 1
 set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
 setOptMode -unfixClkInstForOpt false
@@ -85,6 +90,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
 set_propagated_clock [all_clocks]
 set_clock_propagation propagated
 
+saveDesign $encDir/${DESIGN}_cts.enc
+set rpt_post_cts [extract_report postCTS]
+echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
+
 # ------------------------------------------------------------------------------
 # Routing
 # ------------------------------------------------------------------------------
@@ -110,6 +119,10 @@ setNanoRouteMode -grouteExpWithTimingDriven false
 routeDesign
 #route_opt_design
 saveDesign ${encDir}/${DESIGN}_route.enc
+
+set rpt_post_route [extract_report postRoute]
+echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
+
 defOut -netlist -floorplan -routing ${DESIGN}_route.def
 
 summaryReport -noHtml -outfile summaryReport/post_route.sum

Flows/SKY130HD/mempool_tile/scripts/cadence/run_invs.tcl

@@ -74,6 +74,11 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc
 
+echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_pre_cts [extract_report preCTS]
+echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
+
 set_ccopt_property post_conditioning_enable_routing_eco 1
 set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
 setOptMode -unfixClkInstForOpt false
@@ -85,6 +90,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
 set_propagated_clock [all_clocks]
 set_clock_propagation propagated
 
+saveDesign $encDir/${DESIGN}_cts.enc
+set rpt_post_cts [extract_report postCTS]
+echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
+
 # ------------------------------------------------------------------------------
 # Routing
 # ------------------------------------------------------------------------------
@@ -110,6 +119,10 @@ setNanoRouteMode -grouteExpWithTimingDriven false
 routeDesign
 #route_opt_design
 saveDesign ${encDir}/${DESIGN}_route.enc
+
+set rpt_post_route [extract_report postRoute]
+echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
+
 defOut -netlist -floorplan -routing ${DESIGN}_route.def
 
 summaryReport -noHtml -outfile summaryReport/post_route.sum

Flows/SKY130HD/nvdla/constraints/NV_NVDLA_partition_c.sdc

@@ -12,7 +12,7 @@ set_ideal_network [get_ports direct_reset_]
 set_ideal_network [get_ports dla_reset_rstn]
 set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
 set_ideal_network [get_ports test_mode]
-create_clock [get_ports nvdla_core_clk]  -period 6.0  -waveform {0 3.0}
+create_clock [get_ports nvdla_core_clk]  -period 5.0  -waveform {0 2.5}
 set_clock_transition -max -rise 0.15 [get_clocks nvdla_core_clk]
 set_clock_transition -max -fall 0.15 [get_clocks nvdla_core_clk]
 set_clock_transition -min -rise 0.15 [get_clocks nvdla_core_clk]

Flows/SKY130HD/nvdla/scripts/cadence/run_invs.tcl

@@ -74,6 +74,11 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc
 
+echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_pre_cts [extract_report preCTS]
+echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
+
 set_ccopt_property post_conditioning_enable_routing_eco 1
 set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
 setOptMode -unfixClkInstForOpt false
@@ -85,6 +90,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
 set_propagated_clock [all_clocks]
 set_clock_propagation propagated
 
+saveDesign $encDir/${DESIGN}_cts.enc
+set rpt_post_cts [extract_report postCTS]
+echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
+
 # ------------------------------------------------------------------------------
 # Routing
 # ------------------------------------------------------------------------------
@@ -110,6 +119,10 @@ setNanoRouteMode -grouteExpWithTimingDriven false
 routeDesign
 #route_opt_design
 saveDesign ${encDir}/${DESIGN}_route.enc
+
+set rpt_post_route [extract_report postRoute]
+echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
+
 defOut -netlist -floorplan -routing ${DESIGN}_route.def
 
 summaryReport -noHtml -outfile summaryReport/post_route.sum

Flows/util/extract_report.tcl

+proc extract_from_timing_rpt {timing_rpt} {
+    set wns ""
+    set tns ""
+    set hc ""
+    set vc ""
+    set flag "0"
+    # puts "File name $timing_rpt"
+    set fp [open $timing_rpt r]
+    zlib push gunzip $fp
+    while { [gets $fp line] >= 0 } {
+        # puts "Lins is : $line"
+        if { $flag == 0 } {
+            set words [split $line "|"]
+        } else {
+            set words [split $line]
+        }
+        if {[string map {" " "" } [lindex $words 1]] == "WNS(ns):"} {
+            set wns [string map {" " "" } [lindex $words 2]]
+        } elseif {[string map {" " "" } [lindex $words 1]] == "TNS(ns):"} {
+            set tns [string map {" " "" } [lindex $words 2]]
+            set flag 1
+        } elseif { [lindex $words 0] == "Routing" && [llength $words] == 7} {
+            set hc [lindex $words 2]
+            set vc [lindex $words 5]
+            break
+        }
+    }
+    close $fp
+    set ans [list $wns $tns $hc $vc]
+    return $ans
+}
+
+proc extract_from_power_rpt {power_rpt} {
+    set power ""
+    set fp [open $power_rpt r]
+    while { [gets $fp line] >= 0 } {
+        if { [lindex $line 0] == "Total" && [llength $line] == 3 } {
+            set power [lindex $line 2]
+            break
+        }
+    }
+    return $power
+}
+
+proc extract_cell_area {} {
+    set macro_area [expr  [join [dbget [dbget top.insts.cell.name *ram* -p2 ].area ] +]]
+    set std_cell_area [expr  [join [dbget [dbget top.insts.cell.name *ram* -v -p2 ].area ] +]]
+    return [list $macro_area $std_cell_area]
+}
+
+proc extract_wire_length {} {
+    set wire_length [expr [join [dbget top.nets.wires.length ] + ]]
+}
+
+proc extract_report {stage} {
+    if { $stage == "preCTS" } {
+       timeDesign -preCTS -prefix ${stage} 
+    } elseif { $stage == "postCTS" } {
+       timeDesign -postCTS -prefix ${stage} 
+    } elseif { $stage == "postRoute" } {
+        setAnalysisMode -analysisType onChipVariatio -cppr both
+        timeDesign -postRoute -prefix ${stage}
+    }  
+    set rpt1 [extract_from_timing_rpt timingReports/${stage}.summary.gz]
+    report_power > power_${stage}.rpt
+    set rpt2 [extract_from_power_rpt power_${stage}.rpt]
+    set rpt3 [extract_cell_area]
+    set rpt4 [extract_wire_length]
+    # stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c
+    set ans "$stage,[dbget top.fplan.coreBox_area],[lindex $rpt3 1],[lindex $rpt3 0],$rpt2,$rpt4,[lindex $rpt1 0],[lindex $rpt1 1],[lindex $rpt1 2],[lindex $rpt1 3]"
+    return $ans
+}

Flows/util/plc_pb_to_placement_tcl.py

+'''
+Convert plc to place.tcl for macros
+'''
+import sys
+import re
+import numpy as np
+
+plc_file = sys.argv[1]
+pb_file = sys.argv[2]
+place_tcl = sys.argv[3]
+
+orientMap = {
+    "N" : "R0",
+    "S" : "R180",
+    "W" : "R90",
+    "E" : "R270",
+    "FN" : "MY",
+    "FS" : "MX",
+    "FW" : "MX90",
+    "FE" : "MY90"
+}
+
+class pb_object:
+    def __init__(self, id):
+        self.name = None
+        self.node_id = id
+        self.height = 0
+        self.width = 0
+        self.weight = 0
+        self.x = -1
+        self.x_offset = 0
+        self.y = -1
+        self.y_offset = 0
+        self.m_name = None
+        self.pb_type = None
+        self.side = None
+        self.orientation = None
+
+fp = open(pb_file, "r")
+lines = fp.readlines()
+
+key1 = ['"height"', '"weight"', '"width"', '"x"', '"x_offset"', '"y"', '"y_offset"']
+key2 = ['"macro_name"', '"orientation"', '"side"', '"type"']
+node_list = []
+
+node_id = 0
+key = ""
+keys = set()
+for line in lines:
+    words = line.split()
+    if words[0] == 'node':
+        node_list.append(pb_object(node_id))
+        node_id += 1
+    elif words[0] == 'name:':
+        node_list[-1].name = words[1]
+    elif words[0] == 'key:' :
+        key = words[1]
+        keys.add(key)
+    elif words[0] == 'placeholder:' :
+        if key == key2[0]:
+            node_list[-1].m_name = words[1]
+        elif key == key2[1]:
+            node_list[-1].orientation = words[1]
+        elif key == key2[2]:
+            node_list[-1].side = words[1]
+        elif key == key2[3]:
+            node_list[-1].pb_type = words[1]
+    elif words[0] == 'f:' :
+        if key == key1[0]:
+            node_list[-1].height = words[1]
+        elif key == key1[1]:
+            node_list[-1].weight = words[1]
+        elif key == key1[2]:
+            node_list[-1].width = words[1]
+        elif key == key1[3]:
+            node_list[-1].x = np.round(float(words[1]),6)
+        elif key == key1[4]:
+            node_list[-1].x_offset = words[1]
+        elif key == key1[5]:
+            node_list[-1].y = np.round(float(words[1]),6)
+        elif key == key1[6]:
+            node_list[-1].y_offset = words[1]
+fp.close()
+
+fp = open(plc_file, "r")
+lines = fp.readlines()
+fp_out = open(place_tcl, "w")
+id_pattern = re.compile("[0-9]+")
+for line in lines:
+    words = line.split()
+    if id_pattern.match(words[0]) and (len(words) == 5):
+        idx = int(words[0])
+        if node_list[idx].pb_type == '"MACRO"':
+            x = words[1]
+            y = words[2]
+            orient = orientMap[words[3]]
+            isFixed = words[4]
+            macro_name = node_list[idx].name.replace('_[', '\[')
+            macro_name = macro_name.replace('_]', '\]')
+            fp_out.write(f"placeInstance {macro_name} {x}"\
+                        f" {y} {orient} -fixed\n")
+fp.close()
+fp_out.close()