Skip to content

M
macroplacement
Commit 41bbeda6 by sakundu
Options

Updated MemPool Group Scripts, RTL and DEF for NG45 

Signed-off-by: sakundu <sakundu@ucsd.edu>
parent 3b163a60
Showing with 275 additions and 501 deletions
.gitignore
......@@ -10,4 +10,9 @@ CodeElements/Plc_client/__pycache__/*
CodeElements/Plc_client/proto_reader.py
CodeElements/Plc_client/plc_client.py
CodeElements/Plc_client/failed_proxy_plc/*
__pycache__/
__pycache__
run
run*
GF12/
GF12
Enablements/NanGate45/lef/fakeram45_128x256.lef 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/NanGate45/bp_quad/scripts/cadence/design_setup.tcl
......@@ -2,16 +2,16 @@
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
set DESIGN bsg_chip
set sdc ./sdc/bsg_chip.sdc
set sdc ../../constraints/bsg_chip.sdc
set rtldir ./rtl
#
# DEF file for floorplan initialization
#
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set floorplan_def ./def/bsg_chip_fp_placed_macros.def
set floorplan_def ../../def/bsg_chip_fp_placed_macros.def
} else {
set floorplan_def ./def/bsg_chip_fp.def
set floorplan_def ../../def/bsg_chip_fp.def
}
#
# Effort level during optimization in syn_generic -physical (or called generic) stage
......
Flows/NanGate45/bp_quad/scripts/cadence/run.sh
......@@ -8,9 +8,10 @@ module load innovus/21.1
#
# To run the Physical Synthesis (iSpatial) flow - flow2
export PHY_SYNTH=0
export PHY_SYNTH=1
export clk_period=2000
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
#innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
#../../../../util/run_CodeFlow.sh
Flows/NanGate45/bp_quad/scripts/cadence/run_genus_hybrid.tcl
......@@ -137,6 +137,7 @@ write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
......
Flows/NanGate45/mempool_group/constraints/mempool_group.sdc 0 → 100755
set sdc_version 2.0
set_units -time ns -resistance kOhm -capacitance fF -power mW -voltage V -current uA
set clock_cycle $::env(clk_period)
Set uncertainty [expr $clock_cycle*0.02]
set io_delay 0
set maxFanout 16
set maxTransition [expr $clock_cycle*0.01]
set pre_cts_clock_latency_estimate 0.070
set clock_port_mempool_tile clk_i
create_clock -name clk_i -period $clock_cycle [get_ports $clock_port_mempool_tile]
set_clock_uncertainty $uncertainty [all_clocks]
set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==in && is_on_clock_network==false"]
set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==out && is_on_clock_network==false"]
set_max_transition $maxTransition -clock_path [get_clocks clk_i]
set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i]
#set_propagated_clock [get_clocks clk_i]
# Create virtual clock.
create_clock -name "vclk_i" -period $clock_cycle
set_clock_uncertainty $uncertainty [get_clocks vclk_i]
set_clock_latency $pre_cts_clock_latency_estimate [get_clocks vclk_i]
set_max_transition $maxTransition -clock_path [get_clocks vclk_i]
set_case_analysis 0 [get_ports scan_enable_i]
set_max_fanout $maxFanout [current_design]
# False path some of the quasi-static signals.
#set_false_path -from tile_id_i
# TCDM Master
set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ tcdm_master_*req_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_master_*req_*"]
set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ tcdm_master_*resp_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_master_*resp_*"]
# TCDM Slave
#set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ tcdm_slave_*req_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_slave_*req_*"]
set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ tcdm_slave_*resp_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_slave_*resp_*"]
# Refill port
#set_input_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ refill_*"]
#set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ refill_*"]
# Reset
set_input_delay [expr 0.30*$clock_cycle] -clock vclk_i rst_ni
# Critical range
# Depending on the synthesis tool used, this can be helpful.
#set_critical_range 0.100 [current_design]
Flows/NanGate45/mempool_group/def/mempool_group_fp.def 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/NanGate45/mempool_group/def/mempool_group_fp_placed_macros.def 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/NanGate45/mempool_group/scripts/cadence/design_setup.tcl
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
set DESIGN mempool_group_wrap
set rtldir ../../../../../Testcases/mempool/rtl
set DESIGN mempool_group
set rtl_dir ../../../../../Testcases/mempool/hardware
set sdc ../../constraints/${DESIGN}.sdc
set rtldir "${rtl_dir} \
${rtl_dir}/deps/axi \
${rtl_dir}/deps/snitch \
${rtl_dir}/deps/axi/include \
${rtl_dir}/deps/common_cells \
${rtl_dir}/include \
${rtl_dir}/deps/register_interface/include \
${rtl_dir}/deps/common_cells/include \
${rtl_dir}/deps/reqrsp_interface/include"
# def file with die size and placed IO pins
set floorplan_def ../../def/mempool_group_wrap_fp.def
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set floorplan_def ../../def/${DESIGN}_fp_placed_macros.def
} else {
set floorplan_def ../../def/${DESIGN}_fp.def
}
#
# Effort level during optimization in syn_generic -physical (or called generic) stage
# possible values are : high, medium or low
......@@ -15,3 +28,7 @@ set GEN_EFF medium
# Effort level during optimization in syn_map -physical (or called mapping) stage
# possible values are : high, medium or low
set MAP_EFF high
#
set SITE "FreePDK45_38x28_10R_NP_162NW_34O"
set HALO_WIDTH 10
set TOP_ROUTING_LAYER 13
Flows/NanGate45/mempool_group/scripts/cadence/gen_mp_config.tcl deleted 100644 → 0
# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
puts "VERSION 1.0"
set mem_hier ""
foreach a [dbget [dbget top.insts.cell.name fakeram45_* -p2 ].name ] {
regexp {(.*)(/)([^/]*)} $a c b
lappend mem_hier $b
}
set unique_mem_hier [lsort -unique $mem_hier]
puts "BEGIN SEED"
foreach a $unique_mem_hier {
puts "name=$a"
}
puts "END SEED"
puts "BEGIN MACRO"
foreach a [dbget top.insts.cell.name fakeram45_* -u] {
puts "name=$a orient={R0} isCell=true minRightSpace=10 minLeftSpace=10 minTopSpace=5 minBottomSpace=5"
}
puts "END MACRO"
puts "BEGIN CONSTRAINT"
puts "END CONSTRAINT"
Flows/NanGate45/mempool_group/scripts/cadence/lib_setup.tcl
......@@ -4,6 +4,7 @@
set libdir "../../../../../Enablements/NanGate45/lib"
set lefdir "../../../../../Enablements/NanGate45/lef"
set qrcdir "../../../../../Enablements/NanGate45/qrc"
set_db init_lib_search_path { \
${libdir} \
......@@ -13,6 +14,8 @@ set_db init_lib_search_path { \
set libworst "
${libdir}/NangateOpenCellLibrary_typical.lib \
${libdir}/fakeram45_256x32.lib \
${libdir}/fakeram45_128x256.lib \
${libdir}/fakeram45_128x32.lib \
${libdir}/fakeram45_64x64.lib \
"
......@@ -20,6 +23,8 @@ set libworst "
set libbest "
${libdir}/NangateOpenCellLibrary_typical.lib \
${libdir}/fakeram45_256x32.lib \
${libdir}/fakeram45_128x256.lib \
${libdir}/fakeram45_128x32.lib \
${libdir}/fakeram45_64x64.lib \
"
......@@ -27,13 +32,14 @@ set lefs "
${lefdir}/NangateOpenCellLibrary.tech.lef \
${lefdir}/NangateOpenCellLibrary.macro.mod.lef \
${lefdir}/fakeram45_256x32.lef \
${lefdir}/fakeram45_128x256.lef \
${lefdir}/fakeram45_128x32.lef \
${lefdir}/fakeram45_64x64.lef \
"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
#set qrc_max "SigCmax/qrcTechFile"
#set qrc_min "SigCmin/qrcTechFile"
set qrc_max "${qrcdir}/NG45.tch"
set qrc_min "${qrcdir}/NG45.tch"
setDesignMode -process 45
Flows/NanGate45/mempool_group/scripts/cadence/mmmc_iSpatial_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
#create_opcond -name op_cond_wc -process 1.0 -voltage 0.72 -temperature 125
#create_opcond -name op_cond_bc -process 1.0 -voltage 0.88 -temperature -40
create_timing_condition -name timing_wc -library_sets { WC_LIB }
create_timing_condition -name timing_bc -library_sets { BC_LIB }
create_rc_corner -name Cmax -qrc_tech $qrc_max
create_rc_corner -name Cmin -qrc_tech $qrc_min
create_delay_corner -name WC -early_timing_condition { timing_wc } \
-late_timing_condition { timing_wc } \
-early_rc_corner Cmax \
-late_rc_corner Cmax
create_delay_corner -name BC -early_timing_condition { timing_bc } \
-late_timing_condition { timing_bc } \
-early_rc_corner Cmin \
-late_rc_corner Cmin
create_constraint_mode -name CON -sdc_file $sdc
create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
set_analysis_view -setup WC_VIEW -hold BC_VIEW
Flows/NanGate45/mempool_group/scripts/cadence/mp_config.tcl deleted 100644 → 0
# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
VERSION 1.0
BEGIN SEED
name=i_tile/gen_banks_0__mem_bank
name=i_tile/gen_banks_10__mem_bank
name=i_tile/gen_banks_11__mem_bank
name=i_tile/gen_banks_12__mem_bank
name=i_tile/gen_banks_13__mem_bank
name=i_tile/gen_banks_14__mem_bank
name=i_tile/gen_banks_15__mem_bank
name=i_tile/gen_banks_1__mem_bank
name=i_tile/gen_banks_2__mem_bank
name=i_tile/gen_banks_3__mem_bank
name=i_tile/gen_banks_4__mem_bank
name=i_tile/gen_banks_5__mem_bank
name=i_tile/gen_banks_6__mem_bank
name=i_tile/gen_banks_7__mem_bank
name=i_tile/gen_banks_8__mem_bank
name=i_tile/gen_banks_9__mem_bank
name=i_tile/gen_caches_0__i_snitch_icache/i_lookup/i_data
END SEED
BEGIN MACRO
name=fakeram45_64x64 orient={R0} isCell=true minRightSpace=10 minLeftSpace=10 minTopSpace=5 minBottomSpace=5
name=fakeram45_256x32 orient={R0} isCell=true minRightSpace=10 minLeftSpace=10 minTopSpace=5 minBottomSpace=5
END MACRO
BEGIN CONSTRAINT
END CONSTRAINT
Flows/NanGate45/mempool_group/scripts/cadence/rtl_list.tcl
set rtl_all { \
../../../../../Testcases/mempool/rtl/axi/src/axi_pkg.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/cf_math_pkg.sv \
../../../../../Testcases/mempool/rtl/snitch/src/riscv_instr.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_pkg.sv \
../../../../../Testcases/mempool/rtl/mempool_pkg.sv \
../../../../../Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_ipu.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_pkg.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_handler.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_l0.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lookup.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache.sv \
../../../../../Testcases/mempool/rtl/tech_cells_generic/src/rtl/tc_sram.sv \
../../../../../Testcases/mempool/rtl/axi/src/axi_id_prepend.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/spill_register.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/fall_through_register.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/stream_xbar.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_demux.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_axi_adapter.sv \
../../../../../Testcases/mempool/rtl/axi/src/axi_mux.sv \
../../../../../Testcases/mempool/rtl/axi/src/axi_cut.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/spill_register_flushable.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/deprecated/fifo_v2.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/stream_demux.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/rr_arb_tree.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/lzc.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/fifo_v3.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/stream_arbiter.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/stream_arbiter_flushable.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/onehot_to_bin.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_shared_muldiv.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/deprecated/find_first_one.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/isochronous_spill_register.sv \
../../../../../Testcases/mempool/rtl/tech_cells_generic/src/rtl/tc_clk.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_regfile_ff.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_lsu.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_onehot.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch.sv \
../../../../../Testcases/mempool/rtl/address_scrambler.sv \
../../../../../Testcases/mempool/rtl/axi2mem.sv \
../../../../../Testcases/mempool/rtl/axi_hier_interco.sv \
../../../../../Testcases/mempool/rtl/axi_rab_wrap.sv \
../../../../../Testcases/mempool/rtl/bootrom.sv \
../../../../../Testcases/mempool/rtl/ctrl_registers.sv \
../../../../../Testcases/mempool/rtl/latch_scm.sv \
../../../../../Testcases/mempool/rtl/mempool_cc.sv \
../../../../../Testcases/mempool/rtl/mempool_cluster.sv \
../../../../../Testcases/mempool/rtl/mempool_cluster_wrap.sv \
../../../../../Testcases/mempool/rtl/mempool_group.sv \
../../../../../Testcases/mempool/rtl/mempool_system.sv \
../../../../../Testcases/mempool/rtl/mempool_tile.sv \
../../../../../Testcases/mempool/rtl/snitch_addr_demux.sv \
../../../../../Testcases/mempool/rtl/tcdm_adapter.sv \
../../../../../Testcases/mempool/rtl/tcdm_shim.sv \
set rtl_all {
./deps/axi/src/axi_pkg.sv
./deps/common_cells/src/cf_math_pkg.sv
./deps/snitch/src/snitch_icache/snitch_icache_pkg.sv
./deps/snitch/src/riscv_instr.sv
./deps/snitch/src/snitch_pkg.sv
./src/mempool_pkg.sv
./deps/axi/src/axi_id_remap.sv
./deps/axi/src/axi_xbar.sv
./deps/reqrsp_interface/src/reqrsp_pkg.sv
./deps/cluster_interconnect/rtl/variable_latency_interconnect/addr_decoder.sv
./deps/cluster_interconnect/rtl/variable_latency_interconnect/simplex_xbar.sv
./deps/cluster_interconnect/rtl/variable_latency_interconnect/full_duplex_xbar.sv
./deps/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv
./deps/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv
./deps/snitch/src/snitch_ipu.sv
./src/tcdm_wide_narrow_mux.sv
./deps/snitch/src/snitch_icache/snitch_icache.sv
./deps/snitch/src/snitch_icache/snitch_icache_handler.sv
./deps/snitch/src/snitch_icache/snitch_icache_l0.sv
./deps/snitch/src/snitch_icache/snitch_icache_lfsr.sv
./deps/snitch/src/snitch_icache/snitch_icache_refill.sv
../../../../../Testcases/mempool/rtl/tech_cells_generic/src/rtl/tc_sram.sv
./deps/axi/src/axi_id_prepend.sv
./deps/idma/src/axi_dma_data_path.sv
./deps/common_cells/src/stream_register.sv
./deps/common_cells/src/spill_register.sv
./deps/common_cells/src/cc_onehot.sv
./deps/snitch/src/snitch_icache/snitch_icache_lookup_serial.sv
./deps/common_cells/src/stream_fork.sv
./deps/common_cells/src/stream_fork_dynamic.sv
./deps/common_cells/src/stream_join.sv
./deps/common_cells/src/fall_through_register.sv
./deps/common_cells/src/stream_xbar.sv
./deps/snitch/src/snitch_demux.sv
./deps/axi/src/axi_demux.sv
./deps/axi/src/axi_err_slv.sv
./deps/reqrsp_interface/src/axi_to_reqrsp.sv
./deps/common_cells/src/delta_counter.sv
./deps/reqrsp_interface/src/reqrsp_demux.sv
./deps/snitch/src/snitch_axi_adapter.sv
./deps/snitch/src/snitch_read_only_cache/snitch_read_only_cache.sv
./deps/snitch/src/snitch_read_only_cache/snitch_axi_to_cache.sv
./deps/snitch/src/snitch_icache/snitch_icache_lookup_parallel.sv
./deps/idma/src/midends/idma_distributed_midend.sv
./deps/idma/src/axi_dma_backend.sv
./deps/idma/src/axi_dma_burst_reshaper.sv
./deps/idma/src/axi_dma_data_mover.sv
./deps/common_cells/src/addr_decode.sv
./deps/axi/src/axi_mux.sv
./deps/axi/src/axi_cut.sv
./deps/axi/src/axi_atop_filter.sv
./deps/common_cells/src/stream_fifo.sv
./deps/common_cells/src/id_queue.sv
./deps/common_cells/src/stream_mux.sv
./deps/common_cells/src/counter.sv
./deps/common_cells/src/spill_register_flushable.sv
./deps/common_cells/src/deprecated/fifo_v2.sv
./deps/common_cells/src/stream_demux.sv
./deps/common_cells/src/rr_arb_tree.sv
./deps/common_cells/src/lzc.sv
./deps/common_cells/src/fifo_v3.sv
./deps/common_cells/src/stream_arbiter.sv
./deps/common_cells/src/stream_arbiter_flushable.sv
./deps/common_cells/src/onehot_to_bin.sv
./deps/snitch/src/snitch_shared_muldiv.sv
./deps/common_cells/src/deprecated/find_first_one.sv
./deps/common_cells/src/isochronous_spill_register.sv
./deps/tech_cells_generic/src/rtl/tc_clk.sv
./deps/snitch/src/snitch_regfile_ff.sv
./deps/snitch/src/snitch_lsu.sv
./deps/snitch/src/snitch.sv
./src/address_scrambler.sv
./src/axi2mem.sv
./src/axi_hier_interco.sv
./src/axi_rab_wrap.sv
./src/bootrom.sv
./src/ctrl_registers.sv
./src/latch_scm.sv
./src/mempool_cc.sv
./src/mempool_cluster.sv
./src/mempool_group.sv
./src/mempool_system.sv
./src/mempool_tile.sv
./src/snitch_addr_demux.sv
./src/tcdm_adapter.sv
./src/tcdm_shim.sv
}
Flows/NanGate45/mempool_group/scripts/cadence/run.sh 100644 → 100755
......@@ -6,7 +6,12 @@ module load genus/21.1
module unload innovus
module load innovus/21.1
#
# To run the Physical Synthesis (iSpatial) flow - flow2
export PHY_SYNTH=1
export clk_period=3
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
../../../../util/run_grp_main.sh
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
#../../../../util/run_CodeFlow.sh
Flows/NanGate45/mempool_group/scripts/cadence/run_genus.tcl deleted 100644 → 0
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
set_db init_lib_search_path $libdir
set_db init_hdl_search_path $rtldir
# Target library
set link_library $list_lib
set target_library $list_lib
# set path
set_db auto_ungroup none
set_db library $list_lib
#################################################
# Load Design and Initialize
#################################################
source rtl_list.tcl
foreach rtl_file $rtl_all {
read_hdl -language sv -define TARGET_SYNTHESIS -define XPULPIMG=1 $rtl_file
}
elaborate $DESIGN
time_info Elaboration
read_sdc $sdc
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
# keep hierarchy during synthesis
set_db auto_ungroup none
syn_generic
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
syn_map
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
syn_opt
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
#write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exit
Flows/NanGate45/mempool_group/scripts/cadence/run_genus.tcl.old deleted 100644 → 0
# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
set top_module mempool_tile_wrap
set_db max_cpus_per_server 16
set libdir "../../../../../Enablements/NanGate45/lib/"
set libworst "
${libdir}/NangateOpenCellLibrary_typical.lib \
${libdir}/fakeram45_256x32.lib \
${libdir}/fakeram45_64x64.lib \
"
set list_lib "$libworst"
# Target library
set link_library $list_lib
set target_library $list_lib
# set path
set_db auto_ungroup none
set_db init_lib_search_path $libdir
set_db init_hdl_search_path "./rtl/"
set_db library $list_lib
# Start
if {[file exists template]} {
exec rm -rf template
}
exec mkdir template
if {![file exists gate]} {
exec mkdir gate
}
if {![file exists rpt]} {
exec mkdir rpt
}
# Compiler drectives
set compile_effort "high"
set compile_flatten_all 1
set compile_no_new_cells_at_top_level false
# read RTL
source rtl_list.tcl
foreach rtl_file $rtl_all {
if {$top_module == "jpeg_encoder"} {
read_hdl -sv $rtl_file
} else {
read_hdl -language sv -define TARGET_SYNTHESIS -define XPULPIMG=1 $rtl_file
}
}
elaborate $top_module
# Default SDC Constraints
read_sdc ./${top_module}.sdc
syn_generic
syn_map
write_sdc > gate/${top_module}.sdc
write_hdl > gate/${top_module}.v
write_script > constraints.g
# Write Reports
redirect [format "%s%s%s" rpt/ $top_module _area.rep] { report_area }
redirect [format "%s%s%s" rpt/ $top_module _cell.rep] { report_gates }
redirect [format "%s%s%s" rpt/ $top_module _timing.rep] { report_timing }
exit
Flows/NanGate45/mempool_group/scripts/cadence/run_invs.tcl
......@@ -2,17 +2,13 @@
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
set handoff_dir "syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
set netlist "../../netlist/$DESIGN.v"
set sdc "../../constraints/$DESIGN.sdc"
#set netlist "./syn_handoff/$DESIGN.v"
#set sdc "./syn_handoff/$DESIGN.sdc"
set site "FreePDK45_38x28_10R_NP_162NW_34O"
set rptDir summaryReport/
set encDir enc/
......@@ -59,56 +55,42 @@ generateVias
createBasicPathGroups -expanded
## Generate the floorplan ##
#floorPlan -r 1.0 $util 10 10 10 10
defIn $floorplan_def
## Macro Placement ##
#redirect mp_config.tcl {source gen_mp_config.tcl}
#proto_design -constraints mp_config.tcl
addHaloToBlock -allMacro 5 5 5 5
place_design -concurrent_macros
refine_macro_place
saveDesign ${encDir}/${DESIGN}_floorplan.enc
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl
gen_pb_netlist
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
}
## Creating Pin Blcokage for lower and upper pin layers ##
createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
createPinBlkg -name side_top -edge 1
createPinBlkg -name side_right -edge 2
createPinBlkg -name side_bottom -edge 3
### Write postSynth report ###
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_post_synth [extract_report postSynth]
echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
### Write out the def files ###
source ../../../../util/write_required_def.tcl
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setNanoRouteMode -routeTopRoutingLayer 10
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
#setPlaceMode -placeIoPins true
### Add power plan ###
source ../../../../../Enablements/NanGate45/util/pdn_config.tcl
source ../../../../util/pdn_flow.tcl
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
## Creating Pin Blcokage for lower and upper pin layers ##
createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
createPinBlkg -name Layer_2 -edge 1
createPinBlkg -name Layer_3 -edge 2
createPinBlkg -name Layer_4 -edge 3
saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setNanoRouteMode -routeTopRoutingLayer 10
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
setPlaceMode -placeIoPins true
setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
defOut -netlist -floorplan ${DESIGN}_placed.def
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
......@@ -121,15 +103,17 @@ set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks]
set_clock_propagation propagated
saveDesign $encDir/${DESIGN}_cts.enc
set rpt_post_cts [extract_report postCTS]
echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
setNanoRouteMode -routeTopRoutingLayer 10
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
setNanoRouteMode -routeUseAutoVia true
##Recommended by lib owners
# Prevent router modifying M1 pins shapes
......@@ -138,7 +122,6 @@ setNanoRouteMode -routeWithViaOnlyForStandardCellPin "1:1"
## limit VIAs to ongrid only for VIA1 (S1)
setNanoRouteMode -drouteOnGridOnly "via 1:1"
setNanoRouteMode -dbCheckRule true
setNanoRouteMode -drouteAutoStop false
setNanoRouteMode -drouteExpAdvancedMarFix true
setNanoRouteMode -routeExpAdvancedTechnology true
......@@ -146,24 +129,26 @@ setNanoRouteMode -routeExpAdvancedTechnology true
#SM suggestion for solving long extraction runtime during GR
setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
saveDesign ${encDir}/${DESIGN}_route.enc
defOut -netlist -floorplan -routing ${DESIGN}_route.def
setDelayCalMode -reset
setDelayCalMode -SIAware true
setExtractRCMode -engine postRoute -coupled true -tQuantusForPostRoute false
setAnalysisMode -analysisType onChipVariation -cppr both
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
#route_opt_design
optDesign -postRoute
set rpt_post_route [extract_report postRouteOpt]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
# routeOpt
#optDesign -postRoute -setup -hold -prefix postRoute -expandedViews
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
#extractRC
deselectAll
selectNet -clock
reportSelect > summaryReport/clock_net_length.post_route
deselectAll
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment