Updated MemPool Group Scripts, RTL and DEF for NG45

Signed-off-by: sakundu <sakundu@ucsd.edu>

.gitignore

@@ -10,4 +10,9 @@ CodeElements/Plc_client/__pycache__/*
 CodeElements/Plc_client/proto_reader.py
 CodeElements/Plc_client/plc_client.py
 CodeElements/Plc_client/failed_proxy_plc/*
+__pycache__/
+__pycache__
+run
+run*
 GF12/
+GF12

Enablements/NanGate45/lef/fakeram45_128x32.lef

+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+MACRO fakeram45_128x32
+  FOREIGN fakeram45_128x32 0 0 ;
+  SYMMETRY X Y R90 ;
+  SIZE 59.660 BY 82.600 ;
+  CLASS BLOCK ;
+  PIN w_mask_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.065 0.070 2.135 ;
+    END
+  END w_mask_in[0]
+  PIN w_mask_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.695 0.070 2.765 ;
+    END
+  END w_mask_in[1]
+  PIN w_mask_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.325 0.070 3.395 ;
+    END
+  END w_mask_in[2]
+  PIN w_mask_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.955 0.070 4.025 ;
+    END
+  END w_mask_in[3]
+  PIN w_mask_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 4.585 0.070 4.655 ;
+    END
+  END w_mask_in[4]
+  PIN w_mask_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.215 0.070 5.285 ;
+    END
+  END w_mask_in[5]
+  PIN w_mask_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.845 0.070 5.915 ;
+    END
+  END w_mask_in[6]
+  PIN w_mask_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.475 0.070 6.545 ;
+    END
+  END w_mask_in[7]
+  PIN w_mask_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.105 0.070 7.175 ;
+    END
+  END w_mask_in[8]
+  PIN w_mask_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.735 0.070 7.805 ;
+    END
+  END w_mask_in[9]
+  PIN w_mask_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.365 0.070 8.435 ;
+    END
+  END w_mask_in[10]
+  PIN w_mask_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.995 0.070 9.065 ;
+    END
+  END w_mask_in[11]
+  PIN w_mask_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 9.625 0.070 9.695 ;
+    END
+  END w_mask_in[12]
+  PIN w_mask_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.255 0.070 10.325 ;
+    END
+  END w_mask_in[13]
+  PIN w_mask_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.885 0.070 10.955 ;
+    END
+  END w_mask_in[14]
+  PIN w_mask_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.515 0.070 11.585 ;
+    END
+  END w_mask_in[15]
+  PIN w_mask_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.145 0.070 12.215 ;
+    END
+  END w_mask_in[16]
+  PIN w_mask_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.775 0.070 12.845 ;
+    END
+  END w_mask_in[17]
+  PIN w_mask_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 13.405 0.070 13.475 ;
+    END
+  END w_mask_in[18]
+  PIN w_mask_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.035 0.070 14.105 ;
+    END
+  END w_mask_in[19]
+  PIN w_mask_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.665 0.070 14.735 ;
+    END
+  END w_mask_in[20]
+  PIN w_mask_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.295 0.070 15.365 ;
+    END
+  END w_mask_in[21]
+  PIN w_mask_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.925 0.070 15.995 ;
+    END
+  END w_mask_in[22]
+  PIN w_mask_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.555 0.070 16.625 ;
+    END
+  END w_mask_in[23]
+  PIN w_mask_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 17.185 0.070 17.255 ;
+    END
+  END w_mask_in[24]
+  PIN w_mask_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 17.815 0.070 17.885 ;
+    END
+  END w_mask_in[25]
+  PIN w_mask_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 18.445 0.070 18.515 ;
+    END
+  END w_mask_in[26]
+  PIN w_mask_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.075 0.070 19.145 ;
+    END
+  END w_mask_in[27]
+  PIN w_mask_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.705 0.070 19.775 ;
+    END
+  END w_mask_in[28]
+  PIN w_mask_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.335 0.070 20.405 ;
+    END
+  END w_mask_in[29]
+  PIN w_mask_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.965 0.070 21.035 ;
+    END
+  END w_mask_in[30]
+  PIN w_mask_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 21.595 0.070 21.665 ;
+    END
+  END w_mask_in[31]
+  PIN rd_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.325 0.070 24.395 ;
+    END
+  END rd_out[0]
+  PIN rd_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.955 0.070 25.025 ;
+    END
+  END rd_out[1]
+  PIN rd_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 25.585 0.070 25.655 ;
+    END
+  END rd_out[2]
+  PIN rd_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 26.215 0.070 26.285 ;
+    END
+  END rd_out[3]
+  PIN rd_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 26.845 0.070 26.915 ;
+    END
+  END rd_out[4]
+  PIN rd_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 27.475 0.070 27.545 ;
+    END
+  END rd_out[5]
+  PIN rd_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 28.105 0.070 28.175 ;
+    END
+  END rd_out[6]
+  PIN rd_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 28.735 0.070 28.805 ;
+    END
+  END rd_out[7]
+  PIN rd_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 29.365 0.070 29.435 ;
+    END
+  END rd_out[8]
+  PIN rd_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 29.995 0.070 30.065 ;
+    END
+  END rd_out[9]
+  PIN rd_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 30.625 0.070 30.695 ;
+    END
+  END rd_out[10]
+  PIN rd_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 31.255 0.070 31.325 ;
+    END
+  END rd_out[11]
+  PIN rd_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 31.885 0.070 31.955 ;
+    END
+  END rd_out[12]
+  PIN rd_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 32.515 0.070 32.585 ;
+    END
+  END rd_out[13]
+  PIN rd_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 33.145 0.070 33.215 ;
+    END
+  END rd_out[14]
+  PIN rd_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 33.775 0.070 33.845 ;
+    END
+  END rd_out[15]
+  PIN rd_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 34.405 0.070 34.475 ;
+    END
+  END rd_out[16]
+  PIN rd_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 35.035 0.070 35.105 ;
+    END
+  END rd_out[17]
+  PIN rd_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 35.665 0.070 35.735 ;
+    END
+  END rd_out[18]
+  PIN rd_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 36.295 0.070 36.365 ;
+    END
+  END rd_out[19]
+  PIN rd_out[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 36.925 0.070 36.995 ;
+    END
+  END rd_out[20]
+  PIN rd_out[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 37.555 0.070 37.625 ;
+    END
+  END rd_out[21]
+  PIN rd_out[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 38.185 0.070 38.255 ;
+    END
+  END rd_out[22]
+  PIN rd_out[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 38.815 0.070 38.885 ;
+    END
+  END rd_out[23]
+  PIN rd_out[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 39.445 0.070 39.515 ;
+    END
+  END rd_out[24]
+  PIN rd_out[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 40.075 0.070 40.145 ;
+    END
+  END rd_out[25]
+  PIN rd_out[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 40.705 0.070 40.775 ;
+    END
+  END rd_out[26]
+  PIN rd_out[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 41.335 0.070 41.405 ;
+    END
+  END rd_out[27]
+  PIN rd_out[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 41.965 0.070 42.035 ;
+    END
+  END rd_out[28]
+  PIN rd_out[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 42.595 0.070 42.665 ;
+    END
+  END rd_out[29]
+  PIN rd_out[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 43.225 0.070 43.295 ;
+    END
+  END rd_out[30]
+  PIN rd_out[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 43.855 0.070 43.925 ;
+    END
+  END rd_out[31]
+  PIN wd_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 46.585 0.070 46.655 ;
+    END
+  END wd_in[0]
+  PIN wd_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 47.215 0.070 47.285 ;
+    END
+  END wd_in[1]
+  PIN wd_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 47.845 0.070 47.915 ;
+    END
+  END wd_in[2]
+  PIN wd_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 48.475 0.070 48.545 ;
+    END
+  END wd_in[3]
+  PIN wd_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 49.105 0.070 49.175 ;
+    END
+  END wd_in[4]
+  PIN wd_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 49.735 0.070 49.805 ;
+    END
+  END wd_in[5]
+  PIN wd_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 50.365 0.070 50.435 ;
+    END
+  END wd_in[6]
+  PIN wd_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 50.995 0.070 51.065 ;
+    END
+  END wd_in[7]
+  PIN wd_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 51.625 0.070 51.695 ;
+    END
+  END wd_in[8]
+  PIN wd_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 52.255 0.070 52.325 ;
+    END
+  END wd_in[9]
+  PIN wd_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 52.885 0.070 52.955 ;
+    END
+  END wd_in[10]
+  PIN wd_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 53.515 0.070 53.585 ;
+    END
+  END wd_in[11]
+  PIN wd_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 54.145 0.070 54.215 ;
+    END
+  END wd_in[12]
+  PIN wd_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 54.775 0.070 54.845 ;
+    END
+  END wd_in[13]
+  PIN wd_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 55.405 0.070 55.475 ;
+    END
+  END wd_in[14]
+  PIN wd_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 56.035 0.070 56.105 ;
+    END
+  END wd_in[15]
+  PIN wd_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 56.665 0.070 56.735 ;
+    END
+  END wd_in[16]
+  PIN wd_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 57.295 0.070 57.365 ;
+    END
+  END wd_in[17]
+  PIN wd_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 57.925 0.070 57.995 ;
+    END
+  END wd_in[18]
+  PIN wd_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 58.555 0.070 58.625 ;
+    END
+  END wd_in[19]
+  PIN wd_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 59.185 0.070 59.255 ;
+    END
+  END wd_in[20]
+  PIN wd_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 59.815 0.070 59.885 ;
+    END
+  END wd_in[21]
+  PIN wd_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 60.445 0.070 60.515 ;
+    END
+  END wd_in[22]
+  PIN wd_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 61.075 0.070 61.145 ;
+    END
+  END wd_in[23]
+  PIN wd_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 61.705 0.070 61.775 ;
+    END
+  END wd_in[24]
+  PIN wd_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 62.335 0.070 62.405 ;
+    END
+  END wd_in[25]
+  PIN wd_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 62.965 0.070 63.035 ;
+    END
+  END wd_in[26]
+  PIN wd_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 63.595 0.070 63.665 ;
+    END
+  END wd_in[27]
+  PIN wd_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 64.225 0.070 64.295 ;
+    END
+  END wd_in[28]
+  PIN wd_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 64.855 0.070 64.925 ;
+    END
+  END wd_in[29]
+  PIN wd_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 65.485 0.070 65.555 ;
+    END
+  END wd_in[30]
+  PIN wd_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 66.115 0.070 66.185 ;
+    END
+  END wd_in[31]
+  PIN addr_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 68.845 0.070 68.915 ;
+    END
+  END addr_in[0]
+  PIN addr_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 69.475 0.070 69.545 ;
+    END
+  END addr_in[1]
+  PIN addr_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 70.105 0.070 70.175 ;
+    END
+  END addr_in[2]
+  PIN addr_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 70.735 0.070 70.805 ;
+    END
+  END addr_in[3]
+  PIN addr_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 71.365 0.070 71.435 ;
+    END
+  END addr_in[4]
+  PIN addr_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 71.995 0.070 72.065 ;
+    END
+  END addr_in[5]
+  PIN addr_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 72.625 0.070 72.695 ;
+    END
+  END addr_in[6]
+  PIN we_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 75.355 0.070 75.425 ;
+    END
+  END we_in
+  PIN ce_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 75.985 0.070 76.055 ;
+    END
+  END ce_in
+  PIN clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 76.615 0.070 76.685 ;
+    END
+  END clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER metal4 ;
+      RECT 1.960 2.100 2.240 80.500 ;
+      RECT 5.320 2.100 5.600 80.500 ;
+      RECT 8.680 2.100 8.960 80.500 ;
+      RECT 12.040 2.100 12.320 80.500 ;
+      RECT 15.400 2.100 15.680 80.500 ;
+      RECT 18.760 2.100 19.040 80.500 ;
+      RECT 22.120 2.100 22.400 80.500 ;
+      RECT 25.480 2.100 25.760 80.500 ;
+      RECT 28.840 2.100 29.120 80.500 ;
+      RECT 32.200 2.100 32.480 80.500 ;
+      RECT 35.560 2.100 35.840 80.500 ;
+      RECT 38.920 2.100 39.200 80.500 ;
+      RECT 42.280 2.100 42.560 80.500 ;
+      RECT 45.640 2.100 45.920 80.500 ;
+      RECT 49.000 2.100 49.280 80.500 ;
+      RECT 52.360 2.100 52.640 80.500 ;
+      RECT 55.720 2.100 56.000 80.500 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER metal4 ;
+      RECT 3.640 2.100 3.920 80.500 ;
+      RECT 7.000 2.100 7.280 80.500 ;
+      RECT 10.360 2.100 10.640 80.500 ;
+      RECT 13.720 2.100 14.000 80.500 ;
+      RECT 17.080 2.100 17.360 80.500 ;
+      RECT 20.440 2.100 20.720 80.500 ;
+      RECT 23.800 2.100 24.080 80.500 ;
+      RECT 27.160 2.100 27.440 80.500 ;
+      RECT 30.520 2.100 30.800 80.500 ;
+      RECT 33.880 2.100 34.160 80.500 ;
+      RECT 37.240 2.100 37.520 80.500 ;
+      RECT 40.600 2.100 40.880 80.500 ;
+      RECT 43.960 2.100 44.240 80.500 ;
+      RECT 47.320 2.100 47.600 80.500 ;
+      RECT 50.680 2.100 50.960 80.500 ;
+      RECT 54.040 2.100 54.320 80.500 ;
+      RECT 57.400 2.100 57.680 80.500 ;
+    END
+  END VDD
+  OBS
+    LAYER metal1 ;
+    RECT 0 0 59.660 82.600 ;
+    LAYER metal2 ;
+    RECT 0 0 59.660 82.600 ;
+    LAYER metal3 ;
+    RECT 0.070 0 59.660 82.600 ;
+    RECT 0 0.000 0.070 2.065 ;
+    RECT 0 2.135 0.070 2.695 ;
+    RECT 0 2.765 0.070 3.325 ;
+    RECT 0 3.395 0.070 3.955 ;
+    RECT 0 4.025 0.070 4.585 ;
+    RECT 0 4.655 0.070 5.215 ;
+    RECT 0 5.285 0.070 5.845 ;
+    RECT 0 5.915 0.070 6.475 ;
+    RECT 0 6.545 0.070 7.105 ;
+    RECT 0 7.175 0.070 7.735 ;
+    RECT 0 7.805 0.070 8.365 ;
+    RECT 0 8.435 0.070 8.995 ;
+    RECT 0 9.065 0.070 9.625 ;
+    RECT 0 9.695 0.070 10.255 ;
+    RECT 0 10.325 0.070 10.885 ;
+    RECT 0 10.955 0.070 11.515 ;
+    RECT 0 11.585 0.070 12.145 ;
+    RECT 0 12.215 0.070 12.775 ;
+    RECT 0 12.845 0.070 13.405 ;
+    RECT 0 13.475 0.070 14.035 ;
+    RECT 0 14.105 0.070 14.665 ;
+    RECT 0 14.735 0.070 15.295 ;
+    RECT 0 15.365 0.070 15.925 ;
+    RECT 0 15.995 0.070 16.555 ;
+    RECT 0 16.625 0.070 17.185 ;
+    RECT 0 17.255 0.070 17.815 ;
+    RECT 0 17.885 0.070 18.445 ;
+    RECT 0 18.515 0.070 19.075 ;
+    RECT 0 19.145 0.070 19.705 ;
+    RECT 0 19.775 0.070 20.335 ;
+    RECT 0 20.405 0.070 20.965 ;
+    RECT 0 21.035 0.070 21.595 ;
+    RECT 0 21.665 0.070 24.325 ;
+    RECT 0 24.395 0.070 24.955 ;
+    RECT 0 25.025 0.070 25.585 ;
+    RECT 0 25.655 0.070 26.215 ;
+    RECT 0 26.285 0.070 26.845 ;
+    RECT 0 26.915 0.070 27.475 ;
+    RECT 0 27.545 0.070 28.105 ;
+    RECT 0 28.175 0.070 28.735 ;
+    RECT 0 28.805 0.070 29.365 ;
+    RECT 0 29.435 0.070 29.995 ;
+    RECT 0 30.065 0.070 30.625 ;
+    RECT 0 30.695 0.070 31.255 ;
+    RECT 0 31.325 0.070 31.885 ;
+    RECT 0 31.955 0.070 32.515 ;
+    RECT 0 32.585 0.070 33.145 ;
+    RECT 0 33.215 0.070 33.775 ;
+    RECT 0 33.845 0.070 34.405 ;
+    RECT 0 34.475 0.070 35.035 ;
+    RECT 0 35.105 0.070 35.665 ;
+    RECT 0 35.735 0.070 36.295 ;
+    RECT 0 36.365 0.070 36.925 ;
+    RECT 0 36.995 0.070 37.555 ;
+    RECT 0 37.625 0.070 38.185 ;
+    RECT 0 38.255 0.070 38.815 ;
+    RECT 0 38.885 0.070 39.445 ;
+    RECT 0 39.515 0.070 40.075 ;
+    RECT 0 40.145 0.070 40.705 ;
+    RECT 0 40.775 0.070 41.335 ;
+    RECT 0 41.405 0.070 41.965 ;
+    RECT 0 42.035 0.070 42.595 ;
+    RECT 0 42.665 0.070 43.225 ;
+    RECT 0 43.295 0.070 43.855 ;
+    RECT 0 43.925 0.070 46.585 ;
+    RECT 0 46.655 0.070 47.215 ;
+    RECT 0 47.285 0.070 47.845 ;
+    RECT 0 47.915 0.070 48.475 ;
+    RECT 0 48.545 0.070 49.105 ;
+    RECT 0 49.175 0.070 49.735 ;
+    RECT 0 49.805 0.070 50.365 ;
+    RECT 0 50.435 0.070 50.995 ;
+    RECT 0 51.065 0.070 51.625 ;
+    RECT 0 51.695 0.070 52.255 ;
+    RECT 0 52.325 0.070 52.885 ;
+    RECT 0 52.955 0.070 53.515 ;
+    RECT 0 53.585 0.070 54.145 ;
+    RECT 0 54.215 0.070 54.775 ;
+    RECT 0 54.845 0.070 55.405 ;
+    RECT 0 55.475 0.070 56.035 ;
+    RECT 0 56.105 0.070 56.665 ;
+    RECT 0 56.735 0.070 57.295 ;
+    RECT 0 57.365 0.070 57.925 ;
+    RECT 0 57.995 0.070 58.555 ;
+    RECT 0 58.625 0.070 59.185 ;
+    RECT 0 59.255 0.070 59.815 ;
+    RECT 0 59.885 0.070 60.445 ;
+    RECT 0 60.515 0.070 61.075 ;
+    RECT 0 61.145 0.070 61.705 ;
+    RECT 0 61.775 0.070 62.335 ;
+    RECT 0 62.405 0.070 62.965 ;
+    RECT 0 63.035 0.070 63.595 ;
+    RECT 0 63.665 0.070 64.225 ;
+    RECT 0 64.295 0.070 64.855 ;
+    RECT 0 64.925 0.070 65.485 ;
+    RECT 0 65.555 0.070 66.115 ;
+    RECT 0 66.185 0.070 68.845 ;
+    RECT 0 68.915 0.070 69.475 ;
+    RECT 0 69.545 0.070 70.105 ;
+    RECT 0 70.175 0.070 70.735 ;
+    RECT 0 70.805 0.070 71.365 ;
+    RECT 0 71.435 0.070 71.995 ;
+    RECT 0 72.065 0.070 72.625 ;
+    RECT 0 72.695 0.070 75.355 ;
+    RECT 0 75.425 0.070 75.985 ;
+    RECT 0 76.055 0.070 76.615 ;
+    RECT 0 76.685 0.070 82.600 ;
+    LAYER metal4 ;
+    RECT 0 0 59.660 2.100 ;
+    RECT 0 80.500 59.660 82.600 ;
+    RECT 0.000 2.100 1.960 80.500 ;
+    RECT 2.240 2.100 3.640 80.500 ;
+    RECT 3.920 2.100 5.320 80.500 ;
+    RECT 5.600 2.100 7.000 80.500 ;
+    RECT 7.280 2.100 8.680 80.500 ;
+    RECT 8.960 2.100 10.360 80.500 ;
+    RECT 10.640 2.100 12.040 80.500 ;
+    RECT 12.320 2.100 13.720 80.500 ;
+    RECT 14.000 2.100 15.400 80.500 ;
+    RECT 15.680 2.100 17.080 80.500 ;
+    RECT 17.360 2.100 18.760 80.500 ;
+    RECT 19.040 2.100 20.440 80.500 ;
+    RECT 20.720 2.100 22.120 80.500 ;
+    RECT 22.400 2.100 23.800 80.500 ;
+    RECT 24.080 2.100 25.480 80.500 ;
+    RECT 25.760 2.100 27.160 80.500 ;
+    RECT 27.440 2.100 28.840 80.500 ;
+    RECT 29.120 2.100 30.520 80.500 ;
+    RECT 30.800 2.100 32.200 80.500 ;
+    RECT 32.480 2.100 33.880 80.500 ;
+    RECT 34.160 2.100 35.560 80.500 ;
+    RECT 35.840 2.100 37.240 80.500 ;
+    RECT 37.520 2.100 38.920 80.500 ;
+    RECT 39.200 2.100 40.600 80.500 ;
+    RECT 40.880 2.100 42.280 80.500 ;
+    RECT 42.560 2.100 43.960 80.500 ;
+    RECT 44.240 2.100 45.640 80.500 ;
+    RECT 45.920 2.100 47.320 80.500 ;
+    RECT 47.600 2.100 49.000 80.500 ;
+    RECT 49.280 2.100 50.680 80.500 ;
+    RECT 50.960 2.100 52.360 80.500 ;
+    RECT 52.640 2.100 54.040 80.500 ;
+    RECT 54.320 2.100 55.720 80.500 ;
+    RECT 56.000 2.100 57.400 80.500 ;
+    RECT 57.680 2.100 59.660 80.500 ;
+    LAYER OVERLAP ;
+    RECT 0 0 59.660 82.600 ;
+  END
+END fakeram45_128x32
+
+END LIBRARY

Enablements/NanGate45/lib/fakeram45_128x256.lib

+library(fakeram45_128x256) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2022-09-27 21:14:05Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 1.1;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 1.1;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(fakeram45_128x256_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(fakeram45_128x256_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(fakeram45_128x256_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(fakeram45_128x256_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(fakeram45_128x256_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (fakeram45_128x256_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 256;
+        bit_from : 255;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (fakeram45_128x256_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 7;
+        bit_from : 6;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(fakeram45_128x256) {
+    area : 36582.980;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 7;
+        word_width : 256;
+    }
+    pin(clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.293 ;
+        internal_power(){
+            rise_power(fakeram45_128x256_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("16.929, 16.929")
+            }
+            fall_power(fakeram45_128x256_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("16.929, 16.929")
+            }
+        }
+    }
+
+    bus(rd_out)   {
+        bus_type : fakeram45_128x256_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : addr_in;
+        }
+        timing() {
+            related_pin : "clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(fakeram45_128x256_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.332, 0.332", \
+                  "0.332, 0.332" \
+                )
+            }
+            cell_fall(fakeram45_128x256_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.332, 0.332", \
+                  "0.332, 0.332" \
+                )
+            }
+            rise_transition(fakeram45_128x256_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(fakeram45_128x256_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(we_in){
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_128x256_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.169, 0.169")
+            }
+            fall_power(fakeram45_128x256_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.169, 0.169")
+            }
+        }
+    }
+    pin(ce_in){
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_128x256_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.169, 0.169")
+            }
+            fall_power(fakeram45_128x256_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.169, 0.169")
+            }
+        }
+    }
+    bus(addr_in)   {
+        bus_type : fakeram45_128x256_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_128x256_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.169, 0.169")
+            }
+            fall_power(fakeram45_128x256_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.169, 0.169")
+            }
+        }
+    }
+    bus(wd_in)   {
+        bus_type : fakeram45_128x256_DATA;
+        memory_write() {
+            address : addr_in;
+            clocked_on : "clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (we_in) )";
+            rise_power(fakeram45_128x256_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.169, 0.169")
+            }
+            fall_power(fakeram45_128x256_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.169, 0.169")
+            }
+        }
+        internal_power(){
+            when : "(we_in)";
+            rise_power(fakeram45_128x256_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.169, 0.169")
+            }
+            fall_power(fakeram45_128x256_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.169, 0.169")
+            }
+        }
+    }
+    bus(w_mask_in)   {
+        bus_type : fakeram45_128x256_DATA;
+        memory_write() {
+            address : addr_in;
+            clocked_on : "clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x256_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (we_in) )";
+            rise_power(fakeram45_128x256_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.169, 0.169")
+            }
+            fall_power(fakeram45_128x256_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.169, 0.169")
+            }
+        }
+        internal_power(){
+            when : "(we_in)";
+            rise_power(fakeram45_128x256_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.169, 0.169")
+            }
+            fall_power(fakeram45_128x256_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.169, 0.169")
+            }
+        }
+    }
+    cell_leakage_power : 1211.170;
+}
+
+}

Enablements/NanGate45/lib/fakeram45_128x32.lib

+library(fakeram45_128x32) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2022-09-27 00:09:33Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 1.1;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 1.1;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(fakeram45_128x32_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(fakeram45_128x32_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(fakeram45_128x32_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(fakeram45_128x32_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(fakeram45_128x32_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (fakeram45_128x32_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 32;
+        bit_from : 31;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (fakeram45_128x32_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 7;
+        bit_from : 6;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(fakeram45_128x32) {
+    area : 4927.916;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 7;
+        word_width : 32;
+    }
+    pin(clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.194 ;
+        internal_power(){
+            rise_power(fakeram45_128x32_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("2.198, 2.198")
+            }
+            fall_power(fakeram45_128x32_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("2.198, 2.198")
+            }
+        }
+    }
+
+    bus(rd_out)   {
+        bus_type : fakeram45_128x32_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : addr_in;
+        }
+        timing() {
+            related_pin : "clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(fakeram45_128x32_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.248, 0.248", \
+                  "0.248, 0.248" \
+                )
+            }
+            cell_fall(fakeram45_128x32_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.248, 0.248", \
+                  "0.248, 0.248" \
+                )
+            }
+            rise_transition(fakeram45_128x32_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(fakeram45_128x32_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(we_in){
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_128x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.022, 0.022")
+            }
+            fall_power(fakeram45_128x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.022, 0.022")
+            }
+        }
+    }
+    pin(ce_in){
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_128x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.022, 0.022")
+            }
+            fall_power(fakeram45_128x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.022, 0.022")
+            }
+        }
+    }
+    bus(addr_in)   {
+        bus_type : fakeram45_128x32_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_128x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.022, 0.022")
+            }
+            fall_power(fakeram45_128x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.022, 0.022")
+            }
+        }
+    }
+    bus(wd_in)   {
+        bus_type : fakeram45_128x32_DATA;
+        memory_write() {
+            address : addr_in;
+            clocked_on : "clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (we_in) )";
+            rise_power(fakeram45_128x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.022, 0.022")
+            }
+            fall_power(fakeram45_128x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.022, 0.022")
+            }
+        }
+        internal_power(){
+            when : "(we_in)";
+            rise_power(fakeram45_128x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.022, 0.022")
+            }
+            fall_power(fakeram45_128x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.022, 0.022")
+            }
+        }
+    }
+    bus(w_mask_in)   {
+        bus_type : fakeram45_128x32_DATA;
+        memory_write() {
+            address : addr_in;
+            clocked_on : "clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (we_in) )";
+            rise_power(fakeram45_128x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.022, 0.022")
+            }
+            fall_power(fakeram45_128x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.022, 0.022")
+            }
+        }
+        internal_power(){
+            when : "(we_in)";
+            rise_power(fakeram45_128x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.022, 0.022")
+            }
+            fall_power(fakeram45_128x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.022, 0.022")
+            }
+        }
+    }
+    cell_leakage_power : 241.447;
+}
+
+}

Flows/NanGate45/ariane133/netlist/test

-Will copy the netlist here

Flows/NanGate45/bp_quad/constraints/bsg_chip.sdc

@@ -4,25 +4,37 @@
 
 ###################################################################
 set sdc_version 2.0
+set bp_clk_p $::env(clk_period)
+set clk_uncertainty 150
+set bp_clk_hp [expr ${bp_clk_p}/2]
+set l_clk_p1 [expr ${bp_clk_p}*2]
+set l_clk_p2 [expr ${bp_clk_p}*4]
+set wv1 [list 0 $bp_clk_hp]
+set wv2 [list 0 $bp_clk_p]
+set wv3 [list 0 $l_clk_p1]
+set mx_delay1 [expr ${l_clk_p1}*0.28]
+set mx_delay2 [expr ${l_clk_p2}*0.28]
+set mn_delay1 [expr ${l_clk_p1}*0.02]
+
 
 set_units -time ps -resistance kOhm -capacitance fF -power mW -voltage V       \
 -current uA
-create_clock [get_ports p_bsg_tag_clk_i]  -name tag_clk  -period 11200  -waveform {0 5600}
-set_clock_uncertainty -hold 150  [get_clocks tag_clk]
-create_clock [get_ports p_clk_A_i]  -name bp_clk  -period 2800  -waveform {0 1400}
-set_clock_uncertainty 150  [get_clocks bp_clk]
-create_clock [get_ports p_clk_B_i]  -name io_master_clk  -period 2800  -waveform {0 1400}
-set_clock_uncertainty 150  [get_clocks io_master_clk]
-create_clock [get_ports p_clk_C_i]  -name router_clk  -period 2800  -waveform {0 1400}
-set_clock_uncertainty 150  [get_clocks router_clk]
-create_clock [get_ports p_ci_clk_i]  -name sdi_a_clk  -period 5600  -waveform {0 2800}
-set_clock_uncertainty 150  [get_clocks sdi_a_clk]
-create_clock [get_ports p_ci2_tkn_i]  -name sdo_a_tkn_clk  -period 5600  -waveform {0 2800}
-set_clock_uncertainty 150  [get_clocks sdo_a_tkn_clk]
-create_clock [get_ports p_co_clk_i]  -name sdi_b_clk  -period 5600  -waveform {0 2800}
-set_clock_uncertainty 150  [get_clocks sdi_b_clk]
-create_clock [get_ports p_co2_tkn_i]  -name sdo_b_tkn_clk  -period 5600  -waveform {0 2800}
-set_clock_uncertainty 150  [get_clocks sdo_b_tkn_clk]
+create_clock [get_ports p_bsg_tag_clk_i]  -name tag_clk  -period $l_clk_p2  -waveform $wv3
+set_clock_uncertainty -hold $clk_uncertainty  [get_clocks tag_clk]
+create_clock [get_ports p_clk_A_i]  -name bp_clk  -period $bp_clk_p  -waveform $wv1
+set_clock_uncertainty $clk_uncertainty  [get_clocks bp_clk]
+create_clock [get_ports p_clk_B_i]  -name io_master_clk  -period $bp_clk_p  -waveform $wv1
+set_clock_uncertainty $clk_uncertainty  [get_clocks io_master_clk]
+create_clock [get_ports p_clk_C_i]  -name router_clk  -period $bp_clk_p  -waveform $wv1
+set_clock_uncertainty $clk_uncertainty  [get_clocks router_clk]
+create_clock [get_ports p_ci_clk_i]  -name sdi_a_clk  -period $l_clk_p1  -waveform $wv2
+set_clock_uncertainty $clk_uncertainty  [get_clocks sdi_a_clk]
+create_clock [get_ports p_ci2_tkn_i]  -name sdo_a_tkn_clk  -period $l_clk_p1  -waveform $wv2
+set_clock_uncertainty $clk_uncertainty  [get_clocks sdo_a_tkn_clk]
+create_clock [get_ports p_co_clk_i]  -name sdi_b_clk  -period $l_clk_p1  -waveform $wv2
+set_clock_uncertainty $clk_uncertainty  [get_clocks sdi_b_clk]
+create_clock [get_ports p_co2_tkn_i]  -name sdo_b_tkn_clk  -period $l_clk_p1  -waveform $wv2
+set_clock_uncertainty $clk_uncertainty  [get_clocks sdo_b_tkn_clk]
 #
 set_multicycle_path 0 -hold -to [list [get_ports p_ci2_clk_o] [get_ports       \
 p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o]   \
@@ -42,95 +54,95 @@ p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o]   \
 p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]]
 set_false_path   -from [get_clocks router_clk]  -to [get_clocks bp_clk]
 set_false_path   -from [get_clocks tag_clk]  -to [get_clocks bp_clk]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_clk_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_clk_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_clk_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_clk_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_clk_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_clk_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_clk_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_clk_i]
-set_input_delay -clock tag_clk  3333  [get_ports p_bsg_tag_data_i]
-set_input_delay -clock tag_clk  3333  [get_ports p_bsg_tag_en_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_v_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_v_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_v_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_v_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_0_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_0_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_0_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_0_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_1_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_1_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_1_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_1_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_2_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_2_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_2_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_2_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_3_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_3_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_3_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_3_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_4_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_4_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_4_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_4_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_5_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_5_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_5_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_5_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_6_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_6_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_6_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_6_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_7_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_7_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_7_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_7_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_8_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_8_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_8_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_8_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_v_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_v_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_v_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_v_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_0_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_0_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_0_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_0_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_1_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_1_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_1_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_1_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_2_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_2_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_2_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_2_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_3_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_3_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_3_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_3_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_4_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_4_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_4_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_4_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_5_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_5_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_5_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_5_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_6_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_6_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_6_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_6_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_7_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_7_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_7_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_7_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_8_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_8_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_8_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_8_i]
+set_input_delay -clock sdi_a_clk  -max $mx_delay1  [get_ports p_ci_clk_i]
+set_input_delay -clock sdi_a_clk  -min $mn_delay1  [get_ports p_ci_clk_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_ci_clk_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_ci_clk_i]
+set_input_delay -clock sdi_b_clk  -max $mx_delay1  [get_ports p_co_clk_i]
+set_input_delay -clock sdi_b_clk  -min $mn_delay1  [get_ports p_co_clk_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_co_clk_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_co_clk_i]
+set_input_delay -clock tag_clk  $mx_delay2  [get_ports p_bsg_tag_data_i]
+set_input_delay -clock tag_clk  $mx_delay2  [get_ports p_bsg_tag_en_i]
+set_input_delay -clock sdi_a_clk  -max $mx_delay1  [get_ports p_ci_v_i]
+set_input_delay -clock sdi_a_clk  -min $mn_delay1  [get_ports p_ci_v_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_ci_v_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_ci_v_i]
+set_input_delay -clock sdi_a_clk  -max $mx_delay1  [get_ports p_ci_0_i]
+set_input_delay -clock sdi_a_clk  -min $mn_delay1  [get_ports p_ci_0_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_ci_0_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_ci_0_i]
+set_input_delay -clock sdi_a_clk  -max $mx_delay1  [get_ports p_ci_1_i]
+set_input_delay -clock sdi_a_clk  -min $mn_delay1  [get_ports p_ci_1_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_ci_1_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_ci_1_i]
+set_input_delay -clock sdi_a_clk  -max $mx_delay1  [get_ports p_ci_2_i]
+set_input_delay -clock sdi_a_clk  -min $mn_delay1  [get_ports p_ci_2_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_ci_2_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_ci_2_i]
+set_input_delay -clock sdi_a_clk  -max $mx_delay1  [get_ports p_ci_3_i]
+set_input_delay -clock sdi_a_clk  -min $mn_delay1  [get_ports p_ci_3_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_ci_3_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_ci_3_i]
+set_input_delay -clock sdi_a_clk  -max $mx_delay1  [get_ports p_ci_4_i]
+set_input_delay -clock sdi_a_clk  -min $mn_delay1  [get_ports p_ci_4_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_ci_4_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_ci_4_i]
+set_input_delay -clock sdi_a_clk  -max $mx_delay1  [get_ports p_ci_5_i]
+set_input_delay -clock sdi_a_clk  -min $mn_delay1  [get_ports p_ci_5_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_ci_5_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_ci_5_i]
+set_input_delay -clock sdi_a_clk  -max $mx_delay1  [get_ports p_ci_6_i]
+set_input_delay -clock sdi_a_clk  -min $mn_delay1  [get_ports p_ci_6_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_ci_6_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_ci_6_i]
+set_input_delay -clock sdi_a_clk  -max $mx_delay1  [get_ports p_ci_7_i]
+set_input_delay -clock sdi_a_clk  -min $mn_delay1  [get_ports p_ci_7_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_ci_7_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_ci_7_i]
+set_input_delay -clock sdi_a_clk  -max $mx_delay1  [get_ports p_ci_8_i]
+set_input_delay -clock sdi_a_clk  -min $mn_delay1  [get_ports p_ci_8_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_ci_8_i]
+set_input_delay -clock sdi_a_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_ci_8_i]
+set_input_delay -clock sdi_b_clk  -max $mx_delay1  [get_ports p_co_v_i]
+set_input_delay -clock sdi_b_clk  -min $mn_delay1  [get_ports p_co_v_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_co_v_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_co_v_i]
+set_input_delay -clock sdi_b_clk  -max $mx_delay1  [get_ports p_co_0_i]
+set_input_delay -clock sdi_b_clk  -min $mn_delay1  [get_ports p_co_0_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_co_0_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_co_0_i]
+set_input_delay -clock sdi_b_clk  -max $mx_delay1  [get_ports p_co_1_i]
+set_input_delay -clock sdi_b_clk  -min $mn_delay1  [get_ports p_co_1_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_co_1_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_co_1_i]
+set_input_delay -clock sdi_b_clk  -max $mx_delay1  [get_ports p_co_2_i]
+set_input_delay -clock sdi_b_clk  -min $mn_delay1  [get_ports p_co_2_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_co_2_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_co_2_i]
+set_input_delay -clock sdi_b_clk  -max $mx_delay1  [get_ports p_co_3_i]
+set_input_delay -clock sdi_b_clk  -min $mn_delay1  [get_ports p_co_3_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_co_3_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_co_3_i]
+set_input_delay -clock sdi_b_clk  -max $mx_delay1  [get_ports p_co_4_i]
+set_input_delay -clock sdi_b_clk  -min $mn_delay1  [get_ports p_co_4_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_co_4_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_co_4_i]
+set_input_delay -clock sdi_b_clk  -max $mx_delay1  [get_ports p_co_5_i]
+set_input_delay -clock sdi_b_clk  -min $mn_delay1  [get_ports p_co_5_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_co_5_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_co_5_i]
+set_input_delay -clock sdi_b_clk  -max $mx_delay1  [get_ports p_co_6_i]
+set_input_delay -clock sdi_b_clk  -min $mn_delay1  [get_ports p_co_6_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_co_6_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_co_6_i]
+set_input_delay -clock sdi_b_clk  -max $mx_delay1  [get_ports p_co_7_i]
+set_input_delay -clock sdi_b_clk  -min $mn_delay1  [get_ports p_co_7_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_co_7_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_co_7_i]
+set_input_delay -clock sdi_b_clk  -max $mx_delay1  [get_ports p_co_8_i]
+set_input_delay -clock sdi_b_clk  -min $mn_delay1  [get_ports p_co_8_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -max $mx_delay1  -add_delay  [get_ports p_co_8_i]
+set_input_delay -clock sdi_b_clk  -clock_fall  -min $mn_delay1  -add_delay  [get_ports p_co_8_i]
 set_timing_derate -early -cell_delay 0.97 [get_cells                           \
 {bp_processor/cc/y_0__x_0__tile_node/tile/core/fe/mem/icache/tag_mem/macro_bmem/db1_wb_0__bank/macro_mem}]

Flows/NanGate45/bp_quad/scripts/cadence/design_setup.tcl

@@ -2,16 +2,16 @@
 # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
 
 set DESIGN bsg_chip
-set sdc  ./sdc/bsg_chip.sdc
+set sdc  ../../constraints/bsg_chip.sdc
 set rtldir ./rtl
 
 #
 # DEF file for floorplan initialization
 #
 if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
-    set floorplan_def ./def/bsg_chip_fp_placed_macros.def
+    set floorplan_def ../../def/bsg_chip_fp_placed_macros.def
 } else {
-    set floorplan_def ./def/bsg_chip_fp.def
+    set floorplan_def ../../def/bsg_chip_fp.def
 }
 #
 # Effort level during optimization in syn_generic -physical (or called generic) stage

Flows/NanGate45/bp_quad/scripts/cadence/run.sh

@@ -8,9 +8,10 @@ module load innovus/21.1
 
 #
 # To run the Physical Synthesis (iSpatial) flow - flow2
-export PHY_SYNTH=0
+export PHY_SYNTH=1
+export clk_period=2000
 
 mkdir log -p
 genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
-#innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
+innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
 #../../../../util/run_CodeFlow.sh

Flows/NanGate45/bp_quad/scripts/cadence/run_genus_hybrid.tcl

@@ -137,6 +137,7 @@ write_reports -directory ${REPORTS_PATH} -tag final
 
 if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
     write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+    exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
 } else {
     write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
     write_hdl > ${HANDOFF_PATH}/${DESIGN}.v

Flows/NanGate45/bp_quad/scripts/cadence/sdc/bsg_chip.sdc

-###################################################################
-
-# Created by write_sdc on Wed Sep 29 06:31:20 2021
-
-###################################################################
-set sdc_version 2.0
-
-set_units -time ps -resistance kOhm -capacitance fF -power mW -voltage V       \
--current uA
-create_clock [get_ports p_bsg_tag_clk_i]  -name tag_clk  -period 11200  -waveform {0 5600}
-set_clock_uncertainty -hold 150  [get_clocks tag_clk]
-create_clock [get_ports p_clk_A_i]  -name bp_clk  -period 2800  -waveform {0 1400}
-set_clock_uncertainty 150  [get_clocks bp_clk]
-create_clock [get_ports p_clk_B_i]  -name io_master_clk  -period 2800  -waveform {0 1400}
-set_clock_uncertainty 150  [get_clocks io_master_clk]
-create_clock [get_ports p_clk_C_i]  -name router_clk  -period 2800  -waveform {0 1400}
-set_clock_uncertainty 150  [get_clocks router_clk]
-create_clock [get_ports p_ci_clk_i]  -name sdi_a_clk  -period 5600  -waveform {0 2800}
-set_clock_uncertainty 150  [get_clocks sdi_a_clk]
-create_clock [get_ports p_ci2_tkn_i]  -name sdo_a_tkn_clk  -period 5600  -waveform {0 2800}
-set_clock_uncertainty 150  [get_clocks sdo_a_tkn_clk]
-create_clock [get_ports p_co_clk_i]  -name sdi_b_clk  -period 5600  -waveform {0 2800}
-set_clock_uncertainty 150  [get_clocks sdi_b_clk]
-create_clock [get_ports p_co2_tkn_i]  -name sdo_b_tkn_clk  -period 5600  -waveform {0 2800}
-set_clock_uncertainty 150  [get_clocks sdo_b_tkn_clk]
-#
-set_multicycle_path 0 -hold -to [list [get_ports p_ci2_clk_o] [get_ports       \
-p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o]   \
-[get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports   \
-p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]]
-set_multicycle_path 1 -setup -to [list [get_ports p_ci2_clk_o] [get_ports      \
-p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o]   \
-[get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports   \
-p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]]
-set_multicycle_path 0 -hold -to [list [get_ports p_co2_clk_o] [get_ports       \
-p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o]   \
-[get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports   \
-p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]]
-set_multicycle_path 1 -setup -to [list [get_ports p_co2_clk_o] [get_ports      \
-p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o]   \
-[get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports   \
-p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]]
-set_false_path   -from [get_clocks router_clk]  -to [get_clocks bp_clk]
-set_false_path   -from [get_clocks tag_clk]  -to [get_clocks bp_clk]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_clk_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_clk_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_clk_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_clk_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_clk_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_clk_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_clk_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_clk_i]
-set_input_delay -clock tag_clk  3333  [get_ports p_bsg_tag_data_i]
-set_input_delay -clock tag_clk  3333  [get_ports p_bsg_tag_en_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_v_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_v_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_v_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_v_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_0_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_0_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_0_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_0_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_1_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_1_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_1_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_1_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_2_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_2_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_2_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_2_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_3_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_3_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_3_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_3_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_4_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_4_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_4_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_4_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_5_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_5_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_5_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_5_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_6_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_6_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_6_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_6_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_7_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_7_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_7_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_7_i]
-set_input_delay -clock sdi_a_clk  -max 1582.7  [get_ports p_ci_8_i]
-set_input_delay -clock sdi_a_clk  -min 83.3  [get_ports p_ci_8_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_ci_8_i]
-set_input_delay -clock sdi_a_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_ci_8_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_v_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_v_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_v_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_v_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_0_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_0_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_0_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_0_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_1_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_1_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_1_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_1_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_2_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_2_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_2_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_2_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_3_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_3_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_3_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_3_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_4_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_4_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_4_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_4_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_5_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_5_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_5_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_5_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_6_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_6_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_6_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_6_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_7_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_7_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_7_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_7_i]
-set_input_delay -clock sdi_b_clk  -max 1582.7  [get_ports p_co_8_i]
-set_input_delay -clock sdi_b_clk  -min 83.3  [get_ports p_co_8_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -max 1582.7  -add_delay  [get_ports p_co_8_i]
-set_input_delay -clock sdi_b_clk  -clock_fall  -min 83.3  -add_delay  [get_ports p_co_8_i]
-set_timing_derate -early -cell_delay 0.97 [get_cells                           \
-{bp_processor/cc/y_0__x_0__tile_node/tile/core/fe/mem/icache/tag_mem/macro_bmem/db1_wb_0__bank/macro_mem}]

Flows/NanGate45/mempool_group/constraints/mempool_group.sdc

+set sdc_version 2.0
+set_units -time ns -resistance kOhm -capacitance fF -power mW -voltage V -current uA
+
+set clock_cycle $::env(clk_period)
+Set uncertainty [expr $clock_cycle*0.02]
+set io_delay 0
+set maxFanout 16
+set maxTransition [expr $clock_cycle*0.01]
+set pre_cts_clock_latency_estimate 0.070
+set clock_port_mempool_tile clk_i
+
+create_clock -name clk_i -period $clock_cycle [get_ports $clock_port_mempool_tile]
+set_clock_uncertainty $uncertainty [all_clocks]
+set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==in && is_on_clock_network==false"]
+set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==out && is_on_clock_network==false"]
+set_max_transition $maxTransition -clock_path [get_clocks clk_i]
+set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i]
+#set_propagated_clock [get_clocks clk_i]
+
+
+# Create virtual clock.
+create_clock -name "vclk_i" -period $clock_cycle
+set_clock_uncertainty $uncertainty [get_clocks vclk_i]
+set_clock_latency $pre_cts_clock_latency_estimate [get_clocks vclk_i]
+set_max_transition $maxTransition -clock_path [get_clocks vclk_i]
+
+
+set_case_analysis 0 [get_ports scan_enable_i]
+set_max_fanout $maxFanout [current_design]
+
+
+
+# False path some of the quasi-static signals.
+#set_false_path -from tile_id_i
+
+# TCDM Master
+set_input_delay  [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ tcdm_master_*req_*"] 
+set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_master_*req_*"]
+
+set_input_delay  [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ tcdm_master_*resp_*"] 
+set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_master_*resp_*"]
+
+# TCDM Slave
+#set_input_delay  [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ tcdm_slave_*req_*"] 
+set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_slave_*req_*"]
+
+set_input_delay  [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ tcdm_slave_*resp_*"] 
+set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_slave_*resp_*"]
+
+# Refill port
+#set_input_delay  [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ refill_*"] 
+#set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ refill_*"]
+
+# Reset
+set_input_delay  [expr 0.30*$clock_cycle] -clock vclk_i rst_ni
+
+# Critical range
+# Depending on the synthesis tool used, this can be helpful.
+#set_critical_range 0.100 [current_design]

Flows/NanGate45/mempool_group/scripts/cadence/design_setup.tcl

 # This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
 # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
 
-set DESIGN mempool_group_wrap 
-set rtldir ../../../../../Testcases/mempool/rtl
+set DESIGN mempool_group
+set rtl_dir ../../../../../Testcases/mempool/hardware
 set sdc  ../../constraints/${DESIGN}.sdc
+set rtldir "${rtl_dir} \
+           ${rtl_dir}/deps/axi \
+           ${rtl_dir}/deps/snitch \ 
+           ${rtl_dir}/deps/axi/include \
+           ${rtl_dir}/deps/common_cells \
+           ${rtl_dir}/include \
+           ${rtl_dir}/deps/register_interface/include \
+           ${rtl_dir}/deps/common_cells/include \
+           ${rtl_dir}/deps/reqrsp_interface/include"
 
 # def file with die size and placed IO pins
-set floorplan_def ../../def/mempool_group_wrap_fp.def
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    set floorplan_def ../../def/${DESIGN}_fp_placed_macros.def
+} else {
+    set floorplan_def ../../def/${DESIGN}_fp.def
+}
 #
 # Effort level during optimization in syn_generic -physical (or called generic) stage
 # possible values are : high, medium or low
@@ -15,3 +28,7 @@ set GEN_EFF medium
 # Effort level during optimization in syn_map -physical (or called mapping) stage
 # possible values are : high, medium or low
 set MAP_EFF high
+#
+set SITE "FreePDK45_38x28_10R_NP_162NW_34O"
+set HALO_WIDTH 10
+set TOP_ROUTING_LAYER 13

Flows/NanGate45/mempool_group/scripts/cadence/gen_mp_config.tcl

-# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. 
-# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
-puts "VERSION 1.0"
-set mem_hier ""
-foreach a [dbget [dbget top.insts.cell.name fakeram45_* -p2 ].name ] {
-    regexp {(.*)(/)([^/]*)} $a c b
-    lappend mem_hier $b
-}
-set unique_mem_hier [lsort -unique $mem_hier]
-puts "BEGIN SEED"
-foreach a $unique_mem_hier {
-puts "name=$a"
-}
-puts "END SEED"
-
-puts "BEGIN MACRO"
-foreach a [dbget top.insts.cell.name fakeram45_* -u] {
-puts "name=$a  orient={R0} isCell=true minRightSpace=10 minLeftSpace=10 minTopSpace=5 minBottomSpace=5"
-}
-puts "END MACRO"
-
-puts "BEGIN CONSTRAINT"
-puts "END CONSTRAINT"

Flows/NanGate45/mempool_group/scripts/cadence/lib_setup.tcl

@@ -4,15 +4,18 @@
 
 set libdir "../../../../../Enablements/NanGate45/lib"
 set lefdir "../../../../../Enablements/NanGate45/lef"
+set qrcdir "../../../../../Enablements/NanGate45/qrc"
 
 set_db init_lib_search_path { \
     ${libdir} \
     ${lefdir} \
 }
 
-set libworst "  
+set libworst "
     ${libdir}/NangateOpenCellLibrary_typical.lib \
     ${libdir}/fakeram45_256x32.lib \
+    ${libdir}/fakeram45_128x256.lib \
+    ${libdir}/fakeram45_128x32.lib \
     ${libdir}/fakeram45_64x64.lib \
     "
 
@@ -20,6 +23,8 @@ set libworst "
 set libbest " 
     ${libdir}/NangateOpenCellLibrary_typical.lib \
     ${libdir}/fakeram45_256x32.lib \
+    ${libdir}/fakeram45_128x256.lib \
+    ${libdir}/fakeram45_128x32.lib \
     ${libdir}/fakeram45_64x64.lib \
     "
 
@@ -27,13 +32,14 @@ set lefs "
     ${lefdir}/NangateOpenCellLibrary.tech.lef \
     ${lefdir}/NangateOpenCellLibrary.macro.mod.lef \
     ${lefdir}/fakeram45_256x32.lef \
+    ${lefdir}/fakeram45_128x256.lef \
+    ${lefdir}/fakeram45_128x32.lef \
     ${lefdir}/fakeram45_64x64.lef \
     "
 #
 # Ensures proper and consistent library handling between Genus and Innovus
 #set_db library_setup_ispatial true
 
-
-#set qrc_max "SigCmax/qrcTechFile"
-#set qrc_min "SigCmin/qrcTechFile"
+set qrc_max "${qrcdir}/NG45.tch"
+set qrc_min "${qrcdir}/NG45.tch"
 setDesignMode -process 45

Flows/NanGate45/mempool_group/scripts/cadence/mmmc_iSpatial_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+create_library_set -name WC_LIB -timing $libworst
+create_library_set -name BC_LIB -timing $libbest
+ 
+#create_opcond -name op_cond_wc -process 1.0 -voltage 0.72 -temperature 125
+#create_opcond -name op_cond_bc -process 1.0 -voltage 0.88 -temperature -40
+ 
+create_timing_condition -name timing_wc  -library_sets { WC_LIB }
+create_timing_condition -name timing_bc  -library_sets { BC_LIB }
+ 
+create_rc_corner -name Cmax -qrc_tech $qrc_max
+create_rc_corner -name Cmin -qrc_tech $qrc_min
+
+create_delay_corner -name WC -early_timing_condition { timing_wc } \
+                             -late_timing_condition  { timing_wc } \
+                             -early_rc_corner          Cmax        \
+                             -late_rc_corner           Cmax
+
+create_delay_corner -name BC -early_timing_condition { timing_bc } \
+                             -late_timing_condition  { timing_bc } \
+                             -early_rc_corner          Cmin        \
+                             -late_rc_corner           Cmin
+
+
+create_constraint_mode -name CON -sdc_file $sdc 
+create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
+create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
+ 
+set_analysis_view -setup WC_VIEW -hold BC_VIEW

Flows/NanGate45/mempool_group/scripts/cadence/mp_config.tcl

-# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. 
-# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
-VERSION 1.0
-BEGIN SEED
-name=i_tile/gen_banks_0__mem_bank
-name=i_tile/gen_banks_10__mem_bank
-name=i_tile/gen_banks_11__mem_bank
-name=i_tile/gen_banks_12__mem_bank
-name=i_tile/gen_banks_13__mem_bank
-name=i_tile/gen_banks_14__mem_bank
-name=i_tile/gen_banks_15__mem_bank
-name=i_tile/gen_banks_1__mem_bank
-name=i_tile/gen_banks_2__mem_bank
-name=i_tile/gen_banks_3__mem_bank
-name=i_tile/gen_banks_4__mem_bank
-name=i_tile/gen_banks_5__mem_bank
-name=i_tile/gen_banks_6__mem_bank
-name=i_tile/gen_banks_7__mem_bank
-name=i_tile/gen_banks_8__mem_bank
-name=i_tile/gen_banks_9__mem_bank
-name=i_tile/gen_caches_0__i_snitch_icache/i_lookup/i_data
-END SEED
-BEGIN MACRO
-name=fakeram45_64x64  orient={R0} isCell=true minRightSpace=10 minLeftSpace=10 minTopSpace=5 minBottomSpace=5
-name=fakeram45_256x32  orient={R0} isCell=true minRightSpace=10 minLeftSpace=10 minTopSpace=5 minBottomSpace=5
-END MACRO
-BEGIN CONSTRAINT
-END CONSTRAINT

Flows/NanGate45/mempool_group/scripts/cadence/rtl_list.tcl

-set rtl_all {  \
-../../../../../Testcases/mempool/rtl/axi/src/axi_pkg.sv \
-../../../../../Testcases/mempool/rtl/common_cells/src/cf_math_pkg.sv \
-../../../../../Testcases/mempool/rtl/snitch/src/riscv_instr.sv \
-../../../../../Testcases/mempool/rtl/snitch/src/snitch_pkg.sv \
-../../../../../Testcases/mempool/rtl/mempool_pkg.sv \
-../../../../../Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv \
-../../../../../Testcases/mempool/rtl/snitch/src/snitch_ipu.sv \
-../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_pkg.sv \
-../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache.sv \
-../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_handler.sv \
-../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_l0.sv \
-../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv \
-../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lookup.sv \
-../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv \
-../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache.sv \
-../../../../../Testcases/mempool/rtl/tech_cells_generic/src/rtl/tc_sram.sv \
-../../../../../Testcases/mempool/rtl/axi/src/axi_id_prepend.sv \
-../../../../../Testcases/mempool/rtl/common_cells/src/spill_register.sv \
-../../../../../Testcases/mempool/rtl/common_cells/src/fall_through_register.sv \
-../../../../../Testcases/mempool/rtl/common_cells/src/stream_xbar.sv \
-../../../../../Testcases/mempool/rtl/snitch/src/snitch_demux.sv \
-../../../../../Testcases/mempool/rtl/snitch/src/snitch_axi_adapter.sv \
-../../../../../Testcases/mempool/rtl/axi/src/axi_mux.sv \
-../../../../../Testcases/mempool/rtl/axi/src/axi_cut.sv \
-../../../../../Testcases/mempool/rtl/common_cells/src/spill_register_flushable.sv \
-../../../../../Testcases/mempool/rtl/common_cells/src/deprecated/fifo_v2.sv \
-../../../../../Testcases/mempool/rtl/common_cells/src/stream_demux.sv \
-../../../../../Testcases/mempool/rtl/common_cells/src/rr_arb_tree.sv \
-../../../../../Testcases/mempool/rtl/common_cells/src/lzc.sv \
-../../../../../Testcases/mempool/rtl/common_cells/src/fifo_v3.sv \
-../../../../../Testcases/mempool/rtl/common_cells/src/stream_arbiter.sv \
-../../../../../Testcases/mempool/rtl/common_cells/src/stream_arbiter_flushable.sv \
-../../../../../Testcases/mempool/rtl/common_cells/src/onehot_to_bin.sv \
-../../../../../Testcases/mempool/rtl/snitch/src/snitch_shared_muldiv.sv \
-../../../../../Testcases/mempool/rtl/common_cells/src/deprecated/find_first_one.sv \
-../../../../../Testcases/mempool/rtl/common_cells/src/isochronous_spill_register.sv \
-../../../../../Testcases/mempool/rtl/tech_cells_generic/src/rtl/tc_clk.sv \
-../../../../../Testcases/mempool/rtl/snitch/src/snitch_regfile_ff.sv \
-../../../../../Testcases/mempool/rtl/snitch/src/snitch_lsu.sv \
-../../../../../Testcases/mempool/rtl/snitch/src/snitch_onehot.sv \
-../../../../../Testcases/mempool/rtl/snitch/src/snitch.sv \
-../../../../../Testcases/mempool/rtl/address_scrambler.sv \
-../../../../../Testcases/mempool/rtl/axi2mem.sv \
-../../../../../Testcases/mempool/rtl/axi_hier_interco.sv \
-../../../../../Testcases/mempool/rtl/axi_rab_wrap.sv \
-../../../../../Testcases/mempool/rtl/bootrom.sv \
-../../../../../Testcases/mempool/rtl/ctrl_registers.sv \
-../../../../../Testcases/mempool/rtl/latch_scm.sv \
-../../../../../Testcases/mempool/rtl/mempool_cc.sv \
-../../../../../Testcases/mempool/rtl/mempool_cluster.sv \
-../../../../../Testcases/mempool/rtl/mempool_cluster_wrap.sv \
-../../../../../Testcases/mempool/rtl/mempool_group.sv \
-../../../../../Testcases/mempool/rtl/mempool_system.sv \
-../../../../../Testcases/mempool/rtl/mempool_tile.sv \
-../../../../../Testcases/mempool/rtl/snitch_addr_demux.sv \
-../../../../../Testcases/mempool/rtl/tcdm_adapter.sv \
-../../../../../Testcases/mempool/rtl/tcdm_shim.sv \
-} 
+set rtl_all {
+./deps/axi/src/axi_pkg.sv
+./deps/common_cells/src/cf_math_pkg.sv
+./deps/snitch/src/snitch_icache/snitch_icache_pkg.sv
+./deps/snitch/src/riscv_instr.sv
+./deps/snitch/src/snitch_pkg.sv
+./src/mempool_pkg.sv
+./deps/axi/src/axi_id_remap.sv
+./deps/axi/src/axi_xbar.sv
+./deps/reqrsp_interface/src/reqrsp_pkg.sv
+./deps/cluster_interconnect/rtl/variable_latency_interconnect/addr_decoder.sv
+./deps/cluster_interconnect/rtl/variable_latency_interconnect/simplex_xbar.sv
+./deps/cluster_interconnect/rtl/variable_latency_interconnect/full_duplex_xbar.sv
+./deps/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv
+./deps/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv
+./deps/snitch/src/snitch_ipu.sv
+./src/tcdm_wide_narrow_mux.sv
+./deps/snitch/src/snitch_icache/snitch_icache.sv
+./deps/snitch/src/snitch_icache/snitch_icache_handler.sv
+./deps/snitch/src/snitch_icache/snitch_icache_l0.sv
+./deps/snitch/src/snitch_icache/snitch_icache_lfsr.sv
+./deps/snitch/src/snitch_icache/snitch_icache_refill.sv
+../../../../../Testcases/mempool/rtl/tech_cells_generic/src/rtl/tc_sram.sv
+./deps/axi/src/axi_id_prepend.sv
+./deps/idma/src/axi_dma_data_path.sv
+./deps/common_cells/src/stream_register.sv
+./deps/common_cells/src/spill_register.sv
+./deps/common_cells/src/cc_onehot.sv
+./deps/snitch/src/snitch_icache/snitch_icache_lookup_serial.sv
+./deps/common_cells/src/stream_fork.sv
+./deps/common_cells/src/stream_fork_dynamic.sv
+./deps/common_cells/src/stream_join.sv
+./deps/common_cells/src/fall_through_register.sv
+./deps/common_cells/src/stream_xbar.sv
+./deps/snitch/src/snitch_demux.sv
+./deps/axi/src/axi_demux.sv
+./deps/axi/src/axi_err_slv.sv
+./deps/reqrsp_interface/src/axi_to_reqrsp.sv
+./deps/common_cells/src/delta_counter.sv
+./deps/reqrsp_interface/src/reqrsp_demux.sv
+./deps/snitch/src/snitch_axi_adapter.sv
+./deps/snitch/src/snitch_read_only_cache/snitch_read_only_cache.sv
+./deps/snitch/src/snitch_read_only_cache/snitch_axi_to_cache.sv
+./deps/snitch/src/snitch_icache/snitch_icache_lookup_parallel.sv
+./deps/idma/src/midends/idma_distributed_midend.sv
+./deps/idma/src/axi_dma_backend.sv
+./deps/idma/src/axi_dma_burst_reshaper.sv
+./deps/idma/src/axi_dma_data_mover.sv
+./deps/common_cells/src/addr_decode.sv
+./deps/axi/src/axi_mux.sv
+./deps/axi/src/axi_cut.sv
+./deps/axi/src/axi_atop_filter.sv
+./deps/common_cells/src/stream_fifo.sv
+./deps/common_cells/src/id_queue.sv
+./deps/common_cells/src/stream_mux.sv
+./deps/common_cells/src/counter.sv
+./deps/common_cells/src/spill_register_flushable.sv
+./deps/common_cells/src/deprecated/fifo_v2.sv
+./deps/common_cells/src/stream_demux.sv
+./deps/common_cells/src/rr_arb_tree.sv
+./deps/common_cells/src/lzc.sv
+./deps/common_cells/src/fifo_v3.sv
+./deps/common_cells/src/stream_arbiter.sv
+./deps/common_cells/src/stream_arbiter_flushable.sv
+./deps/common_cells/src/onehot_to_bin.sv
+./deps/snitch/src/snitch_shared_muldiv.sv
+./deps/common_cells/src/deprecated/find_first_one.sv
+./deps/common_cells/src/isochronous_spill_register.sv
+./deps/tech_cells_generic/src/rtl/tc_clk.sv
+./deps/snitch/src/snitch_regfile_ff.sv
+./deps/snitch/src/snitch_lsu.sv
+./deps/snitch/src/snitch.sv
+./src/address_scrambler.sv
+./src/axi2mem.sv
+./src/axi_hier_interco.sv
+./src/axi_rab_wrap.sv
+./src/bootrom.sv
+./src/ctrl_registers.sv
+./src/latch_scm.sv
+./src/mempool_cc.sv
+./src/mempool_cluster.sv
+./src/mempool_group.sv
+./src/mempool_system.sv
+./src/mempool_tile.sv
+./src/snitch_addr_demux.sv
+./src/tcdm_adapter.sv
+./src/tcdm_shim.sv
+}

Flows/NanGate45/mempool_group/scripts/cadence/run.sh

@@ -6,7 +6,12 @@ module load genus/21.1
 module unload innovus
 module load innovus/21.1
 
+#
+# To run the Physical Synthesis (iSpatial) flow - flow2
+export PHY_SYNTH=1
+export clk_period=3
+
 mkdir log -p
-genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
-innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
-../../../../util/run_grp_main.sh
+genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
+innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
+#../../../../util/run_CodeFlow.sh

Flows/NanGate45/mempool_group/scripts/cadence/run_genus.tcl

-# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
-# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
-source lib_setup.tcl
-source design_setup.tcl
-
-# set the output directories
-set OUTPUTS_PATH  syn_output
-set REPORTS_PATH  syn_rpt
-set HANDOFF_PATH  syn_handoff
-
-if {![file exists ${OUTPUTS_PATH}]} {
-  file mkdir ${OUTPUTS_PATH}
-}
-
-if {![file exists ${REPORTS_PATH}]} {
-  file mkdir ${REPORTS_PATH}
-}
-
-if {![file exists ${HANDOFF_PATH}]} {
-  file mkdir ${HANDOFF_PATH}
-}
-#
-# set threads
-set_db max_cpus_per_server 16
-set_db super_thread_servers "localhost"
-#
-set list_lib "$libworst"
-
-set_db init_lib_search_path $libdir
-set_db init_hdl_search_path $rtldir 
-
-# Target library
-set link_library $list_lib
-set target_library $list_lib
-
-# set path
-set_db auto_ungroup none
-
-set_db library $list_lib
-
-
-#################################################
-# Load Design and Initialize
-#################################################
-
-source rtl_list.tcl
-
-foreach rtl_file $rtl_all {
-    read_hdl -language sv -define TARGET_SYNTHESIS -define XPULPIMG=1 $rtl_file
-}
-
-elaborate $DESIGN
-time_info Elaboration
-
-read_sdc $sdc
-init_design
-
-check_design -unresolved
-
-check_timing_intent
-# reports the physical layout estimation report from lef and QRC tech file
-report_ple > ${REPORTS_PATH}/ple.rpt 
-
-# keep hierarchy during synthesis
-set_db auto_ungroup none
-
-syn_generic
-time_info GENERIC
-
-# generate a summary for the current stage of synthesis
-write_reports -directory ${REPORTS_PATH} -tag generic
-write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
-
-syn_map
-time_info MAPPED
-
-# generate a summary for the current stage of synthesis
-write_reports -directory ${REPORTS_PATH} -tag map
-write_db  ${OUTPUTS_PATH}/${DESIGN}_map.db
-
-syn_opt
-time_info OPT 
-write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
-
-##############################################################################
-# Write reports
-##############################################################################
-
-# summarizes the information, warnings and errors
-report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
-
-# generate PPA reports
-report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
-report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
-report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
-write_reports -directory ${REPORTS_PATH} -tag final 
-
-write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
-write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
-#write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
-
-exit
-

Flows/NanGate45/mempool_group/scripts/cadence/run_genus.tcl.old

-# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. 
-# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
-set top_module mempool_tile_wrap
-set_db max_cpus_per_server 16
-set libdir "../../../../../Enablements/NanGate45/lib/"
-
-set libworst "
-    ${libdir}/NangateOpenCellLibrary_typical.lib \
-    ${libdir}/fakeram45_256x32.lib \
-    ${libdir}/fakeram45_64x64.lib \
-    "
-
-set list_lib "$libworst"
-
-# Target library
-set link_library $list_lib
-set target_library $list_lib
-
-# set path
-set_db auto_ungroup none
-set_db init_lib_search_path $libdir
-set_db init_hdl_search_path "./rtl/"
-
-set_db library $list_lib
-
-# Start
-if {[file exists template]} {
-	exec rm -rf template
-}
-
-exec mkdir template
-if {![file exists gate]} {
-	exec mkdir gate
-}
-
-if {![file exists rpt]} {
-	exec mkdir rpt
-}
-
-# Compiler drectives
-set compile_effort "high"
-set compile_flatten_all 1
-set compile_no_new_cells_at_top_level false
-
-# read RTL
-source rtl_list.tcl 
-
-foreach rtl_file $rtl_all {
-    if {$top_module == "jpeg_encoder"} {
-        read_hdl -sv $rtl_file
-    } else {
-        read_hdl -language sv -define TARGET_SYNTHESIS -define XPULPIMG=1 $rtl_file
-    }
-}
-
-elaborate $top_module
-
-
-# Default SDC Constraints
-read_sdc ./${top_module}.sdc
-
-syn_generic
-syn_map
-
-write_sdc > gate/${top_module}.sdc
-write_hdl > gate/${top_module}.v
-write_script > constraints.g
-
-# Write Reports
-redirect [format "%s%s%s" rpt/ $top_module _area.rep] { report_area }
-redirect [format "%s%s%s" rpt/ $top_module _cell.rep] { report_gates }
-redirect [format "%s%s%s" rpt/ $top_module _timing.rep] { report_timing }
-
-exit

Flows/NanGate45/mempool_group/scripts/cadence/run_invs.tcl

@@ -2,17 +2,13 @@
 # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
 source lib_setup.tcl
 source design_setup.tcl
+set handoff_dir  "syn_handoff"
+
+set netlist ${handoff_dir}/${DESIGN}.v
+set sdc ${handoff_dir}/${DESIGN}.sdc 
 source mmmc_setup.tcl
 
 setMultiCpuUsage -localCpu 16
-set util 0.3
-
-set netlist "../../netlist/$DESIGN.v"
-set sdc "../../constraints/$DESIGN.sdc"
-#set netlist "./syn_handoff/$DESIGN.v"
-#set sdc "./syn_handoff/$DESIGN.sdc"
-
-set site "FreePDK45_38x28_10R_NP_162NW_34O"
 
 set rptDir summaryReport/ 
 set encDir enc/
@@ -59,56 +55,42 @@ generateVias
 createBasicPathGroups -expanded
 
 ## Generate the floorplan ##
-#floorPlan -r 1.0 $util 10 10 10 10
-defIn $floorplan_def 
-
-## Macro Placement ##
-#redirect mp_config.tcl {source gen_mp_config.tcl}
-#proto_design -constraints mp_config.tcl 
-addHaloToBlock -allMacro 5 5 5 5
-place_design -concurrent_macros
-refine_macro_place
-saveDesign ${encDir}/${DESIGN}_floorplan.enc
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    defIn ${handoff_dir}/${DESIGN}.def
+    source ../../../../util/gen_pb.tcl
+    gen_pb_netlist
+} else {
+    defIn $floorplan_def
+    addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
+    place_design -concurrent_macros
+    refine_macro_place
+}
 
-## Creating Pin Blcokage for lower and upper pin layers ##
-createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
-createPinBlkg -name side_top -edge 1
-createPinBlkg -name side_right -edge 2
-createPinBlkg -name side_bottom -edge 3
+### Write postSynth report ###
+echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_post_synth [extract_report postSynth]
+echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
 
+### Write out the def files ###
+source ../../../../util/write_required_def.tcl
 
-setPlaceMode -place_detail_legalization_inst_gap 1
-setFillerMode -fitGap true
-setNanoRouteMode -routeTopRoutingLayer 10
-setNanoRouteMode -routeBottomRoutingLayer 2
-setNanoRouteMode -drouteVerboseViolationSummary 1
-setNanoRouteMode -routeWithSiDriven true
-setNanoRouteMode -routeWithTimingDriven true
-setNanoRouteMode -routeExpUseAutoVia true
-#setPlaceMode -placeIoPins true
+### Add power plan ###
+source ../../../../../Enablements/NanGate45/util/pdn_config.tcl
+source ../../../../util/pdn_flow.tcl
 
-place_opt_design -out_dir $rptDir -prefix place
-saveDesign $encDir/${DESIGN}_placed.enc
-
-## Creating Pin Blcokage for lower and upper pin layers ##
-createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
-createPinBlkg -name Layer_2 -edge 1
-createPinBlkg -name Layer_3 -edge 2
-createPinBlkg -name Layer_4 -edge 3
+saveDesign ${encDir}/${DESIGN}_floorplan.enc
 
 setPlaceMode -place_detail_legalization_inst_gap 1
 setFillerMode -fitGap true
-setNanoRouteMode -routeTopRoutingLayer 10
-setNanoRouteMode -routeBottomRoutingLayer 2
-setNanoRouteMode -drouteVerboseViolationSummary 1
-setNanoRouteMode -routeWithSiDriven true
-setNanoRouteMode -routeWithTimingDriven true
-setNanoRouteMode -routeExpUseAutoVia true
-setPlaceMode -placeIoPins true
+setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
+setDesignMode -bottomRoutingLayer 2 
 
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc
-defOut -netlist -floorplan ${DESIGN}_placed.def
+
+set rpt_pre_cts [extract_report preCTS]
+echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
 
 set_ccopt_property post_conditioning_enable_routing_eco 1
 set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
@@ -121,15 +103,17 @@ set_interactive_constraint_modes [all_constraint_modes -active]
 set_propagated_clock [all_clocks]
 set_clock_propagation propagated
 
+saveDesign $encDir/${DESIGN}_cts.enc
+set rpt_post_cts [extract_report postCTS]
+echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
+
 # ------------------------------------------------------------------------------
 # Routing
 # ------------------------------------------------------------------------------
-setNanoRouteMode -routeTopRoutingLayer 10
-setNanoRouteMode -routeBottomRoutingLayer 2
 setNanoRouteMode -drouteVerboseViolationSummary 1
 setNanoRouteMode -routeWithSiDriven true
 setNanoRouteMode -routeWithTimingDriven true
-setNanoRouteMode -routeExpUseAutoVia true
+setNanoRouteMode -routeUseAutoVia true
 
 ##Recommended by lib owners
 # Prevent router modifying M1 pins shapes
@@ -138,7 +122,6 @@ setNanoRouteMode -routeWithViaOnlyForStandardCellPin "1:1"
 
 ## limit VIAs to ongrid only for VIA1 (S1)
 setNanoRouteMode -drouteOnGridOnly "via 1:1"
-setNanoRouteMode -dbCheckRule true
 setNanoRouteMode -drouteAutoStop false
 setNanoRouteMode -drouteExpAdvancedMarFix true
 setNanoRouteMode -routeExpAdvancedTechnology true
@@ -146,24 +129,26 @@ setNanoRouteMode -routeExpAdvancedTechnology true
 #SM suggestion for solving long extraction runtime during GR
 setNanoRouteMode -grouteExpWithTimingDriven false
 
-
 routeDesign
 saveDesign ${encDir}/${DESIGN}_route.enc
 defOut -netlist -floorplan -routing ${DESIGN}_route.def
 
-setDelayCalMode -reset 
-setDelayCalMode -SIAware true
-setExtractRCMode -engine postRoute -coupled true -tQuantusForPostRoute false
-setAnalysisMode -analysisType onChipVariation -cppr both
+set rpt_post_route [extract_report postRoute]
+echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
+
+### Run DRC and LVS ###
+verify_connectivity -error 0 -geom_connect -no_antenna
+verify_drc -limit 0
+
+#route_opt_design
+optDesign -postRoute
+set rpt_post_route [extract_report postRouteOpt]
+echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
 
-# routeOpt
-#optDesign -postRoute -setup -hold -prefix postRoute -expandedViews
+### Run DRC and LVS ###
+verify_connectivity -error 0 -geom_connect -no_antenna
+verify_drc -limit 0
 
-#extractRC
-deselectAll
-selectNet -clock
-reportSelect  > summaryReport/clock_net_length.post_route
-deselectAll
 summaryReport -noHtml -outfile summaryReport/post_route.sum
 saveDesign ${encDir}/${DESIGN}.enc
 defOut -netlist -floorplan -routing ${DESIGN}.def

Flows/util/shuffle_macro.tcl

@@ -52,4 +52,4 @@ proc shuffle_macros {seed} {
     }
     puts "$k macros (ref name: ${macro_ref}) are shuffled"
   }
-}
+}
\ No newline at end of file