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Added CT+DREAMPlace results 

Signed-off-by: sakundu <sakundu@ucsd.edu>
parent 8ee38889
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Docs/OurProgress/README.md
......@@ -5866,6 +5866,482 @@ We have also added
- **Ariane133-NG45-68%-1.3ns**: [Link](../../Flows/NanGate45/ariane133#macro-placement-generated-by-an-industry-engineer-not-a-gridded-placement) to the human macro placement details of Ariane on NG45 enablement.
- **MemPool Group-GF12-68%**: [Link](#MemPool_Group_GF12_Human) to the human macro placement details of MemPool Group on GF12 enablement.
<a id="March 5"></a>
**March 5:**
<a id="Question14"></a>
**<span style="color:blue">Question 14.</span>** What is the impact on CT results when DREAMPlace is used instead of force-directed placement?
We have integrated DREAMPlace in Circuit Training (commit hash: 91e14fd1caa5b15d9bb1b58b6d5e47042ab244f3) and trained CT to generate macro placement solutions for Ariane, BlackParrot and MemPool Group designs. We referer to CT with DREAMPlace as CT+DREAMPlace and CT with FD as CT+FD. The training results are as follows:
- Ariane133-NG45-68%-1.3ns: Following table and screenshots presents the macro placement solution generated by CT+DREAMPlace for Ariane133 design with 68% floorplan utilization, 1.3ns target clock period on NG45 enablement. (Wirelength Cost:0.0678, Congestion cost: 0.8320, Density cost: 0.5239)
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Ariane133-NG45-68%-1.3ns CT+DREAMPlace result (<a href="https://tensorboard.dev/experiment/jaeB8QBoRF2TgirwVZHOeg/#scalars">Link</a> to tensorboard) (<a href="#Ariane133_NG45_1.3ns_CT">Link</a> to CT+FD result)</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS (ns)</td>
<td>TNS (ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1814274</td>
<td>244313</td>
<td>1018356</td>
<td>791.482</td>
<td>4669338</td>
<td>-0.135</td>
<td>-176.306</td>
<td>0.05%</td>
<td>0.12%</td>
</tr>
<tr>
<td>postCTS</td>
<td>1814274</td>
<td>244976</td>
<td>1018356</td>
<td>830.645</td>
<td>4693972</td>
<td>-0.106</td>
<td>-75.708</td>
<td>0.05%</td>
<td>0.15%</td>
</tr>
<tr>
<td>postRoute</td>
<td>1814274</td>
<td>244976</td>
<td>1018356</td>
<td>828.923</td>
<td>4822561</td>
<td>-0.124</td>
<td>-109.91</td>
<td></td>
<td></td>
</tr>
<tr>
<td>postRouteOpt</td>
<td>1814274</td>
<td>245438</td>
<td>1018356</td>
<td>829.353</td>
<td>4827641</td>
<td>-0.126</td>
<td>-93.752</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/Ariane_NG45_CT_DREAM_Place.png" alg="Ariane_NG45_CT_DREAM_place">
<img width="300" src="./images/Ariane_NG45_CT_DREAM_Route.png" alg="Ariane_NG45_CT_DREAM_route">
</p>
- BlackParrot(Quad-Core)-NG45-68%-1.3ns: Following table and screenshots presents the macro placement solution generated by CT+DREAMPlace for BlackParrot design with 68% floorplan utilization, 1.3ns target clock period on NG45 enablement. (Wirelength cost: 0.0878, Density cost: 0.5687, Congestion cost: 1.1420)
<table>
<thead>
<tr>
<th colspan="10"><p align="center">BP(Quad-Core)-NG45-68%-1.3ns CT+DREAMPlace (<a href="https://tensorboard.dev/experiment/0gianlLgQ8WBVHRXBP9yOQ/">Link</a> to tensor board) (<a href="../../Flows/NanGate45/bp_quad#macro-placement-generated-using-circuit-training-ct">Link</a> to CT+FD result)</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS (ns)</td>
<td>TNS (ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>8449457</td>
<td>1959789</td>
<td>3917822</td>
<td>4396.086</td>
<td>42267061</td>
<td>-0.209</td>
<td>-1132.2</td>
<td>0.28%</td>
<td>0.57%</td>
</tr>
<tr>
<td>postCTS</td>
<td>8449457</td>
<td>1978100</td>
<td>3917822</td>
<td>4783.785</td>
<td>42346079</td>
<td>-0.163</td>
<td>-680.8</td>
<td>0.29%</td>
<td>0.63%</td>
</tr>
<tr>
<td>postRoute</td>
<td>8449457</td>
<td>1978100</td>
<td>3917822</td>
<td>4751.075</td>
<td>43883402</td>
<td>-0.201</td>
<td>-1406.3</td>
<td></td>
<td></td>
</tr>
<tr>
<td>postRouteOpt</td>
<td>8449457</td>
<td>1979794</td>
<td>3917822</td>
<td>4753.696</td>
<td>43931174</td>
<td>-0.178</td>
<td>-850.8</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/BP_NG45_CT_DREAM_Place.png" alg="BP_NG45_CT_DREAM_place">
<img width="300" src="./images/BP_NG45_CT_DREAM_Route.png" alg="BP_NG45_CT_DREAM_route">
</p>
- MemPool Group-NG45-68%-1.3ns: Following table and screenshots presents the macro placement solution generated by CT+DREAMPlace for MemPool Group design with 68% floorplan utilization, 4ns target clock period on NG45 enablement. (Wirelength cost: 0.0728, Density cost: 0.6617, Congestion cost: 1.2714) DRC Count: 14779.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">MemPool Group-NG45-68%-4ns CT+DREAMPlace (<a href="https://tensorboard.dev/experiment/yOsJjkWkQBC7imKQJRr7SQ/">Link</a> to tensorboard) (<a href="#MemPoolGroup_NG45_68_CT">Link</a> to CT+FD Result)</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS (ns)</td>
<td>TNS (ns)</td>
<td>Congestion (H)</td>
<td>Congestion <br>(V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>11371934</td>
<td>4990302</td>
<td>3078071</td>
<td>2659.403</td>
<td>121635791</td>
<td>-0.015</td>
<td>-71.824</td>
<td>3.33%</td>
<td>3.26%</td>
</tr>
<tr>
<td>postCTS</td>
<td>11371934</td>
<td>4969651</td>
<td>3078071</td>
<td>2839.139</td>
<td>122062712</td>
<td>-0.004</td>
<td>-0.104</td>
<td>3.49%</td>
<td>3.19%</td>
</tr>
<tr>
<td>postRoute</td>
<td>11371934</td>
<td>4969651</td>
<td>3078071</td>
<td>2893.588</td>
<td>132078512</td>
<td>-1.137</td>
<td>-29243.4</td>
<td></td>
<td></td>
</tr>
<tr>
<td>postRouteOpt</td>
<td>11371934</td>
<td>4995348</td>
<td>3078071</td>
<td>2908.959</td>
<td>132299696</td>
<td>-0.072</td>
<td>-97.892</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/MemPool_NG45_CT_DREAM_Place.png" alg="MemPool_NG45_CT_DREAM_place">
<img width="300" src="./images/MemPool_NG45_CT_DREAM_Route.png" alg="MemPool_NG45_CT_DREAM_route">
</p>
<a id="Question15"></a>
**<span style="color:blue">Question 15.</span>** Should we factor in density cost while using DREAMPlace for CT?
We update the density weight from 0.5 to 0.0, then rerun CT-DREAMPlace for Ariane, BlackParrot and MemPool Group designs. The training results are as follows:
- Ariane133-NG45-68%-1.3ns: Following table and screenshots presents the macro placement solution generated by CT+DREAMPlace for Ariane133 design with 68% floorplan utilization, 1.3ns target clock period on NG45 enablement when density weight is 0. (Wirelength Cost: 0.0715, Congestion cost: 0.8111, Density cost: 0.5251)
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Ariane133-NG45-68%-1.3ns CT+DREAMPlace result (Density Weight = 0.0) (<a href="https://tensorboard.dev/experiment/1oaGY9rATny8mEaGkR41tA/">Link</a> to tensorboard) (<a href="#Ariane133_NG45_1.3ns_CT">Link</a> to CT+FD result)</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS (ns)</td>
<td>TNS (ns)</td>
<td>Congestion (H)</td>
<td>Congestion <br>(V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1814274</td>
<td>245097</td>
<td>1018356</td>
<td>793.171</td>
<td>4959656</td>
<td>-0.137</td>
<td>-202.147</td>
<td>0.04%</td>
<td>0.17%</td>
</tr>
<tr>
<td>postCTS</td>
<td>1814274</td>
<td>248172</td>
<td>1018356</td>
<td>839.062</td>
<td>4993255</td>
<td>-0.117</td>
<td>-108.074</td>
<td>0.04%</td>
<td>0.15%</td>
</tr>
<tr>
<td>postRoute</td>
<td>1814274</td>
<td>248172</td>
<td>1018356</td>
<td>836.985</td>
<td>5114089</td>
<td>-0.164</td>
<td>-243.834</td>
<td></td>
<td></td>
</tr>
<tr>
<td>postRouteOpt</td>
<td>1814274</td>
<td>248775</td>
<td>1018356</td>
<td>837.655</td>
<td>5119513</td>
<td>-0.16</td>
<td>-152.043</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/Ariane_NG45_CT_DREAM_Place_no_density.png" alg="Ariane_NG45_CT_DREAM_place_no_density">
<img width="300" src="./images/Ariane_NG45_CT_DREAM_Route_no_density.png" alg="Ariane_NG45_CT_DREAM_route_no_density">
</p>
- BlackParrot(Quad-Core)-NG45-68%-1.3ns: Following table and screenshots presents the macro placement solution generated by CT+DREAMPlace for BlackParrot design with 68% floorplan utilization, 1.3ns target clock period on NG45 enablement when density weight is 0. (Wirelength cost: 0.0791, Density cost: 0.5770, Congestion cost: 1.0964)
<table>
<thead>
<tr>
<th colspan="10"><p align="center">BP(Quad-Core)-NG45-68%-1.3ns CT+DREAMPlace (Density weight = 0.0) (<a href="https://tensorboard.dev/experiment/ymoDJjnlRO6vWWeki9MwVA/">Link</a> to tensorboard) (<a href="../../Flows/NanGate45/bp_quad#macro-placement-generated-using-circuit-training-ct">Link</a> to CT+FD result)</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS (ns)</td>
<td>TNS (ns)</td>
<td>Congestion (H)</td>
<td>Congestion <br>(V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>8449457</td>
<td>1947589</td>
<td>3917822</td>
<td>4323.518</td>
<td>38208933</td>
<td>-0.233</td>
<td>-1177.6</td>
<td>0.33%</td>
<td>0.46%</td>
</tr>
<tr>
<td>postCTS</td>
<td>8449457</td>
<td>1961564</td>
<td>3917822</td>
<td>4703.800</td>
<td>38314312</td>
<td>-0.153</td>
<td>-468.3</td>
<td>0.37%</td>
<td>0.49%</td>
</tr>
<tr>
<td>postRoute</td>
<td>8449457</td>
<td>1961564</td>
<td>3917822</td>
<td>4674.250</td>
<td>39753854</td>
<td>-0.200</td>
<td>-1995.5</td>
<td></td>
<td></td>
</tr>
<tr>
<td>postRouteOpt</td>
<td>8449457</td>
<td>1964239</td>
<td>3917822</td>
<td>4677.048</td>
<td>39800843</td>
<td>-0.180</td>
<td>-809.0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/BP_NG45_CT_DREAM_Place_no_density.png" alg="BP_NG45_CT_DREAM_place_no_density">
<img width="300" src="./images/BP_NG45_CT_DREAM_Route_no_density.png" alg="BP_NG45_CT_DREAM_route_no_density">
</p>
- MemPool Group-NG45-68%-1.3ns: Following table and screenshots presents the macro placement solution generated by CT+DREAMPlace for MemPool Group design with 68% floorplan utilization, 4ns target clock period on NG45 enablement when density weight is 0. (Wirelength cost: 0.0711, Density cost: 0.6666, Congestion cost: 1.2605 ) DRC Count: 3260
<table>
<thead>
<tr>
<th colspan="10"><p align="center">MemPool Group-NG45-68%-4ns CT+DREAMPlace (Density weight = 0.0) (<a href="https://tensorboard.dev/experiment/evulbGlLRReI6cJFZqUMuA/">Link</a> to tensorboard) (<a href="#MemPoolGroup_NG45_68_CT">Link</a> to CT+FD Result)</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS (ns)</td>
<td>TNS (ns)</td>
<td>Congestion (H)</td>
<td>Congestion <br>(V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>11371934</td>
<td>4934839</td>
<td>3078071</td>
<td>2613.613</td>
<td>119923841</td>
<td>-0.027</td>
<td>-146.5</td>
<td>2.56%</td>
<td>2.51%</td>
</tr>
<tr>
<td>postCTS</td>
<td>11371934</td>
<td>4928559</td>
<td>3078071</td>
<td>2802.851</td>
<td>120508367</td>
<td>-0.003</td>
<td>-0.1</td>
<td>2.87%</td>
<td>2.66%</td>
</tr>
<tr>
<td>postRoute</td>
<td>11371934</td>
<td>4928559</td>
<td>3078071</td>
<td>2848.873</td>
<td>130024068</td>
<td>-0.803</td>
<td>-19920.7</td>
<td></td>
<td></td>
</tr>
<tr>
<td>postRouteOpt</td>
<td>11371934</td>
<td>4953483</td>
<td>3078071</td>
<td>2858.071</td>
<td>130243153</td>
<td>-0.050</td>
<td>-33.5</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/MemPool_NG45_CT_DREAM_Place_no_density.png" alg="MemPool_NG45_CT_DREAM_place_no_density">
<img width="300" src="./images/MemPool_NG45_CT_DREAM_Route_no_density.png" alg="MemPool_NG45_CT_DREAM_route_no_density">
</p>
We observe from the above results that CT+DREAMPlace achieves similar result for density weight 0 and 0.5.
## **Pinned (to bottom) question list:**
**<span style="color:blue">[Question 1](#Question1).</span>** How does having an initial set of placement locations (from physical synthesis) affect the (relative) quality of the CT result?
......@@ -5881,3 +6357,5 @@ We have also added
**<span style="color:blue">[Question 11](#Question11).</span>** How does the initial placement generated by different physical synthesis tools affect the CT solution?
**<span style="color:blue">[Question 12](#Question12).</span>** How well does Simulated Annealing (SA) optimize Circuit Training's proxy cost?
**<span style="color:blue">[Question 13](#Question13).</span>** How good are human macro placements relative to Circuit Training?
**<span style="color:blue">[Question 14](#Question14).</span>** What is the impact on CT results when DREAMPlace is used instead of force-directed placement?
**<span style="color:blue">[Question 15](#Question15).</span>** Should we factor in density cost while using DREAMPlace for CT?
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