Commit 39e1f4bd by Ravi Varadarajan

README updates

Signed-off-by: Ravi Varadarajan <rvaradarajan@ucsd.edu>
parent 12a4ac46
# NanGate45 (FreePDK45, 45nm Open Cell Library, bsg_fakeram memory generation) # NanGate45 (FreePDK45, 45nm Open Cell Library, bsg_fakeram memory generation)
The NanGate45 Open Cell Library is available under an Apache2.0 license from Silicon Integration Initiative (Si2). It is based on FreePDK45 from North Carolina State University. [\[Link\]](https://eda.ncsu.edu/downloads/) The NanGate45 Open Cell Library is available under the Apache2.0 license from Silicon Integration Initiative (Si2). It is based on FreePDK45 from North Carolina State University. [\[FreePDK45 Link\]](https://eda.ncsu.edu/downloads/)
As the FreePDK45/NanGate45 enablement does not have memory generators, we use the bsg_fakeram memory generator available on the [bsg_fakeram](https://github.com/jjcherry56/bsg_fakeram) GitHub repo. As the FreePDK45/NanGate45 enablement does not have memory generators, we use the bsg_fakeram memory generator available in the [bsg_fakeram](https://github.com/jjcherry56/bsg_fakeram) GitHub repo.
With this combined enablement, testcases with SRAMs can be synthesized, placed and routed using both proprietary (commercial) tools such as Cadence Genus/Innovus, and open-source tools such as OpenROAD. With this combined enablement, testcases with SRAMs can be synthesized, placed and routed using both proprietary (commercial) tools such as Cadence Genus/Innovus, and open-source tools such as OpenROAD.
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