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Added GF12 normalized results for tuned constraints 

Signed-off-by: sakundu <sakundu@ucsd.edu>
parent 287bb6f2
Showing with 854 additions and 4 deletions
Docs/OurProgress/README.md
......@@ -4496,7 +4496,7 @@ We have run CT to generate macro placements for Ariane133, BlackParrot and MemPo
<td>1.3219</td>
<td>-0.144</td>
<td>-307.690</td>
<td>0</td>
<td>0.00</td>
<td>3.5</td>
</tr>
<tr>
......@@ -4508,7 +4508,7 @@ We have run CT to generate macro placements for Ariane133, BlackParrot and MemPo
<td>1.3389</td>
<td>-0.169</td>
<td>-190.458</td>
<td>0</td>
<td>0.00</td>
<td>3.5</td>
</tr>
<tr>
......@@ -4933,8 +4933,7 @@ We have run CT to generate macro placements for Ariane133, BlackParrot and MemPo
<table>
<thead>
<tr>
<th colspan="10">MemPool Group-GF12-68% human macro placement [results are normalized as described <a href="#GF12_Normalization">here</a>
] </th>
<th colspan="10"><p align="center">MemPool Group-GF12-68% human macro placement [results are normalized as described <a href="#GF12_Normalization">here</a>]</p></th>
</tr>
</thead>
<tbody>
......@@ -5006,6 +5005,857 @@ We have run CT to generate macro placements for Ariane133, BlackParrot and MemPo
<img width="300" src="./images/MemPool_Group_GF12_Human_Route.png" alg="MemPool_Group_GF12_Human_Route">
</p>
We have tuned the timing constraints for the BlackParrot (Quad-Core) and MemPool Group designs on GF12. The results of different MacroPlacer solutions
for the tuned designs are as follows:
- **BlackParrot (Quad-Core)-GF12-68% CMP**: The subsequent table and screenshots presents the post P\&R details of BlackParrot (Quad-Core) design on GF12 enablement when the macro placement is generated by CMP.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">BlackParot-GF12-68% Innovus CMP [results are normalized as described <a href="#GF12_Normalization">here</a>]</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS (ns)</td>
<td>TNS (ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1</td>
<td>0.188</td>
<td>0.498</td>
<td>1.000</td>
<td>1.000</td>
<td>-0.099</td>
<td>-230.148</td>
<td>1.00</td>
<td>1.00</td>
</tr>
<tr>
<td>postCTS</td>
<td>1</td>
<td>0.190</td>
<td>0.498</td>
<td>1.148</td>
<td>1.009</td>
<td>-0.080</td>
<td>-93.367</td>
<td>1.00</td>
<td>1.00</td>
</tr>
<tr>
<td>postRoute</td>
<td>1</td>
<td>0.190</td>
<td>0.498</td>
<td>1.138</td>
<td>1.033</td>
<td>-0.171</td>
<td>-1033.653</td>
<td></td>
<td></td>
</tr>
<tr>
<td>postRouteOpt</td>
<td>1</td>
<td>0.190</td>
<td>0.498</td>
<td>1.138</td>
<td>1.034</td>
<td>-0.087</td>
<td>-138.918</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/BlackParrot_GF12_Tuned_CMP_Place.png" alg="BlackParrot_GF12_Tuned_CMP_Place">
<img width="300" src="./images/BlackParrot_GF12_Tuned_CMP_Route.png" alg="BlackParrot_GF12_Tuned_CMP_Route">
</p>
- **BlackParrot (Quad-Core)-GF12-68% SA**: The subsequent table and screenshots presents the post P\&R details of BlackParrot (Quad-Core) design on GF12 enablement when the macro placement is generated by SA.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">BlackParrot-GF12-68% SA (wirelength cost: 0.0576, congestion cost: 0.6619, density cost: 0.5971, proxy cost: 0.6871) [results are normalized as described <a href="#GF12_Normalization">here</a>]</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS (ns)</td>
<td>TNS (ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1</td>
<td>0.189</td>
<td>0.498</td>
<td>1.030</td>
<td>1.239</td>
<td>-0.119</td>
<td>-234.785</td>
<td>1.00</td>
<td>1.40</td>
</tr>
<tr>
<td>postCTS</td>
<td>1</td>
<td>0.191</td>
<td>0.498</td>
<td>1.183</td>
<td>1.246</td>
<td>-0.111</td>
<td>-159.242</td>
<td>1.00</td>
<td>1.80</td>
</tr>
<tr>
<td>postRoute</td>
<td>1</td>
<td>0.191</td>
<td>0.498</td>
<td>1.171</td>
<td>1.274</td>
<td>-0.296</td>
<td>-4161.765</td>
<td></td>
<td></td>
</tr>
<tr>
<td>postRouteOpt</td>
<td>1</td>
<td>0.191</td>
<td>0.498</td>
<td>1.175</td>
<td>1.275</td>
<td>-0.160</td>
<td>-325.995</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/BlackParrot_GF12_Tuned_SA_Place.png" alg="BlackParrot_GF12_Tuned_SA_Place">
<img width="300" src="./images/BlackParrot_GF12_Tuned_SA_Route.png" alg="BlackParrot_GF12_Tuned_SA_Route">
</p>
- **BlackParrot (Quad-Core)-GF12-68% Human Expert**: The subsequent table and screenshots presents the post P\&R details of BlackParrot (Quad-Core) design on GF12 enablement when the macro placement is generated by Huamn Expert.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">BlackParot-GF12-68% Human Expert [results are normalized as described <a href="#GF12_Normalization">here</a>]</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS (ns)</td>
<td>TNS (ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1</td>
<td>0.189</td>
<td>0.498</td>
<td>1.010</td>
<td>1.065</td>
<td>-0.107</td>
<td>-264.618</td>
<td>1.00</td>
<td>2.60</td>
</tr>
<tr>
<td>postCTS</td>
<td>1</td>
<td>0.190</td>
<td>0.498</td>
<td>1.157</td>
<td>1.074</td>
<td>-0.048</td>
<td>-40.525</td>
<td>2.00</td>
<td>3.20</td>
</tr>
<tr>
<td>postRoute</td>
<td>1</td>
<td>0.190</td>
<td>0.498</td>
<td>1.148</td>
<td>1.106</td>
<td>-0.266</td>
<td>-340.181</td>
<td></td>
<td></td>
</tr>
<tr>
<td>postRouteOpt</td>
<td>1</td>
<td>0.189</td>
<td>0.498</td>
<td>1.144</td>
<td>1.107</td>
<td>-0.049</td>
<td>-15.400</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/BlackParrot_GF12_Tuned_Human_Place.png" alg="BlackParrot_GF12_Tuned_Human_Place">
<img width="300" src="./images/BlackParrot_GF12_Tuned_Human_Route.png" alg="BlackParrot_GF12_Tuned_Human_Route">
</p>
- **BlackParrot (Quad-Core)-GF12-68% AutoDMP**: The subsequent table and screenshots presents the post P\&R details of BlackParrot (Quad-Core) design on GF12 enablement when the macro placement is generated by AutoDMP (Nvidia).
<table>
<thead>
<tr>
<th colspan="10"><p align="center">BlackParot-GF12-68% AutoDMP [results are normalized as described <a href="#GF12_Normalization">here</a>]</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS (ns)</td>
<td>TNS (ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1</td>
<td>0.189</td>
<td>0.498</td>
<td>1.005</td>
<td>1.008</td>
<td>-0.136</td>
<td>-254.904</td>
<td>1.00</td>
<td>1.00</td>
</tr>
<tr>
<td>postCTS</td>
<td>1</td>
<td>0.191</td>
<td>0.498</td>
<td>1.153</td>
<td>1.017</td>
<td>-0.076</td>
<td>-99.649</td>
<td>1.00</td>
<td>1.20</td>
</tr>
<tr>
<td>postRoute</td>
<td>1</td>
<td>0.191</td>
<td>0.498</td>
<td>1.143</td>
<td>1.043</td>
<td>-0.253</td>
<td>-361.892</td>
<td></td>
<td></td>
</tr>
<tr>
<td>postRouteOpt</td>
<td>1</td>
<td>0.190</td>
<td>0.498</td>
<td>1.140</td>
<td>1.043</td>
<td>-0.062</td>
<td>-61.772</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/BlackParrot_GF12_Tuned_AutoDMP_Place.png" alg="BlackParrot_GF12_Tuned_AutoDMP_Place">
<img width="300" src="./images/BlackParrot_GF12_Tuned_AutoDMP_Route.png" alg="BlackParrot_GF12_Tuned_AutoDMP_Route">
</p>
- **BlackParrot (Quad-Core)-GF12-68% Hier-RTLMP**: The subsequent table and screenshots presents the post P\&R details of BlackParrot (Quad-Core) design on GF12 enablement when the macro placement is generated by Hier-RTLMP.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">BlackParrot-GF12-68% Hier-RTLMP [results are normalized as described <a href="#GF12_Normalization">here</a>]</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS (ns)</td>
<td>TNS (ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1</td>
<td>0.188</td>
<td>0.498</td>
<td>1.035</td>
<td>1.249</td>
<td>-0.100</td>
<td>-214.208</td>
<td>2.00</td>
<td>1.60</td>
</tr>
<tr>
<td>postCTS</td>
<td>1</td>
<td>0.190</td>
<td>0.498</td>
<td>1.188</td>
<td>1.257</td>
<td>-0.079</td>
<td>-102.866</td>
<td>1.00</td>
<td>1.80</td>
</tr>
<tr>
<td>postRoute</td>
<td>1</td>
<td>0.190</td>
<td>0.498</td>
<td>1.177</td>
<td>1.288</td>
<td>-0.213</td>
<td>-339.322</td>
<td></td>
<td></td>
</tr>
<tr>
<td>postRouteOpt</td>
<td>1</td>
<td>0.190</td>
<td>0.498</td>
<td>1.173</td>
<td>1.289</td>
<td>-0.082</td>
<td>-54.313</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/BlackParrot_GF12_Tuned_HierRTLMP_Place.png" alg="BlackParrot_GF12_Tuned_HierRTLMP_Place">
<img width="300" src="./images/BlackParrot_GF12_Tuned_HierRTLMP_Route.png" alg="BlackParrot_GF12_Tuned_HierRTLMP_Route">
</p>
- **MemPool Group-GF12-68% CMP**: The subsequent table and screenshots presents the post P\&R details of MemPool Group design on GF12 enablement when the macro placement is generated by CMP.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">MemPool Group-GF12-68% Innovus CMP [results are normalized as described <a href="#GF12_Normalization">here</a>]</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS (ns)</td>
<td>TNS (ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1</td>
<td>0.412</td>
<td>0.312</td>
<td>1.000</td>
<td>1.000</td>
<td>-0.073</td>
<td>-4486.957</td>
<td>1.00</td>
<td>1.00</td>
</tr>
<tr>
<td>postCTS</td>
<td>1</td>
<td>0.403</td>
<td>0.312</td>
<td>1.056</td>
<td>1.007</td>
<td>-0.058</td>
<td>-196.767</td>
<td>1.00</td>
<td>1.00</td>
</tr>
<tr>
<td>postRoute</td>
<td>1</td>
<td>0.403</td>
<td>0.312</td>
<td>1.055</td>
<td>1.048</td>
<td>-0.126</td>
<td>-2495.000</td>
<td></td>
<td></td>
</tr>
<tr>
<td>postRouteOpt</td>
<td>1</td>
<td>0.393</td>
<td>0.312</td>
<td>1.025</td>
<td>1.051</td>
<td>-0.101</td>
<td>-167.530</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/MemPool_Group_GF12_Tuned_CMP_Place.png" alg="MemPool_Group_GF12_Tuned_CMP_Place">
<img width="300" src="./images/MemPool_Group_GF12_Tuned_CMP_Route.png" alg="MemPool_Group_GF12_Tuned_CMP_Route">
</p>
- **MemPool Group-GF12-68% CT**: The subsequent table and screenshots presents the post P\&R details of MemPool Group design on GF12 enablement when the macro placement is generated by CT.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">MemPool Group-GF12-68% CT (Wirelength cost: 0.069, Congestion cost: 0.810, Density Cost: 1.039, Proxy Cost: 0.994) (<a href="https://tensorboard.dev/experiment/TdW3lCz3SESNWoAkkHYJEA/#scalars">Link</a> to tensorboard) [results are normalized as described <a href="#GF12_Normalization">here</a>]</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS (ns)</td>
<td>TNS (ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1</td>
<td>0.416</td>
<td>0.312</td>
<td>1.085</td>
<td>1.189</td>
<td>-0.085</td>
<td>-5086.783</td>
<td>0.76</td>
<td>1.25</td>
</tr>
<tr>
<td>postCTS</td>
<td>1</td>
<td>0.409</td>
<td>0.312</td>
<td>1.153</td>
<td>1.196</td>
<td>-0.090</td>
<td>-578.565</td>
<td>0.73</td>
<td>1.33</td>
</tr>
<tr>
<td>postRoute</td>
<td>1</td>
<td>0.409</td>
<td>0.312</td>
<td>1.154</td>
<td>1.244</td>
<td>-0.196</td>
<td>-5010.696</td>
<td></td>
<td></td>
</tr>
<tr>
<td>postRouteOpt</td>
<td>1</td>
<td>0.400</td>
<td>0.312</td>
<td>1.124</td>
<td>1.247</td>
<td>-0.087</td>
<td>-124.331</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/MemPool_Group_GF12_Tuned_CT_Place.png" alg="MemPool_Group_GF12_Tuned_CT_Place">
<img width="300" src="./images/MemPool_Group_GF12_Tuned_CT_Route.png" alg="MemPool_Group_GF12_Tuned_CT_Route">
</p>
- **MemPool Group-GF12-68% SA**: The subsequent table and screenshots presents the post P\&R details of MemPool Group design on GF12 enablement when the macro placement is generated by SA.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">MemPool Group-GF12-68% SA (Wirelength cost: 0.064, Congestion cost: 0.940, Density Cost: 1.325, Proxy Cost: 1.196) [results are normalized as described <a href="#GF12_Normalization">here</a>]</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS (ns)</td>
<td>TNS (ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1</td>
<td>0.415</td>
<td>0.312</td>
<td>1.081</td>
<td>1.187</td>
<td>-0.083</td>
<td>-5070.000</td>
<td>1.29</td>
<td>1.42</td>
</tr>
<tr>
<td>postCTS</td>
<td>1</td>
<td>0.408</td>
<td>0.312</td>
<td>1.138</td>
<td>1.197</td>
<td>-0.094</td>
<td>-415.182</td>
<td>1.32</td>
<td>1.52</td>
</tr>
<tr>
<td>postRoute</td>
<td>1</td>
<td>0.408</td>
<td>0.312</td>
<td>1.145</td>
<td>1.248</td>
<td>-0.149</td>
<td>-4161.478</td>
<td></td>
<td></td>
</tr>
<tr>
<td>postRouteOpt</td>
<td>1</td>
<td>0.403</td>
<td>0.312</td>
<td>1.130</td>
<td>1.250</td>
<td>-0.077</td>
<td>-262.988</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/MemPool_Group_GF12_Tuned_SA_Place.png" alg="MemPool_Group_GF12_Tuned_SA_Place">
<img width="300" src="./images/MemPool_Group_GF12_Tuned_SA_Route.png" alg="MemPool_Group_GF12_Tuned_SA_Route">
</p>
- **MemPool Group-GF12-68% Human Expert**: The subsequent table and screenshots presents the post P\&R details of MemPool Group design on GF12 enablement when the macro placement is generated by Human Expert.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">MemPool Group-GF12-68% Human Expert [results are normalized as described <a href="#GF12_Normalization">here</a>]</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS (ns)</td>
<td>TNS (ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1</td>
<td>0.414</td>
<td>0.312</td>
<td>1.027</td>
<td>1.065</td>
<td>-0.081</td>
<td>-4820.478</td>
<td>0.48</td>
<td>1.00</td>
</tr>
<tr>
<td>postCTS</td>
<td>1</td>
<td>0.407</td>
<td>0.312</td>
<td>1.092</td>
<td>1.070</td>
<td>-0.062</td>
<td>-357.957</td>
<td>0.55</td>
<td>1.04</td>
</tr>
<tr>
<td>postRoute</td>
<td>1</td>
<td>0.407</td>
<td>0.312</td>
<td>1.091</td>
<td>1.113</td>
<td>-0.142</td>
<td>-3350.652</td>
<td></td>
<td></td>
</tr>
<tr>
<td>postRouteOpt</td>
<td>1</td>
<td>0.398</td>
<td>0.312</td>
<td>1.059</td>
<td>1.116</td>
<td>-0.075</td>
<td>-105.913</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/MemPool_Group_GF12_Tuned_Human_Place.png" alg="MemPool_Group_GF12_Tuned_Human_Place">
<img width="300" src="./images/MemPool_Group_GF12_Tuned_Human_Route.png" alg="MemPool_Group_GF12_Tuned_Human_Route">
</p>
- **MemPool Group-GF12-68% AutoDMP**: The subsequent table and screenshots presents the post P\&R details of MemPool Group design on GF12 enablement when the macro placement is generated by AutoDMP (Nvidia).
<table>
<thead>
<tr>
<th colspan="10"><p align="center">MemPool Group-GF12-68% AutoDMP [results are normalized as described <a href="#GF12_Normalization">here</a>]</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS (ns)</td>
<td>TNS (ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1</td>
<td>0.415</td>
<td>0.312</td>
<td>1.015</td>
<td>1.037</td>
<td>-0.105</td>
<td>-5260.304</td>
<td>1.00</td>
<td>1.13</td>
</tr>
<tr>
<td>postCTS</td>
<td>1</td>
<td>0.407</td>
<td>0.312</td>
<td>1.078</td>
<td>1.044</td>
<td>-0.104</td>
<td>-517.435</td>
<td>1.00</td>
<td>1.22</td>
</tr>
<tr>
<td>postRoute</td>
<td>1</td>
<td>0.407</td>
<td>0.312</td>
<td>1.077</td>
<td>1.089</td>
<td>-0.116</td>
<td>-3304.174</td>
<td></td>
<td></td>
</tr>
<tr>
<td>postRouteOpt</td>
<td>1</td>
<td>0.400</td>
<td>0.312</td>
<td>1.054</td>
<td>1.091</td>
<td>-0.103</td>
<td>-267.739</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/MemPool_Group_GF12_Tuned_AutoDMP_Place.png" alg="MemPool_Group_GF12_Tuned_AutoDMP_Place">
<img width="300" src="./images/MemPool_Group_GF12_Tuned_AutoDMP_Route.png" alg="MemPool_Group_GF12_Tuned_AutoDMP_Route">
</p>
- **MemPool Group-GF12-68% Hier-RTLMP**: The subsequent table and screenshots presents the post P\&R details of MemPool Group design on GF12 enablement when the macro placement is generated by Hier-RTLMP.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">MemPool Group-GF12-68% Hier-RTLMP [results are normalized as described <a href="#GF12_Normalization">here</a>]</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS (ns)</td>
<td>TNS (ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1</td>
<td>0.411</td>
<td>0.312</td>
<td>1.031</td>
<td>1.086</td>
<td>-0.076</td>
<td>-4525.696</td>
<td>0.62</td>
<td>0.92</td>
</tr>
<tr>
<td>postCTS</td>
<td>1</td>
<td>0.405</td>
<td>0.312</td>
<td>1.100</td>
<td>1.095</td>
<td>-0.072</td>
<td>-394.957</td>
<td>0.68</td>
<td>1.04</td>
</tr>
<tr>
<td>postRoute</td>
<td>1</td>
<td>0.405</td>
<td>0.312</td>
<td>1.101</td>
<td>1.138</td>
<td>-0.139</td>
<td>-3301.739</td>
<td></td>
<td></td>
</tr>
<tr>
<td>postRouteOpt</td>
<td>1</td>
<td>0.397</td>
<td>0.312</td>
<td>1.074</td>
<td>1.140</td>
<td>-0.068</td>
<td>-94.348</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/MemPool_Group_GF12_Tuned_HierRTLMP_Place.png" alg="MemPool_Group_GF12_Tuned_HierRTLMP_Place">
<img width="300" src="./images/MemPool_Group_GF12_Tuned_HierRTLMP_Route.png" alg="MemPool_Group_GF12_Tuned_HierRTLMP_Route">
</p>
**An Observation regarding "Pure Commercial Flow".**
<a id="PureCommercialFlow"></a>
......
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