Update the scripts for ariane136 to streamline flow1 and flow2

Signed-off-by: Ravi Varadarajan <rvaradarajan@ucsd.edu>

Flows/NanGate45/ariane136/scripts/cadence/design_setup.tcl

@@ -4,8 +4,14 @@
 set DESIGN ariane 
 set sdc  ../../constraints/${DESIGN}.sdc
 
-# def file with die size and placed IO pins
-set floorplan_def ../../def/ariane136_fp_rows.def
+#
+# DEF file for floorplan initialization
+#
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    set floorplan_def ../../def/ariane_fp_placed_macros.def
+} else {
+    set floorplan_def ../../def/ariane136_fp_rows.def
+}
 #
 # Effort level during optimization in syn_generic -physical (or called generic) stage
 # possible values are : high, medium or low

Flows/NanGate45/ariane136/scripts/cadence/gen_mp_config.tcl

-# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. 
-# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
-puts "VERSION 1.0"
-set mem_hier ""
-foreach a [dbget [dbget top.insts.cell.name fakeram45_* -p2 ].name ] {
-    regexp {(.*)(/)([^/]*)} $a c b
-    lappend mem_hier $b
-}
-set unique_mem_hier [lsort -unique $mem_hier]
-puts "BEGIN SEED"
-foreach a $unique_mem_hier {
-puts "name=$a util=$util"
-}
-puts "END SEED"
-
-puts "BEGIN MACRO"
-foreach a [dbget top.insts.cell.name fakeram45_* -u] {
-puts "name=$a  orient={R0} isCell=true minRightSpace=10 minLeftSpace=10 minTopSpace=5 minBottomSpace=5"
-}
-puts "END MACRO"
-
-puts "BEGIN CONSTRAINT"
-puts "END CONSTRAINT"

Flows/NanGate45/ariane136/scripts/cadence/mp_config.tcl

-# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. 
-# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
-##########################################
-# Masterplan User Constraint File Template
-##########################################
-
-###########################################################
-# Syntax Convention:                                      #
-# [] means optional                                       #
-# <> means filling with real value or name in your design #
-# () indicates the unit name for your value               #
-# | means OR                                              #
-# {} is used to enclose a group of names (one or more)    #
-# ... means more similar items                            #
-###########################################################
-
-
-###########################################################
-# Version section (required on and after Innovus 10.1)  #
-# If not provided, will be parsed as older format         #
-# VERSION <N.N>                                           #
-# For example:                                            #
-###########################################################
-VERSION 1.0
-
-
-######################################################################
-# Seed Section (optional) : one single line per seed                 #
-# name=<seedName> [util=<float>] [createFence=true]\                 #
-#    [minWHRatio=<float>] [maxWHRatio=<float>]\                      #
-#    [minFenceToFenceSpace=<(um)>] [minFenceToCoreSpace=<(um)>]\     #
-#    [minFenceToInsideMacroSpace=<(um)>]\                            #
-#    [minFenceToOutsideMacroSpace=<(um)>]\                           #
-#    [minInsideFenceMacroToMacroSpace=<(um)>]\                       #
-#    [master=<nameOrOtherName>] [cloneOrient={R0|MX|MY|R180}]        #
-# For example:                                                       #
-######################################################################
-BEGIN SEED
-name=i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_1__i_ram
-name=i_cache_subsystem/i_icache/sram_block_0__tag_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_1__i_ram
-name=i_cache_subsystem/i_icache/sram_block_1__tag_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_1__i_ram
-name=i_cache_subsystem/i_icache/sram_block_2__tag_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_1__i_ram
-name=i_cache_subsystem/i_icache/sram_block_3__tag_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_1__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_0__tag_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_1__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_1__tag_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_2__data_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_2__data_sram/genblk1_1__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_2__tag_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_3__data_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_3__data_sram/genblk1_1__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_3__tag_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_4__data_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_4__data_sram/genblk1_1__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_4__tag_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_5__data_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_5__data_sram/genblk1_1__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_5__tag_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_6__data_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_6__data_sram/genblk1_1__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_6__tag_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_7__data_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_7__data_sram/genblk1_1__i_ram
-name=i_cache_subsystem/i_nbdcache/sram_block_7__tag_sram/genblk1_0__i_ram
-name=i_cache_subsystem/i_nbdcache/valid_dirty_sram/genblk1_0__i_ram
-END SEED
-
-
-######################################################################
-# MACRO section syntax  : one single line per macro                  #
-# name=<InstOrCell> [minLeftSpace=<(um)>] [minRightSpace=<(um)>]\    #
-#                   [minTopSpace=<(um)>] [minBottomSpace=<(um)>]\    #
-#                   [orient={R0|MX|MY|R180|MX90|R90|R270|MY90}]\     #
-#                   [isCell=true] [minMacroToCoreSpace=<(um)>]       #
-# For example:                                                       #
-######################################################################
-BEGIN MACRO
-name=fakeram45_256x16 orient={R0} isCell=true minRightSpace=10 minLeftSpace=10 minTopSpace=5 minBottomSpace=5
-END MACRO
-
-
-#################################################################################
-# relative placement CONSTRAINT section syntax                                  #
-# name=<HInstOrGroupOrHM> loc=<T|B|R|L|TL|TR|BL|BR|(x,y)>                       #
-# name=<NewName> members={<Module1> <Module2> <Module3>..} [strength=Soft|Hard] #
-# For example:                                                                  #
-#################################################################################
-BEGIN CONSTRAINT
-END CONSTRAINT

Flows/NanGate45/ariane136/scripts/cadence/run.sh

@@ -6,6 +6,10 @@ module load genus/21.1
 module unload innovus
 module load innovus/21.1
 
+#
+# To run the Physical Synthesis (iSpatial) flow - flow2
+export PHY_SYNTH=1
+
 mkdir log -p
-genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl
+genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
 innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log

Flows/NanGate45/ariane136/scripts/cadence/run_genus_hybrid.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    read_mmmc mmmc_iSpatial_setup.tcl
+}
+
+# set the output directories
+set OUTPUTS_PATH  syn_output
+set REPORTS_PATH  syn_rpt
+set HANDOFF_PATH  syn_handoff
+
+if {![file exists ${OUTPUTS_PATH}]} {
+  file mkdir ${OUTPUTS_PATH}
+}
+
+if {![file exists ${REPORTS_PATH}]} {
+  file mkdir ${REPORTS_PATH}
+}
+
+if {![file exists ${HANDOFF_PATH}]} {
+  file mkdir ${HANDOFF_PATH}
+}
+#
+# set threads
+set_db max_cpus_per_server 16
+set_db super_thread_servers "localhost"
+#
+set list_lib "$libworst"
+
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
+    read_physical -lefs $lefs
+}
+
+# Target library
+set link_library $list_lib
+set target_library $list_lib
+
+# set pathi
+set_db hdl_flatten_complex_port true
+set_db hdl_record_naming_style  %s_%s
+set_db auto_ungroup none
+
+
+if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
+    set_db library $list_lib
+}
+
+#################################################
+# Load Design and Initialize
+#################################################
+
+source rtl_list.tcl
+
+foreach rtl_file $rtl_all {
+    read_hdl -sv $rtl_file
+}
+
+elaborate $DESIGN
+time_info Elaboration
+
+if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
+    read_sdc $sdc
+}
+
+init_design
+
+check_design -unresolved
+
+check_timing_intent
+# reports the physical layout estimation report from lef and QRC tech file
+report_ple > ${REPORTS_PATH}/ple.rpt 
+
+###############################################
+# Read DEF
+###############################################
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    read_def $floorplan_def
+    check_floorplan -detailed
+}
+
+# keep hierarchy during synthesis
+set_db auto_ungroup none
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_generic -physical
+} else {
+    syn_generic
+}
+time_info GENERIC
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag generic
+write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
+
+ 
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_map -physical
+} else {
+    syn_map
+}
+time_info MAPPED
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag map
+write_db  ${OUTPUTS_PATH}/${DESIGN}_map.db
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_opt -spatial
+} else {
+    syn_opt
+}
+
+time_info OPT 
+write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
+
+##############################################################################
+# Write reports
+##############################################################################
+
+# summarizes the information, warnings and errors
+report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
+
+# generate PPA reports
+report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
+report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
+report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
+write_reports -directory ${REPORTS_PATH} -tag final 
+
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+} else {
+    write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
+    write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
+}
+
+exit

Flows/NanGate45/ariane136/scripts/cadence/run_invs.tcl

@@ -56,22 +56,17 @@ generateVias
 createBasicPathGroups -expanded
 
 ## Generate the floorplan ##
-#floorPlan -r 1.0 $util 10 10 10 10
+
 defIn $floorplan_def 
 
 ## Macro Placement ##
-#redirect mp_config.tcl {source gen_mp_config.tcl}
-#proto_design -constraints mp_config.tcl 
-addHaloToBlock -allMacro 5 5 5 5
-place_design -concurrent_macros
-refine_macro_place
-saveDesign ${encDir}/${DESIGN}_floorplan.enc
 
-## Creating Pin Blcokage for lower and upper pin layers ##
-createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
-createPinBlkg -name side_top -edge 1
-createPinBlkg -name side_right -edge 2
-createPinBlkg -name side_bottom -edge 3
+if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
+    addHaloToBlock -allMacro 5 5 5 5
+    place_design -concurrent_macros
+    refine_macro_place
+}
+saveDesign ${encDir}/${DESIGN}_floorplan.enc
 
 setPlaceMode -place_detail_legalization_inst_gap 1
 setFillerMode -fitGap true