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Unverified Commit 2080fbab by Sayak Kundu Committed by GitHub
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Merge pull request #29 from TILOS-AI-Institute/flow_scripts 

Flow scripts
parents c1475daa 9ddf6f16
Showing with 2183 additions and 111 deletions
Flows/ASAP7/ariane133/scripts/cadence/run_genus_hybrid.tcl
......@@ -136,6 +136,7 @@ write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
......
Flows/ASAP7/ariane133/scripts/cadence/run_invs.tcl
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
setLibraryUnit -time 1.0ps
source lib_setup.tcl
source design_setup.tcl
source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
......@@ -12,6 +10,7 @@ set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
source mmmc_setup.tcl
set rptDir summaryReport/
set encDir enc/
......@@ -40,6 +39,8 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setAnalysisMode -reset
setAnalysisMode -analysisType onChipVariation -cppr both
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -69,6 +70,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
#snapFPlan -pin
}
### Write postSynth report ###
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_post_synth [extract_report postSynth]
echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
### Write out the def files ###
source ../../../../util/write_required_def.tcl
......@@ -86,8 +93,6 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......@@ -147,6 +152,11 @@ echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
#route_opt_design
optDesign -postRoute
set rpt_post_route [extract_report postRouteOpt]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
......
Flows/ASAP7/ariane136/scripts/cadence/run_genus_hybrid.tcl
......@@ -136,6 +136,7 @@ write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
......
Flows/ASAP7/ariane136/scripts/cadence/run_invs.tcl
......@@ -3,7 +3,6 @@
setLibraryUnit -time 1.0ps
source lib_setup.tcl
source design_setup.tcl
source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
......@@ -12,6 +11,7 @@ set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
source mmmc_setup.tcl
set rptDir summaryReport/
set encDir enc/
......@@ -40,6 +40,8 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setAnalysisMode -reset
setAnalysisMode -analysisType onChipVariation -cppr both
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -69,6 +71,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
#snapFPlan -pin
}
### Write postSynth report ###
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_post_synth [extract_report postSynth]
echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
### Write out the def files ###
source ../../../../util/write_required_def.tcl
......@@ -86,8 +94,6 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......@@ -147,6 +153,11 @@ echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
#route_opt_design
optDesign -postRoute
set rpt_post_route [extract_report postRouteOpt]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
......
Flows/ASAP7/mempool_tile/constraints/mempool_tile_wrap.sdc
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/ASAP7/mempool_tile/scripts/cadence/run_genus_hybrid.tcl
......@@ -136,6 +136,7 @@ write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
......
Flows/ASAP7/mempool_tile/scripts/cadence/run_invs.tcl
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
setLibraryUnit -time 1.0ps
source lib_setup.tcl
source design_setup.tcl
source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
......@@ -12,6 +10,7 @@ set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
source mmmc_setup.tcl
set rptDir summaryReport/
set encDir enc/
......@@ -40,6 +39,8 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setAnalysisMode -reset
setAnalysisMode -analysisType onChipVariation -cppr both
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -69,6 +70,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
#snapFPlan -pin
}
### Write postSynth report ###
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_post_synth [extract_report postSynth]
echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
### Write out the def files ###
source ../../../../util/write_required_def.tcl
......@@ -86,8 +93,6 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......@@ -147,6 +152,11 @@ echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
#route_opt_design
optDesign -postRoute
set rpt_post_route [extract_report postRouteOpt]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
......
Flows/ASAP7/nvdla/scripts/cadence/run_genus_hybrid.tcl
......@@ -137,6 +137,7 @@ write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
......
Flows/ASAP7/nvdla/scripts/cadence/run_invs.tcl
......@@ -3,7 +3,6 @@
setLibraryUnit -time 1.0ps
source lib_setup.tcl
source design_setup.tcl
source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
......@@ -12,6 +11,7 @@ set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
source mmmc_setup.tcl
set rptDir summaryReport/
set encDir enc/
......@@ -40,6 +40,8 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setAnalysisMode -reset
setAnalysisMode -analysisType onChipVariation -cppr both
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -69,6 +71,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
#snapFPlan -pin
}
### Write postSynth report ###
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_post_synth [extract_report postSynth]
echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
### Write out the def files ###
source ../../../../util/write_required_def.tcl
......@@ -86,8 +94,6 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......@@ -147,6 +153,11 @@ echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
#route_opt_design
optDesign -postRoute
set rpt_post_route [extract_report postRouteOpt]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
......
Flows/NanGate45/ariane133/constraints/ariane.sdc
#period set in nano-seconds - currently: 4ns = 250 MHz freq
create_clock [get_ports clk_i] -name core_clock -period 4
create_clock [get_ports clk_i] -name core_clock -period 1.3
Flows/NanGate45/ariane133/scripts/cadence/mmmc_setup.tcl
......@@ -4,8 +4,8 @@
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
create_rc_corner -name Cmax
create_rc_corner -name Cmin
create_rc_corner -name Cmax -qx_tech_file $qrc_max
create_rc_corner -name Cmin -qx_tech_file $qrc_min
create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
......
Flows/NanGate45/ariane133/scripts/cadence/run_genus_hybrid.tcl
......@@ -136,6 +136,7 @@ write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
......
Flows/NanGate45/ariane133/scripts/cadence/run_invs.tcl
......@@ -68,6 +68,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
refine_macro_place
}
### Write postSynth report ###
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_post_synth [extract_report postSynth]
echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
### Write out the def files ###
source ../../../../util/write_required_def.tcl
......@@ -85,8 +91,6 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......@@ -134,15 +138,15 @@ defOut -netlist -floorplan -routing ${DESIGN}_route.def
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
#route_opt_design
optDesign -postRoute
set rpt_post_route [extract_report postRouteOpt]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
......
Flows/NanGate45/ariane136/constraints/ariane.sdc
#period set in nano-seconds - currently: 2ns = 500 MHz freq
create_clock [get_ports clk_i] -name core_clock -period 4
create_clock [get_ports clk_i] -name core_clock -period 1.3
#
#set_input_delay -clock core_clock 0 [get_ports clk_i]
#set_input_delay -clock core_clock 0 [get_ports rst_ni]
......
Flows/NanGate45/ariane136/scripts/cadence/mmmc_setup.tcl
......@@ -4,8 +4,8 @@
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
create_rc_corner -name Cmax
create_rc_corner -name Cmin
create_rc_corner -name Cmax -qx_tech_file $qrc_max
create_rc_corner -name Cmin -qx_tech_file $qrc_min
create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
......
Flows/NanGate45/ariane136/scripts/cadence/run_genus_hybrid.tcl
......@@ -136,6 +136,7 @@ write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
......
Flows/NanGate45/ariane136/scripts/cadence/run_invs.tcl
......@@ -2,7 +2,6 @@
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
......@@ -11,6 +10,7 @@ set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
source mmmc_setup.tcl
set rptDir summaryReport/
set encDir enc/
......@@ -39,6 +39,8 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setAnalysisMode -reset
setAnalysisMode -analysisType onChipVariation -cppr both
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -66,6 +68,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
refine_macro_place
}
### Write postSynth report ###
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_post_synth [extract_report postSynth]
echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
### Write out the def files ###
source ../../../../util/write_required_def.tcl
......@@ -83,8 +91,6 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......@@ -137,6 +143,11 @@ set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
#route_opt_design
optDesign -postRoute
set rpt_post_route [extract_report postRouteOpt]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
......
Flows/NanGate45/bp_quad/constraints/bsg_chip.sdc 0 → 100644
###################################################################
# Created by write_sdc on Wed Sep 29 06:31:20 2021
###################################################################
set sdc_version 2.0
set_units -time ps -resistance kOhm -capacitance fF -power mW -voltage V \
-current uA
create_clock [get_ports p_bsg_tag_clk_i] -name tag_clk -period 11200 -waveform {0 5600}
set_clock_uncertainty -hold 150 [get_clocks tag_clk]
create_clock [get_ports p_clk_A_i] -name bp_clk -period 2800 -waveform {0 1400}
set_clock_uncertainty 150 [get_clocks bp_clk]
create_clock [get_ports p_clk_B_i] -name io_master_clk -period 2800 -waveform {0 1400}
set_clock_uncertainty 150 [get_clocks io_master_clk]
create_clock [get_ports p_clk_C_i] -name router_clk -period 2800 -waveform {0 1400}
set_clock_uncertainty 150 [get_clocks router_clk]
create_clock [get_ports p_ci_clk_i] -name sdi_a_clk -period 5600 -waveform {0 2800}
set_clock_uncertainty 150 [get_clocks sdi_a_clk]
create_clock [get_ports p_ci2_tkn_i] -name sdo_a_tkn_clk -period 5600 -waveform {0 2800}
set_clock_uncertainty 150 [get_clocks sdo_a_tkn_clk]
create_clock [get_ports p_co_clk_i] -name sdi_b_clk -period 5600 -waveform {0 2800}
set_clock_uncertainty 150 [get_clocks sdi_b_clk]
create_clock [get_ports p_co2_tkn_i] -name sdo_b_tkn_clk -period 5600 -waveform {0 2800}
set_clock_uncertainty 150 [get_clocks sdo_b_tkn_clk]
#
set_multicycle_path 0 -hold -to [list [get_ports p_ci2_clk_o] [get_ports \
p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o] \
[get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports \
p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]]
set_multicycle_path 1 -setup -to [list [get_ports p_ci2_clk_o] [get_ports \
p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o] \
[get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports \
p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]]
set_multicycle_path 0 -hold -to [list [get_ports p_co2_clk_o] [get_ports \
p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o] \
[get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports \
p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]]
set_multicycle_path 1 -setup -to [list [get_ports p_co2_clk_o] [get_ports \
p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o] \
[get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports \
p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]]
set_false_path -from [get_clocks router_clk] -to [get_clocks bp_clk]
set_false_path -from [get_clocks tag_clk] -to [get_clocks bp_clk]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_clk_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_clk_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_clk_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_clk_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_clk_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_clk_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_clk_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_clk_i]
set_input_delay -clock tag_clk 3333 [get_ports p_bsg_tag_data_i]
set_input_delay -clock tag_clk 3333 [get_ports p_bsg_tag_en_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_v_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_v_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_v_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_v_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_0_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_0_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_0_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_0_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_1_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_1_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_1_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_1_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_2_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_2_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_2_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_2_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_3_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_3_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_3_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_3_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_4_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_4_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_4_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_4_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_5_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_5_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_5_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_5_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_6_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_6_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_6_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_6_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_7_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_7_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_7_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_7_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_8_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_8_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_8_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_8_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_v_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_v_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_v_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_v_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_0_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_0_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_0_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_0_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_1_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_1_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_1_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_1_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_2_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_2_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_2_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_2_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_3_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_3_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_3_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_3_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_4_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_4_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_4_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_4_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_5_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_5_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_5_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_5_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_6_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_6_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_6_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_6_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_7_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_7_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_7_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_7_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_8_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_8_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_8_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_8_i]
set_timing_derate -early -cell_delay 0.97 [get_cells \
{bp_processor/cc/y_0__x_0__tile_node/tile/core/fe/mem/icache/tag_mem/macro_bmem/db1_wb_0__bank/macro_mem}]
Flows/NanGate45/bp_quad/scripts/cadence/.rs_ravi.tstamp 0 → 100644
array set allMetrics {-1,wall 1663844835}
array set allMetrics {pbs_debug:9,date { 6:09:12 (Sep22)} pbs_debug:11,date { 6:14:20 (Sep22)} pbs_debug:4,multiInfo {{{Total Time} {{clock 01:28:32} {lthread 01:27:41}}} {{Stage Time} {{clock 00:00:26} {lthread 00:00:26}}} {{% Time} {{clock { 0.5}} {lthread 0.46810685634366117<PREC(5.1)>}}}} pbs_debug:6,date { 6:06:07 (Sep22)} pbs_debug:7,tcount 16 pbs_debug:14,all 27892.0 pbs_debug:6,all 25231.0 pbs_debug:10,cpuload 5.00 pbs_debug:3,date { 5:35:21 (Sep22)} pbs_debug:14,sum 36190.865895999996 pbs_debug:11,fieldInfo {{Memory {6.97 GB}} {Date { 6:14:20 (Sep22)}} {{Thread Count} 16} {{System Load} 4.72}} pbs_debug:6,sum 32434.559306000003 pbs_debug:14,cpuload 5.77 pbs_debug:9,status {} pbs_debug:0,date { 4:54:40 (Sep22)} pbs_debug:10,mem {6.94 GB} pbs_debug:2,mem {7.24 GB} pbs_debug:9,thread 7479.479809999994 pbs_debug:12,multiInfo {{{Total Time} {{clock 02:07:09} {lthread 02:08:22}}} {{Stage Time} {{clock 00:00:04} {lthread 00:00:04}}} {{% Time} {{clock { 0.1}} {lthread 0.07201643943748634<PREC(5.1)>}}}} pbs_debug:5,tcount 16 pbs_debug:8,parent 5246.0 pbs_debug:7,status {} pbs_debug:17,tcount 16 pbs_debug:15,pmem {19.26 GB} pbs_debug:5,fieldInfo {{Memory {7.28 GB}} {Date { 6:01:30 (Sep22)}} {{Thread Count} 16} {{System Load} 4.46}} pbs_debug:7,thread 7228.839250000001 pbs_debug:3,tcount 16 pbs_debug:6,parent 5142.0 pbs_debug:12,pmem {19.26 GB} pbs_debug:11,all 25845.0 pbs_debug:3,all 15136.0 pbs_debug:6,multiInfo {{{Total Time} {{clock 01:58:52} {lthread 02:00:03}}} {{Stage Time} {{clock 00:04:37} {lthread 00:04:38}}} {{% Time} {{clock { 5.2}} {lthread 5.020924961612134<PREC(5.1)>}}}} pbs_debug:7,pmem {19.26 GB} pbs_debug:16,wall 8189 pbs_debug:11,sum 33543.483972999995 pbs_debug:0,cpuload 4.33 pbs_debug:3,sum 20371.246812999998 pbs_debug:5,status {} pbs_debug:15,tcount 16 pbs_debug:4,pmem {19.26 GB} pbs_debug:13,fieldInfo {{Memory {6.97 GB}} {Date { 6:15:32 (Sep22)}} {{Thread Count} 16} {{System Load} 5.02}} pbs_debug:13,wall 7697 pbs_debug:4,cpuload 4.22 pbs_debug:5,thread 6924.682705000001 pbs_debug:1,tcount 16 pbs_debug:4,parent 4418.0 pbs_debug:1,pmem {19.26 GB} pbs_debug:8,wall 7213 pbs_debug:8,cpuload 4.30 pbs_debug:17,name FINAL_CLEAN_UP pbs_debug:10,wall 7319 pbs_debug:17,status {} pbs_debug:14,multiInfo {{{Total Time} {{clock 02:15:47} {lthread 02:18:18}}} {{Stage Time} {{clock 00:07:30} {lthread 00:08:15}}} {{% Time} {{clock { 8.4}} {lthread 8.93000925157392<PREC(5.1)>}}}} pbs_debug:15,mem {6.97 GB} pbs_debug:5,wall 6855 pbs_debug:14,name 1ST_ST pbs_debug:7,mem {7.03 GB} pbs_debug:3,status {} pbs_debug:17,thread 8359.425567999997 pbs_debug:16,parent 6417.0 pbs_debug:13,tcount 16 pbs_debug:2,wall 4994 pbs_debug:9,name {PBS_TechMap-Postmap Cleanup} pbs_debug:11,name PBS_Incr_Opt-Start pbs_debug:3,thread 5235.246813 pbs_debug:2,parent 4175.0 pbs_debug:6,name {PBS_TechMap-Datapath Postmap Operations} pbs_debug:7,fieldInfo {{Memory {7.03 GB}} {Date { 6:06:27 (Sep22)}} {{Thread Count} 16} {{System Load} 4.24}} pbs_debug:0,all 2839.0 pbs_debug:15,status {} pbs_debug:3,name PBS_TechMap-Start pbs_debug:0,sum 5644.138198000001 pbs_debug:1,status {} pbs_debug:15,thread 8348.576931999998 pbs_debug:14,parent 6344.0 pbs_debug:11,tcount 16 pbs_debug:8,multiInfo {{{Total Time} {{clock 02:00:13} {lthread 02:01:27}}} {{Stage Time} {{clock 00:01:01} {lthread 00:00:59}}} {{% Time} {{clock { 1.1}} {lthread 1.0622424817029235<PREC(5.1)>}}}} pbs_debug:16,all 27965.0 pbs_debug:0,fieldInfo {{Memory {5.53 GB}} {Date { 4:54:40 (Sep22)}} {{Thread Count} 16} {{System Load} 4.33}} pbs_debug:1,thread 4993.246813 pbs_debug:0,name PBS_Generic-Start pbs_debug:8,all 25335.0 pbs_debug:11,cpuload 4.72 pbs_debug:0,multiInfoDetail {{{Total Time} {{clock 00:47:25} {lthread 00:46:45} {threads 00:47:19} {non-thread 00:47:19}}} {{Stage Time} {{clock 00:00:00} {lthread 00:00:00} {threads 00:00:00} {non-thread 00:00:00}}} {{% Time} {{clock { 0.0}} {lthread 0.0<PREC(5.1)>} {threads 0.0<PREC(5.1)>} {non-thread 0.0<PREC(5.1)>}}} {{ST Metrics} {{Efficiency <PERCENT>} {Utilization <PERCENT>} {{Lazy Time} <PERCENT>}}}} pbs_debug:0,parent 2839.0 pbs_debug:16,sum 36313.576931999996 pbs_debug:2,multiInfoDetail {{{Total Time} {{clock 01:23:14} {lthread 01:23:38} {threads 04:08:39} {non-thread 01:09:35}}} {{Stage Time} {{clock 00:00:25} {lthread 00:00:25} {threads 00:00:25} {non-thread 00:00:25}}} {{% Time} {{clock { 0.5}} {lthread 0.4501027464842896<PREC(5.1)>} {threads 0.09945498667303179<PREC(5.1)>} {non-thread 0.6965728615213151<PREC(5.1)>}}} {{ST Metrics} {{Efficiency <PERCENT>} {Utilization <PERCENT>} {{Lazy Time} 0.0<PERCENT>}}}} pbs_debug:16,date { 6:23:44 (Sep22)} pbs_debug:8,sum 32622.83925 pbs_debug:15,fieldInfo {{Memory {6.97 GB}} {Date { 6:23:44 (Sep22)}} {{Thread Count} 16} {{System Load} 6.01}} pbs_debug:15,cpuload 6.01 pbs_debug:4,multiInfoDetail {{{Total Time} {{clock 01:28:32} {lthread 01:27:41} {threads 04:12:42} {non-thread 01:13:38}}} {{Stage Time} {{clock 00:00:26} {lthread 00:00:26} {threads 00:00:26} {non-thread 00:00:26}}} {{% Time} {{clock { 0.5}} {lthread 0.46810685634366117<PREC(5.1)>} {threads 0.10343318613995306<PREC(5.1)>} {non-thread 0.7244357759821677<PREC(5.1)>}}} {{ST Metrics} {{Efficiency <PERCENT>} {Utilization <PERCENT>} {{Lazy Time} 0.0<PERCENT>}}}} pbs_debug:13,status {} pbs_debug:1,multiInfo {{{Total Time} {{clock 01:22:49} {lthread 01:23:13}}} {{Stage Time} {{clock 00:35:24} {lthread 00:36:28}}} {{% Time} {{clock { 39.7}} {lthread 39.394947888697395<PREC(5.1)>}}}} pbs_debug:6,multiInfoDetail {{{Total Time} {{clock 01:58:52} {lthread 02:00:03} {threads 07:00:31} {non-thread 01:25:42}}} {{Stage Time} {{clock 00:04:37} {lthread 00:04:38} {threads 00:05:01} {non-thread 00:05:01}}} {{% Time} {{clock { 5.2}} {lthread 5.020924961612134<PREC(5.1)>} {threads 1.1974380395433026<PREC(5.1)>} {non-thread 8.386737252716634<PREC(5.1)>}}} {{ST Metrics} {{Efficiency -0.0<PERCENT>} {Utilization -0.07933042399638279<PERCENT>} {{Lazy Time} -0.006774732851985377<PERCENT>}}}} pbs_debug:13,date { 6:15:32 (Sep22)} pbs_debug:12,mem {6.97 GB} pbs_debug:8,multiInfoDetail {{{Total Time} {{clock 02:00:13} {lthread 02:01:27} {threads 07:02:15} {non-thread 01:27:26}}} {{Stage Time} {{clock 00:01:01} {lthread 00:00:59} {threads 00:00:59} {non-thread 00:00:59}}} {{% Time} {{clock { 1.1}} {lthread 1.0622424817029235<PREC(5.1)>} {threads 0.23471376854835502<PREC(5.1)>} {non-thread 1.6439119531903037<PREC(5.1)>}}} {{ST Metrics} {{Efficiency <PERCENT>} {Utilization <PERCENT>} {{Lazy Time} 0.032786885245901676<PERCENT>}}}} pbs_debug:4,mem {7.25 GB} pbs_debug:13,thread 7802.867519999994 pbs_debug:12,parent 5760.0 pbs_debug:16,multiInfo {{{Total Time} {{clock 02:16:29} {lthread 02:19:08}}} {{Stage Time} {{clock 00:00:00} {lthread 00:00:00}}} {{% Time} {{clock { 0.0}} {lthread 0.0<PREC(5.1)>}}}} pbs_debug:8,date { 6:07:28 (Sep22)} pbs_debug:10,date { 6:09:14 (Sep22)} pbs_debug:5,date { 6:01:30 (Sep22)} pbs_debug:11,status {} pbs_debug:2,date { 5:30:29 (Sep22)} pbs_debug:9,fieldInfo {{Memory {6.94 GB}} {Date { 6:09:12 (Sep22)}} {{Thread Count} 16} {{System Load} 5.09}} pbs_debug:11,thread 7698.483972999995 pbs_debug:10,parent 5484.0 pbs_debug:13,all 25981.0 pbs_debug:5,all 24930.0 pbs_debug:13,sum 33783.86751999999 pbs_debug:1,cpuload 4.21 pbs_debug:2,fieldInfo {{Memory {7.24 GB}} {Date { 5:30:29 (Sep22)}} {{Thread Count} 16} {{System Load} 4.35}} pbs_debug:5,sum 31854.682705 pbs_debug:10,multiInfoDetail {{{Total Time} {{clock 02:01:59} {lthread 02:04:41} {threads 07:06:13} {non-thread 01:31:24}}} {{Stage Time} {{clock 00:00:02} {lthread 00:00:02} {threads 00:00:02} {non-thread 00:00:02}}} {{% Time} {{clock { 0.0}} {lthread 0.03600821971874317<PREC(5.1)>} {threads 0.007956398933842543<PREC(5.1)>} {non-thread 0.05572582892170521<PREC(5.1)>}}} {{ST Metrics} {{Efficiency <PERCENT>} {Utilization <PERCENT>} {{Lazy Time} 0.0<PERCENT>}}}} pbs_debug:12,multiInfoDetail {{{Total Time} {{clock 02:07:09} {lthread 02:08:22} {threads 07:10:49} {non-thread 01:36:00}}} {{Stage Time} {{clock 00:00:04} {lthread 00:00:04} {threads 00:00:04} {non-thread 00:00:04}}} {{% Time} {{clock { 0.1}} {lthread 0.07201643943748634<PREC(5.1)>} {threads 0.015912797867685086<PREC(5.1)>} {non-thread 0.11145165784341042<PREC(5.1)>}}} {{ST Metrics} {{Efficiency <PERCENT>} {Utilization <PERCENT>} {{Lazy Time} 0.0<PERCENT>}}}} pbs_debug:5,cpuload 4.46 pbs_debug:17,pmem {19.26 GB} pbs_debug:14,multiInfoDetail {{{Total Time} {{clock 02:15:47} {lthread 02:18:18} {threads 07:44:52} {non-thread 01:45:44}}} {{Stage Time} {{clock 00:07:30} {lthread 00:08:15} {threads 00:31:51} {non-thread 00:07:32}}} {{% Time} {{clock { 8.4}} {lthread 8.93000925157392<PREC(5.1)>} {threads 7.60233918128655<PREC(5.1)>} {non-thread 12.594037336305378<PREC(5.1)>}}} {{ST Metrics} {{Efficiency 2.072519676635273<PERCENT>} {Utilization 0.0887066936686931<PERCENT>} {{Lazy Time} -0.10221861333333648<PERCENT>}}}} pbs_debug:17,fieldInfo {{Memory {6.97 GB}} {Date { 6:23:55 (Sep22)}} {{Thread Count} 16} {{System Load} 5.85}} pbs_debug:1,mem {8.00 GB} pbs_debug:16,multiInfoDetail {{{Total Time} {{clock 02:16:29} {lthread 02:19:08} {threads 07:46:05} {non-thread 01:46:57}}} {{Stage Time} {{clock 00:00:00} {lthread 00:00:00} {threads 00:00:00} {non-thread 00:00:00}}} {{% Time} {{clock { 0.0}} {lthread 0.0<PREC(5.1)>} {threads 0.0<PREC(5.1)>} {non-thread 0.0<PREC(5.1)>}}} {{ST Metrics} {{Efficiency <PERCENT>} {Utilization <PERCENT>} {{Lazy Time} <PERCENT>}}}} pbs_debug:9,cpuload 5.09 pbs_debug:3,multiInfo {{{Total Time} {{clock 01:28:06} {lthread 01:27:15}}} {{Stage Time} {{clock 00:04:52} {lthread 00:03:37}}} {{% Time} {{clock { 5.5}} {lthread 3.9068918394836336<PREC(5.1)>}}}} pbs_debug:14,pmem {19.26 GB} pbs_debug:17,mem {6.97 GB} pbs_debug:9,mem {6.94 GB} pbs_debug:9,pmem {19.26 GB} pbs_debug:11,pmem {19.26 GB} pbs_debug:10,fieldInfo {{Memory {6.94 GB}} {Date { 6:09:14 (Sep22)}} {{Thread Count} 16} {{System Load} 5.00}} pbs_debug:6,pmem {19.26 GB} pbs_debug:8,tcount 16 pbs_debug:15,wall 8189 pbs_debug:11,multiInfo {{{Total Time} {{clock 02:07:05} {lthread 02:08:18}}} {{Stage Time} {{clock 00:05:06} {lthread 00:03:37}}} {{% Time} {{clock { 5.7}} {lthread 3.9069667905929877<PREC(5.1)>}}}} pbs_debug:10,all 25573.0 pbs_debug:3,pmem {19.26 GB} pbs_debug:12,wall 7629 pbs_debug:2,all 14919.0 pbs_debug:10,sum 33054.47981 pbs_debug:0,pmem {11.98 GB} pbs_debug:2,sum 19937.246812999998 pbs_debug:7,wall 7152 pbs_debug:16,name CRB_ST pbs_debug:12,cpuload 4.66 pbs_debug:6,tcount 16 pbs_debug:9,parent 5482.0 pbs_debug:4,wall 5312 pbs_debug:4,fieldInfo {{Memory {7.25 GB}} {Date { 5:35:47 (Sep22)}} {{Thread Count} 16} {{System Load} 4.22}} pbs_debug:13,name INIT_CLEAN_UP pbs_debug:16,cpuload 6.01 pbs_debug:1,wall 4969 pbs_debug:8,name {PBS_TechMap-Postmap Clock Gating} pbs_debug:10,name PBS_Techmap-Post_MBCI pbs_debug:14,mem {6.95 GB} pbs_debug:5,multiInfo {{{Total Time} {{clock 01:54:15} {lthread 01:55:24}}} {{Stage Time} {{clock 00:25:43} {lthread 00:27:43}}} {{% Time} {{clock { 28.8}} {lthread 29.94868254358979<PREC(5.1)>}}}} pbs_debug:8,status {} pbs_debug:6,mem {7.03 GB} pbs_debug:5,name {PBS_Techmap-Global Mapping} pbs_debug:8,thread 7287.839250000001 pbs_debug:4,tcount 16 pbs_debug:7,parent 5187.0 pbs_debug:12,fieldInfo {{Memory {6.97 GB}} {Date { 6:14:24 (Sep22)}} {{Thread Count} 16} {{System Load} 4.66}} pbs_debug:2,name {PBS_Generic-Postgen HBO Optimizations} pbs_debug:6,status {} pbs_debug:13,multiInfo {{{Total Time} {{clock 02:08:17} {lthread 02:10:02}}} {{Stage Time} {{clock 00:01:08} {lthread 00:01:40}}} {{% Time} {{clock { 1.3}} {lthread 1.8073164082613808<PREC(5.1)>}}}} pbs_debug:16,tcount 16 pbs_debug:15,date { 6:23:44 (Sep22)} pbs_debug:6,thread 7203.559306000001 pbs_debug:15,all 27965.0 pbs_debug:2,tcount 16 pbs_debug:5,parent 4841.0 pbs_debug:7,all 25276.0 pbs_debug:12,date { 6:14:24 (Sep22)} pbs_debug:2,cpuload 4.35 pbs_debug:15,sum 36313.576931999996 pbs_debug:7,sum 32504.83925 pbs_debug:7,date { 6:06:27 (Sep22)} pbs_debug:6,cpuload 4.22 pbs_debug:6,fieldInfo {{Memory {7.03 GB}} {Date { 6:06:07 (Sep22)}} {{Thread Count} 16} {{System Load} 4.22}} pbs_debug:4,status {} pbs_debug:11,mem {6.97 GB} pbs_debug:17,parent 6428.0 pbs_debug:14,tcount 16 pbs_debug:3,mem {7.25 GB} pbs_debug:4,date { 5:35:47 (Sep22)} pbs_debug:4,thread 5261.246813 pbs_debug:0,tcount 16 pbs_debug:3,parent 4392.0 pbs_debug:7,multiInfo {{{Total Time} {{clock 01:59:12} {lthread 02:00:28}}} {{Stage Time} {{clock 00:00:20} {lthread 00:00:25}}} {{% Time} {{clock { 0.4}} {lthread 0.45514288901475947<PREC(5.1)>}}}} pbs_debug:1,date { 5:30:04 (Sep22)} pbs_debug:16,status {} pbs_debug:14,fieldInfo {{Memory {6.95 GB}} {Date { 6:23:03 (Sep22)}} {{Thread Count} 16} {{System Load} 5.77}} pbs_debug:2,status {} pbs_debug:16,thread 8348.576931999998 pbs_debug:0,multiInfo {{{Total Time} {{clock 00:47:25} {lthread 00:46:45}}} {{Stage Time} {{clock 00:00:00} {lthread 00:00:00}}} {{% Time} {{clock { 0.0}} {lthread 0.0<PREC(5.1)>}}}} pbs_debug:15,parent 6417.0 pbs_debug:12,tcount 16 pbs_debug:2,thread 5018.246813 pbs_debug:1,parent 4150.0 pbs_debug:12,all 25849.0 pbs_debug:15,multiInfo {{{Total Time} {{clock 02:16:29} {lthread 02:19:08}}} {{Stage Time} {{clock 00:00:42} {lthread 00:00:49}}} {{% Time} {{clock { 0.8}} {lthread 0.8950029533672194<PREC(5.1)>}}}} pbs_debug:4,all 15162.0 pbs_debug:16,pmem {19.26 GB} pbs_debug:12,sum 33551.483972999995 pbs_debug:14,status {} pbs_debug:4,sum 20423.246812999998 pbs_debug:13,pmem {19.26 GB} pbs_debug:1,multiInfoDetail {{{Total Time} {{clock 01:22:49} {lthread 01:23:13} {threads 04:08:14} {non-thread 01:09:10}}} {{Stage Time} {{clock 00:35:24} {lthread 00:36:28} {threads 03:20:55} {non-thread 00:21:51}}} {{% Time} {{clock { 39.7}} {lthread 39.394947888697395<PREC(5.1)>} {threads 47.957194573735926<PREC(5.1)>} {non-thread 36.528280858177766<PREC(5.1)>}}} {{ST Metrics} {{Efficiency 0.7655836329916794<PERCENT>} {Utilization 0.40085241152437023<PERCENT>} {{Lazy Time} -0.03018296374764584<PERCENT>}}}} pbs_debug:13,cpuload 5.02 pbs_debug:0,status {} pbs_debug:14,thread 8298.865895999996 pbs_debug:3,multiInfoDetail {{{Total Time} {{clock 01:28:06} {lthread 01:27:15} {threads 04:12:16} {non-thread 01:13:12}}} {{Stage Time} {{clock 00:04:52} {lthread 00:03:37} {threads 00:03:37} {non-thread 00:03:37}}} {{% Time} {{clock { 5.5}} {lthread 3.9068918394836336<PREC(5.1)>} {threads 0.8632692843219159<PREC(5.1)>} {non-thread 6.046252438005015<PREC(5.1)>}}} {{ST Metrics} {{Efficiency <PERCENT>} {Utilization <PERCENT>} {{Lazy Time} 0.2568493150684932<PERCENT>}}}} pbs_debug:13,parent 5892.0 pbs_debug:10,tcount 16 pbs_debug:0,mem {5.53 GB} pbs_debug:5,multiInfoDetail {{{Total Time} {{clock 01:54:15} {lthread 01:55:24} {threads 06:55:30} {non-thread 01:20:41}}} {{Stage Time} {{clock 00:25:43} {lthread 00:27:43} {threads 02:42:48} {non-thread 00:07:03}}} {{% Time} {{clock { 28.8}} {lthread 29.94868254358979<PREC(5.1)>} {threads 38.85905239288698<PREC(5.1)>} {non-thread 11.786012816940652<PREC(5.1)>}}} {{ST Metrics} {{Efficiency 0.4708526283114028<PERCENT>} {Utilization 0.7457070620909749<PERCENT>} {{Lazy Time} -0.0780530732339606<PERCENT>}}}} pbs_debug:8,pmem {19.26 GB} pbs_debug:17,cpuload 5.85 pbs_debug:17,wall 8200 pbs_debug:10,pmem {19.26 GB} pbs_debug:0,thread 2805.138198 pbs_debug:8,fieldInfo {{Memory {6.90 GB}} {Date { 6:07:28 (Sep22)}} {{Thread Count} 16} {{System Load} 4.30}} pbs_debug:7,multiInfoDetail {{{Total Time} {{clock 01:59:12} {lthread 02:00:28} {threads 07:01:16} {non-thread 01:26:27}}} {{Stage Time} {{clock 00:00:20} {lthread 00:00:25} {threads 00:00:45} {non-thread 00:00:45}}} {{% Time} {{clock { 0.4}} {lthread 0.45514288901475947<PREC(5.1)>} {threads 0.17901897601145722<PREC(5.1)>} {non-thread 1.2538311507383673<PREC(5.1)>}}} {{ST Metrics} {{Efficiency -0.0<PERCENT>} {Utilization -0.7800672343261599<PERCENT>} {{Lazy Time} -0.2639971999999944<PERCENT>}}}} pbs_debug:9,multiInfoDetail {{{Total Time} {{clock 02:01:57} {lthread 02:04:39} {threads 07:06:11} {non-thread 01:31:22}}} {{Stage Time} {{clock 00:01:44} {lthread 00:03:11} {threads 00:03:56} {non-thread 00:03:56}}} {{% Time} {{clock { 1.9}} {lthread 3.450317695751374<PREC(5.1)>} {threads 0.9388550741934201<PREC(5.1)>} {non-thread 6.575647812761215<PREC(5.1)>}}} {{ST Metrics} {{Efficiency -0.0<PERCENT>} {Utilization -0.23147208503256334<PERCENT>} {{Lazy Time} -0.8426976923076295<PERCENT>}}}} pbs_debug:5,pmem {19.26 GB} pbs_debug:14,wall 8147 pbs_debug:16,mem {6.97 GB} pbs_debug:12,status {} pbs_debug:8,mem {6.90 GB} pbs_debug:9,multiInfo {{{Total Time} {{clock 02:01:57} {lthread 02:04:39}}} {{Stage Time} {{clock 00:01:44} {lthread 00:03:11}}} {{% Time} {{clock { 1.9}} {lthread 3.450317695751374<PREC(5.1)>}}}} pbs_debug:1,fieldInfo {{Memory {8.00 GB}} {Date { 5:30:04 (Sep22)}} {{Thread Count} 16} {{System Load} 4.21}} pbs_debug:2,pmem {19.26 GB} pbs_debug:9,wall 7317 pbs_debug:11,wall 7625 pbs_debug:12,thread 7702.483972999995 pbs_debug:11,parent 5756.0 pbs_debug:6,wall 7132 pbs_debug:16,fieldInfo {{Memory {6.97 GB}} {Date { 6:23:44 (Sep22)}} {{Thread Count} 16} {{System Load} 6.01}} pbs_debug:15,name INTRMD_CLEAN_UP pbs_debug:2,multiInfo {{{Total Time} {{clock 01:23:14} {lthread 01:23:38}}} {{Stage Time} {{clock 00:00:25} {lthread 00:00:25}}} {{% Time} {{clock { 0.5}} {lthread 0.4501027464842896<PREC(5.1)>}}}} pbs_debug:1,all 14894.0 pbs_debug:3,wall 5286 pbs_debug:12,name PBS_Incr_Opt-Uniquify_Netlist pbs_debug:10,status {} pbs_debug:1,sum 19887.246812999998 pbs_debug:17,multiInfo {{{Total Time} {{clock 02:16:40} {lthread 02:19:19}}} {{Stage Time} {{clock 00:00:11} {lthread 00:00:10}}} {{% Time} {{clock { 0.2}} {lthread 0.195320034368312<PREC(5.1)>}}}} pbs_debug:0,wall 2845 pbs_debug:7,name {PBS_TechMap-Postmap HBO Optimizations} pbs_debug:17,all 27976.0 pbs_debug:10,thread 7481.479809999994 pbs_debug:9,all 25571.0 pbs_debug:3,cpuload 4.37 pbs_debug:11,multiInfoDetail {{{Total Time} {{clock 02:07:05} {lthread 02:08:18} {threads 07:10:45} {non-thread 01:35:56}}} {{Stage Time} {{clock 00:05:06} {lthread 00:03:37} {threads 00:04:32} {non-thread 00:04:32}}} {{% Time} {{clock { 5.7}} {lthread 3.9069667905929877<PREC(5.1)>} {threads 1.0820702550025858<PREC(5.1)>} {non-thread 7.578712733351908<PREC(5.1)>}}} {{ST Metrics} {{Efficiency -0.0<PERCENT>} {Utilization -0.2534321749394244<PERCENT>} {{Lazy Time} 0.29083606862744926<PERCENT>}}}} pbs_debug:17,sum 36335.425568 pbs_debug:4,name {PBS_TechMap-Premap HBO Optimizations} pbs_debug:13,multiInfoDetail {{{Total Time} {{clock 02:08:17} {lthread 02:10:02} {threads 07:13:01} {non-thread 01:38:12}}} {{Stage Time} {{clock 00:01:08} {lthread 00:01:40} {threads 00:02:12} {non-thread 00:02:12}}} {{% Time} {{clock { 1.3}} {lthread 1.8073164082613808<PREC(5.1)>} {threads 0.5251223296336078<PREC(5.1)>} {non-thread 3.677904708832544<PREC(5.1)>}}} {{ST Metrics} {{Efficiency -0.0<PERCENT>} {Utilization -0.31495652370204374<PERCENT>} {{Lazy Time} -0.4762286323529332<PERCENT>}}}} pbs_debug:9,sum 33050.47981 pbs_debug:7,cpuload 4.24 pbs_debug:15,multiInfoDetail {{{Total Time} {{clock 02:16:29} {lthread 02:19:08} {threads 07:46:05} {non-thread 01:46:57}}} {{Stage Time} {{clock 00:00:42} {lthread 00:00:49} {threads 00:01:13} {non-thread 00:01:13}}} {{% Time} {{clock { 0.8}} {lthread 0.8950029533672194<PREC(5.1)>} {threads 0.2904085610852528<PREC(5.1)>} {non-thread 2.0339927556422404<PREC(5.1)>}}} {{ST Metrics} {{Efficiency -0.0<PERCENT>} {Utilization -0.4684867963724684<PERCENT>} {{Lazy Time} -0.183596095238153<PERCENT>}}}} pbs_debug:10,multiInfo {{{Total Time} {{clock 02:01:59} {lthread 02:04:41}}} {{Stage Time} {{clock 00:00:02} {lthread 00:00:02}}} {{% Time} {{clock { 0.0}} {lthread 0.03600821971874317<PREC(5.1)>}}}} pbs_debug:17,multiInfoDetail {{{Total Time} {{clock 02:16:40} {lthread 02:19:19} {threads 07:46:16} {non-thread 01:47:08}}} {{Stage Time} {{clock 00:00:11} {lthread 00:00:10} {threads 00:00:11} {non-thread 00:00:11}}} {{% Time} {{clock { 0.2}} {lthread 0.195320034368312<PREC(5.1)>} {threads 0.04376019413613399<PREC(5.1)>} {non-thread 0.30649205906937865<PREC(5.1)>}}} {{ST Metrics} {{Efficiency -0.0<PERCENT>} {Utilization -0.013952353088555247<PERCENT>} {{Lazy Time} 0.013760363636472261<PERCENT>}}}} pbs_debug:1,name PBS_Generic_Opt-Post pbs_debug:13,mem {6.97 GB} pbs_debug:5,mem {7.28 GB} pbs_debug:17,date { 6:23:55 (Sep22)} pbs_debug:9,tcount 16 pbs_debug:14,date { 6:23:03 (Sep22)} pbs_debug:3,fieldInfo {{Memory {7.25 GB}} {Date { 5:35:21 (Sep22)}} {{Thread Count} 16} {{System Load} 4.37}}}
array set allMetrics {default:1,mem {4.32 GB} default:3,wall 7368 default:1,status {} default:0,wall 0 default:1,thread 2607.0 default:0,parent 5.0 default:4,name OPT default:1,name Elaboration default:2,all 14963.0 default:2,sum 20025.246812999998 default:1,multiInfoDetail {{{Total Time} {{clock 00:44:24} {lthread 00:43:27} {threads 00:43:27} {non-thread 00:43:27}}} {{Stage Time} {{clock 00:44:24} {lthread 00:43:22} {threads 00:43:22} {non-thread 00:43:22}}} {{% Time} {{clock { 32.3}} {lthread 30.9746212133809<PREC(5.1)>} {threads 9.287218474497626<PREC(5.1)>} {non-thread 40.222600092750035<PREC(5.1)>}}} {{ST Metrics} {{Efficiency <PERCENT>} {Utilization <PERCENT>} {{Lazy Time} 0.02327327327327322<PERCENT>}}}} default:3,multiInfoDetail {{{Total Time} {{clock 02:02:48} {lthread 02:05:30} {threads 07:07:02} {non-thread 01:32:13}}} {{Stage Time} {{clock 00:38:49} {lthread 00:41:08} {threads 02:57:39} {non-thread 00:21:54}}} {{% Time} {{clock { 28.2}} {lthread 29.382237566657473<PREC(5.1)>} {threads 38.044758539458186<PREC(5.1)>} {non-thread 20.312258463441026<PREC(5.1)>}}} {{ST Metrics} {{Efficiency 0.5060178503976721<PERCENT>} {Utilization 0.4676353482037162<PERCENT>} {{Lazy Time} -0.05978230871618484<PERCENT>}}}} default:3,date { 6:10:03 (Sep22)} default:0,date { 4:07:15 (Sep22)} default:0,multiInfo {{{Total Time} {{clock 00:00:00} {lthread 00:00:05}}} {{Stage Time} {{clock 00:00:00} {lthread 00:00:00}}} {{% Time} {{clock { 0.0}} {lthread 0.0<PREC(5.1)>}}}} default:1,cpuload 4.15 default:3,mem {6.90 GB} default:1,fieldInfo {{Memory {4.32 GB}} {Date { 4:51:39 (Sep22)}} {{Thread Count} 16} {{System Load} 4.15}} default:4,pmem {19.26 GB} default:1,pmem {11.98 GB} default:2,multiInfo {{{Total Time} {{clock 01:23:59} {lthread 01:24:22}}} {{Stage Time} {{clock 00:39:35} {lthread 00:40:55}}} {{% Time} {{clock { 28.8}} {lthread 29.227647970036756<PREC(5.1)>}}}} default:4,all 28022.0 default:4,tcount 16 default:4,sum 36427.425568 default:2,wall 5039 default:0,mem {250.4 MB} default:3,name MAPPED default:2,tcount 16 default:0,name init default:3,fieldInfo {{Memory {6.90 GB}} {Date { 6:10:03 (Sep22)}} {{Thread Count} 16} {{System Load} 4.52}} default:4,status {} default:1,all 2607.0 default:4,multiInfo {{{Total Time} {{clock 02:17:26} {lthread 02:20:05}}} {{Stage Time} {{clock 00:14:38} {lthread 00:14:34}}} {{% Time} {{clock { 10.6}} {lthread 10.41549324992487<PREC(5.1)>}}}} default:4,thread 8405.425567999997 default:3,parent 5533.0 default:0,tcount 8 default:1,sum 5214.0 default:2,cpuload 4.36 default:2,status {} default:2,date { 5:31:14 (Sep22)} default:2,thread 5062.246813 default:1,parent 2607.0 default:0,status {} default:0,thread 5.0 default:0,multiInfoDetail {{{Total Time} {{clock 00:00:00} {lthread 00:00:05} {threads 00:00:05} {non-thread 00:00:05}}} {{Stage Time} {{clock 00:00:00} {lthread 00:00:00} {threads 00:00:00} {non-thread 00:00:00}}} {{% Time} {{clock { 0.0}} {lthread 0.0<PREC(5.1)>} {threads 0.0<PREC(5.1)>} {non-thread 0.0<PREC(5.1)>}}} {{ST Metrics} {{Efficiency <PERCENT>} {Utilization <PERCENT>} {{Lazy Time} <PERCENT>}}}} default:2,multiInfoDetail {{{Total Time} {{clock 01:23:59} {lthread 01:24:22} {threads 04:09:23} {non-thread 01:10:19}}} {{Stage Time} {{clock 00:39:35} {lthread 00:40:55} {threads 03:25:56} {non-thread 00:26:52}}} {{% Time} {{clock { 28.8}} {lthread 29.227647970036756<PREC(5.1)>} {threads 44.101795338544456<PREC(5.1)>} {non-thread 24.91884371618488<PREC(5.1)>}}} {{ST Metrics} {{Efficiency 0.7963267570630003<PERCENT>} {Utilization 0.34344686185323225<PERCENT>} {{Lazy Time} -0.033788131789473486<PERCENT>}}}} default:4,multiInfoDetail {{{Total Time} {{clock 02:17:26} {lthread 02:20:05} {threads 07:47:02} {non-thread 01:47:54}}} {{Stage Time} {{clock 00:14:38} {lthread 00:14:34} {threads 00:40:00} {non-thread 00:15:41}}} {{% Time} {{clock { 10.6}} {lthread 10.41549324992487<PREC(5.1)>} {threads 8.566227647499732<PREC(5.1)>} {non-thread 14.546297727624053<PREC(5.1)>}}} {{ST Metrics} {{Efficiency -1.3804942307869272<PERCENT>} {Utilization -0.07549524230049154<PERCENT>} {{Lazy Time} 0.003478635535304586<PERCENT>}}}} default:2,mem {7.19 GB} default:3,pmem {19.26 GB} default:0,pmem {250.4 MB} default:4,wall 8246 default:1,wall 2664 default:3,all 25622.0 default:3,sum 33152.47981 default:0,fieldInfo {{Memory {250.4 MB}} {Date { 4:07:15 (Sep22)}} {{Thread Count} 8} {{System Load} 3.20}} default:3,cpuload 4.52 default:2,name GENERIC default:1,multiInfo {{{Total Time} {{clock 00:44:24} {lthread 00:43:27}}} {{Stage Time} {{clock 00:44:24} {lthread 00:43:22}}} {{% Time} {{clock { 32.3}} {lthread 30.9746212133809<PREC(5.1)>}}}} default:0,all 5.0 default:4,date { 6:24:41 (Sep22)} default:0,sum 10.0 default:1,date { 4:51:39 (Sep22)} default:2,fieldInfo {{Memory {7.19 GB}} {Date { 5:31:14 (Sep22)}} {{Thread Count} 16} {{System Load} 4.36}} default:3,tcount 16 default:3,multiInfo {{{Total Time} {{clock 02:02:48} {lthread 02:05:30}}} {{Stage Time} {{clock 00:38:49} {lthread 00:41:08}}} {{% Time} {{clock { 28.2}} {lthread 29.382237566657473<PREC(5.1)>}}}} default:4,mem {6.78 GB} default:4,parent 6474.0 default:1,tcount 16 default:3,status {} default:0,cpuload 3.20 default:2,pmem {19.26 GB} default:3,thread 7530.479809999994 default:4,fieldInfo {{Memory {6.78 GB}} {Date { 6:24:41 (Sep22)}} {{Thread Count} 16} {{System Load} 5.08}} default:4,cpuload 5.08 default:2,parent 4219.0}
Flows/NanGate45/bp_quad/scripts/cadence/design_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
set DESIGN bsg_chip
set sdc ./sdc/bsg_chip.sdc
set rtldir ./rtl
#
# DEF file for floorplan initialization
#
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set floorplan_def ./def/bsg_chip_fp_placed_macros.def
} else {
set floorplan_def ./def/bsg_chip_fp.def
}
#
# Effort level during optimization in syn_generic -physical (or called generic) stage
# possible values are : high, medium or low
set GEN_EFF medium
# Effort level during optimization in syn_map -physical (or called mapping) stage
# possible values are : high, medium or low
set MAP_EFF high
#
set SITE "FreePDK45_38x28_10R_NP_162NW_34O"
set HALO_WIDTH 5
set TOP_ROUTING_LAYER 10
Flows/NanGate45/bp_quad/scripts/cadence/lib_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
# lib and lef, RC setup
set platformdir "../../../../../Enablements/NanGate45/"
set libdir "${platformdir}/lib"
set lefdir "${platformdir}/lef"
set qrcdir "${platformdir}/qrc"
set_db init_lib_search_path { \
${libdir} \
${lefdir} \
}
set libworst "
${libdir}/NangateOpenCellLibrary_typical.lib \
${libdir}/fakeram45_32x32.lib \
${libdir}/fakeram45_128x116.lib \
${libdir}/fakeram45_256x48.lib \
${libdir}/fakeram45_512x64.lib \
${libdir}/fakeram45_64x62.lib \
${libdir}/fakeram45_64x124.lib \
"
set libbest "
${libdir}/NangateOpenCellLibrary_typical.lib \
${libdir}/fakeram45_32x32.lib \
${libdir}/fakeram45_128x116.lib \
${libdir}/fakeram45_256x48.lib \
${libdir}/fakeram45_512x64.lib \
${libdir}/fakeram45_64x62.lib \
${libdir}/fakeram45_64x124.lib \
"
set lefs "
${lefdir}/NangateOpenCellLibrary.tech.lef \
${lefdir}/NangateOpenCellLibrary.macro.mod.lef \
${lefdir}/fakeram45_32x32.lef \
${lefdir}/fakeram45_128x116.lef \
${lefdir}/fakeram45_256x48.lef \
${lefdir}/fakeram45_512x64.lef \
${lefdir}/fakeram45_64x62.lef \
${lefdir}/fakeram45_64x124.lef \
"
set qrc_max "${qrcdir}/NG45.tch"
set qrc_min "${qrcdir}/NG45.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 45
Flows/NanGate45/bp_quad/scripts/cadence/mmmc_iSpatial_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
#create_opcond -name op_cond_wc -process 1.0 -voltage 0.72 -temperature 125
#create_opcond -name op_cond_bc -process 1.0 -voltage 0.88 -temperature -40
create_timing_condition -name timing_wc -library_sets { WC_LIB }
create_timing_condition -name timing_bc -library_sets { BC_LIB }
create_rc_corner -name Cmax -qrc_tech $qrc_max
create_rc_corner -name Cmin -qrc_tech $qrc_min
create_delay_corner -name WC -early_timing_condition { timing_wc } \
-late_timing_condition { timing_wc } \
-early_rc_corner Cmax \
-late_rc_corner Cmax
create_delay_corner -name BC -early_timing_condition { timing_bc } \
-late_timing_condition { timing_bc } \
-early_rc_corner Cmin \
-late_rc_corner Cmin
create_constraint_mode -name CON -sdc_file $sdc
create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
set_analysis_view -setup WC_VIEW -hold BC_VIEW
Flows/NanGate45/bp_quad/scripts/cadence/mmmc_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
create_rc_corner -name Cmax
create_rc_corner -name Cmin
create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
create_delay_corner -name BC -library_set BC_LIB -rc_corner Cmin
create_constraint_mode -name CON -sdc_file $sdc
create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
Flows/NanGate45/bp_quad/scripts/cadence/rtl/bsg_chip_block.sv2v.v 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/NanGate45/bp_quad/scripts/cadence/rtl/fakeram45_32x32_dp.v 0 → 100644
module fakeram_32x32_dp
(
QA,
CLKA,
CENA,
AA,
CLKB,
CENB,
AB,
DB,
STOV,
EMAA,
EMASA,
EMAB,
RET1N
);
input CLKA;
input CLKB;
input CENA;
input [4:0] AA;
output [31:0] QA;
input CENB;
input [4:0] AB;
input [31:0] DB;
input STOV;
input [2:0] EMAA;
input EMASA;
input [2:0] EMAB;
input RET1N;
assign STOV = 1'b0;
assign EMASA = 1'b0;
assign EMAA = 3'b010; // Extra margin adjustment A: Default for 0.8V
assign EMAB = 3'b010; // Extra margin adjustment B: Default for 0.8V
assign RET1N = 1'b1;
wire [31:0] QB;
wire [31:0] QA1;
fakeram45_32x32 rmod_a
(
.rd_out(QA1),
.addr_in(AA),
.we_in(~CENA),
.wd_in(DB), //dummy
.w_mask_in(DB), //dummy
.clk(CLKA),
.ce_in(CENA)
);
fakeram45_32x32 rmod_b
(
.rd_out(QB), //dummy
.addr_in(AB),
.we_in(CENB),
.wd_in(DB),
.w_mask_in(DB),
.clk(CLKB),
.ce_in(CENB)
);
genvar k;
generate
for (k = 0; k < 32; k=k+1) begin
assign QA[k] = (~CENB & QB[k]) | (CENB & QA1[k]);
end
endgenerate
endmodule
Flows/NanGate45/bp_quad/scripts/cadence/rtl_list.tcl 0 → 100644
set rtl_all {
./rtl/bsg_chip_block.sv2v.v
./rtl/fakeram45_32x32_dp.v
}
Flows/NanGate45/bp_quad/scripts/cadence/run.sh 0 → 100755
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
#!/bin/tcsh
module unload genus
module load genus/21.1
module unload innovus
module load innovus/21.1
#
# To run the Physical Synthesis (iSpatial) flow - flow2
export PHY_SYNTH=0
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
#innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
#../../../../util/run_CodeFlow.sh
Flows/NanGate45/bp_quad/scripts/cadence/run_genus.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
# Target library
set link_library $list_lib
set target_library $list_lib
# set path
set_db hdl_flatten_complex_port true
set_db hdl_record_naming_style %s_%s
set_db auto_ungroup none
set_db library $list_lib
#################################################
# Load Design and Initialize
#################################################
source rtl_list.tcl
foreach rtl_file $rtl_all {
read_hdl -sv $rtl_file
}
elaborate $DESIGN
time_info Elaboration
read_sdc $sdc
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
# keep hierarchy during synthesis
set_db auto_ungroup none
syn_generic
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
syn_map
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
syn_opt
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
#write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exit
Flows/NanGate45/bp_quad/scripts/cadence/run_genus_hybrid.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_mmmc mmmc_iSpatial_setup.tcl
}
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
read_physical -lefs $lefs
}
# Target library
set link_library $list_lib
set target_library $list_lib
# set pathi
set_db hdl_flatten_complex_port true
set_db hdl_record_naming_style %s_%s
set_db auto_ungroup none
set_db hdl_error_on_blackbox true
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
set_db library $list_lib
}
#################################################
# Load Design and Initialize
#################################################
set_db init_hdl_search_path $rtldir
source rtl_list.tcl
foreach rtl_file $rtl_all {
read_hdl -sv $rtl_file
}
elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
#read_sdc $sdc
source $sdc
}
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
###############################################
# Read DEF
###############################################
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_def $floorplan_def
check_floorplan -detailed
}
# keep hierarchy during synthesis
set_db auto_ungroup none
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
}
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_map -physical
} else {
syn_map
}
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_opt -spatial
} else {
syn_opt
}
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
}
exit
Flows/NanGate45/bp_quad/scripts/cadence/run_genus_iSpatial.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
read_mmmc mmmc_iSpatial_setup.tcl
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
read_physical -lefs $lefs
# Target library
set link_library $list_lib
set target_library $list_lib
# set path
set_db hdl_flatten_complex_port true
set_db hdl_record_naming_style %s_%s
set_db auto_ungroup none
#set_db library $list_lib
#################################################
# Load Design and Initialize
#################################################
source rtl_list.tcl
foreach rtl_file $rtl_all {
read_hdl -sv $rtl_file
}
elaborate $DESIGN
time_info Elaboration
#read_sdc $sdc
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
###############################################
# Read DEF
###############################################
read_def $floorplan_def
check_floorplan -detailed
# keep hierarchy during synthesis
set_db auto_ungroup none
syn_generic -physical
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
syn_map -physical
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
syn_opt -spatial
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
#write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
#write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exit
Flows/NanGate45/bp_quad/scripts/cadence/run_invs.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
set rptDir summaryReport/
set encDir enc/
if {![file exists $rptDir/]} {
exec mkdir $rptDir/
}
if {![file exists $encDir/]} {
exec mkdir $encDir/
}
# default settings
set init_pwr_net VDD
set init_gnd_net VSS
# default settings
set init_verilog "$netlist"
set init_design_netlisttype "Verilog"
set init_design_settop 1
set init_top_cell "$DESIGN"
set init_lef_file "$lefs"
# MCMM setup
init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
globalNetConnect VSS -type pgpin -pin VSS -inst * -override
globalNetConnect VDD -type tiehi -inst * -override
globalNetConnect VSS -type tielo -inst * -override
setOptMode -powerEffort low -leakageToDynamicRatio 0.5
setGenerateViaMode -auto true
generateVias
# basic path groups
createBasicPathGroups -expanded
## Generate the floorplan ##
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl
gen_pb_netlist
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
}
### Write out the def files ###
source ../../../../util/write_required_def.tcl
### Add power plan ###
source ../../../../../Enablements/NanGate45/util/pdn_config.tcl
source ../../../../util/pdn_flow.tcl
saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
create_ccopt_clock_tree_spec
ccopt_design
set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks]
set_clock_propagation propagated
saveDesign $encDir/${DESIGN}_cts.enc
set rpt_post_cts [extract_report postCTS]
echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeUseAutoVia true
##Recommended by lib owners
# Prevent router modifying M1 pins shapes
setNanoRouteMode -routeWithViaInPin "1:1"
setNanoRouteMode -routeWithViaOnlyForStandardCellPin "1:1"
## limit VIAs to ongrid only for VIA1 (S1)
setNanoRouteMode -drouteOnGridOnly "via 1:1"
setNanoRouteMode -drouteAutoStop false
setNanoRouteMode -drouteExpAdvancedMarFix true
setNanoRouteMode -routeExpAdvancedTechnology true
#SM suggestion for solving long extraction runtime during GR
setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
exit
Flows/NanGate45/bp_quad/scripts/cadence/sdc/bsg_chip.sdc 0 → 100644
###################################################################
# Created by write_sdc on Wed Sep 29 06:31:20 2021
###################################################################
set sdc_version 2.0
set_units -time ps -resistance kOhm -capacitance fF -power mW -voltage V \
-current uA
create_clock [get_ports p_bsg_tag_clk_i] -name tag_clk -period 11200 -waveform {0 5600}
set_clock_uncertainty -hold 150 [get_clocks tag_clk]
create_clock [get_ports p_clk_A_i] -name bp_clk -period 2800 -waveform {0 1400}
set_clock_uncertainty 150 [get_clocks bp_clk]
create_clock [get_ports p_clk_B_i] -name io_master_clk -period 2800 -waveform {0 1400}
set_clock_uncertainty 150 [get_clocks io_master_clk]
create_clock [get_ports p_clk_C_i] -name router_clk -period 2800 -waveform {0 1400}
set_clock_uncertainty 150 [get_clocks router_clk]
create_clock [get_ports p_ci_clk_i] -name sdi_a_clk -period 5600 -waveform {0 2800}
set_clock_uncertainty 150 [get_clocks sdi_a_clk]
create_clock [get_ports p_ci2_tkn_i] -name sdo_a_tkn_clk -period 5600 -waveform {0 2800}
set_clock_uncertainty 150 [get_clocks sdo_a_tkn_clk]
create_clock [get_ports p_co_clk_i] -name sdi_b_clk -period 5600 -waveform {0 2800}
set_clock_uncertainty 150 [get_clocks sdi_b_clk]
create_clock [get_ports p_co2_tkn_i] -name sdo_b_tkn_clk -period 5600 -waveform {0 2800}
set_clock_uncertainty 150 [get_clocks sdo_b_tkn_clk]
#
set_multicycle_path 0 -hold -to [list [get_ports p_ci2_clk_o] [get_ports \
p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o] \
[get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports \
p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]]
set_multicycle_path 1 -setup -to [list [get_ports p_ci2_clk_o] [get_ports \
p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o] \
[get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports \
p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]]
set_multicycle_path 0 -hold -to [list [get_ports p_co2_clk_o] [get_ports \
p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o] \
[get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports \
p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]]
set_multicycle_path 1 -setup -to [list [get_ports p_co2_clk_o] [get_ports \
p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o] \
[get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports \
p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]]
set_false_path -from [get_clocks router_clk] -to [get_clocks bp_clk]
set_false_path -from [get_clocks tag_clk] -to [get_clocks bp_clk]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_clk_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_clk_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_clk_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_clk_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_clk_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_clk_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_clk_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_clk_i]
set_input_delay -clock tag_clk 3333 [get_ports p_bsg_tag_data_i]
set_input_delay -clock tag_clk 3333 [get_ports p_bsg_tag_en_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_v_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_v_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_v_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_v_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_0_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_0_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_0_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_0_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_1_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_1_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_1_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_1_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_2_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_2_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_2_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_2_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_3_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_3_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_3_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_3_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_4_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_4_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_4_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_4_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_5_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_5_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_5_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_5_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_6_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_6_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_6_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_6_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_7_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_7_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_7_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_7_i]
set_input_delay -clock sdi_a_clk -max 1582.7 [get_ports p_ci_8_i]
set_input_delay -clock sdi_a_clk -min 83.3 [get_ports p_ci_8_i]
set_input_delay -clock sdi_a_clk -clock_fall -max 1582.7 -add_delay [get_ports p_ci_8_i]
set_input_delay -clock sdi_a_clk -clock_fall -min 83.3 -add_delay [get_ports p_ci_8_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_v_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_v_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_v_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_v_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_0_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_0_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_0_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_0_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_1_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_1_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_1_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_1_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_2_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_2_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_2_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_2_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_3_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_3_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_3_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_3_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_4_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_4_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_4_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_4_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_5_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_5_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_5_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_5_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_6_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_6_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_6_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_6_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_7_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_7_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_7_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_7_i]
set_input_delay -clock sdi_b_clk -max 1582.7 [get_ports p_co_8_i]
set_input_delay -clock sdi_b_clk -min 83.3 [get_ports p_co_8_i]
set_input_delay -clock sdi_b_clk -clock_fall -max 1582.7 -add_delay [get_ports p_co_8_i]
set_input_delay -clock sdi_b_clk -clock_fall -min 83.3 -add_delay [get_ports p_co_8_i]
set_timing_derate -early -cell_delay 0.97 [get_cells \
{bp_processor/cc/y_0__x_0__tile_node/tile/core/fe/mem/icache/tag_mem/macro_bmem/db1_wb_0__bank/macro_mem}]
Flows/NanGate45/mempool_group/scripts/cadence/mmmc_setup.tcl
......@@ -4,8 +4,8 @@
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
create_rc_corner -name Cmax
create_rc_corner -name Cmin
create_rc_corner -name Cmax -qx_tech_file $qrc_max
create_rc_corner -name Cmin -qx_tech_file $qrc_min
create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
......
Flows/NanGate45/mempool_group/scripts/cadence/run_invs.tcl
......@@ -41,6 +41,8 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setAnalysisMode -reset
setAnalysisMode -analysisType onChipVariation -cppr both
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......
Flows/NanGate45/mempool_tile/constraints/mempool_tile.sdc
set sdc_version 2.0
set_units -time ns -resistance kOhm -capacitance fF -power mW -voltage V -current uA
set clock_cycle 4
set clock_cycle 6.8
set uncertainty 0.08
set io_delay 0
set maxFanout 16
......@@ -11,8 +11,8 @@ set clock_port_mempool_tile clk_i
create_clock -name clk_i -period $clock_cycle [get_ports $clock_port_mempool_tile]
set_clock_uncertainty $uncertainty [all_clocks]
set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==in && is_on_clock_network==false"]
set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==out && is_on_clock_network==false"]
#set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==in && is_on_clock_network==false"]
#set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==out && is_on_clock_network==false"]
set_max_transition $maxTransition -clock_path [get_clocks clk_i]
set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i]
#set_propagated_clock [get_clocks clk_i]
......@@ -20,7 +20,7 @@ set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i]
# Create virtual clock.
create_clock -name "vclk_i" -period $clock_cycle
set_clock_uncertainty $clk_uncertainty [get_clocks vclk_i]
set_clock_uncertainty $uncertainty [get_clocks vclk_i]
set_clock_latency $pre_cts_clock_latency_estimate [get_clocks vclk_i]
set_max_transition $maxTransition -clock_path [get_clocks vclk_i]
......@@ -34,26 +34,26 @@ set_max_fanout $maxFanout [current_design]
set_false_path -from tile_id_i
# TCDM Master
set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "hierarchical_name =~ tcdm_master_*req_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_master_*req_*"]
set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ tcdm_master_*req_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_master_*req_*"]
set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "hierarchical_name =~ tcdm_master_*resp_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_master_*resp_*"]
set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ tcdm_master_*resp_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_master_*resp_*"]
# TCDM Slave
set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "hierarchical_name =~ tcdm_slave_*req_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_slave_*req_*"]
set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ tcdm_slave_*req_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_slave_*req_*"]
set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "hierarchical_name =~ tcdm_slave_*resp_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_slave_*resp_*"]
set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ tcdm_slave_*resp_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_slave_*resp_*"]
# Refill port
set_input_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "hierarchical_name =~ refill_*"]
set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ refill_*"]
#set_input_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ refill_*"]
#set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ refill_*"]
# Reset
set_input_delay [expr 0.30*$clock_cycle] -clock vclk_i rst_ni
# Critical range
# Depending on the synthesis tool used, this can be helpful.
set_critical_range 0.100 [current_design]
#set_critical_range 0.100 [current_design]
Flows/NanGate45/mempool_tile/constraints/mempool_tile_wrap.sdc
set sdc_version 2.0
set_units -time ns -resistance kOhm -capacitance fF -power mW -voltage V -current uA
set clock_cycle 4
set clock_cycle 6.8
set uncertainty 0.08
set io_delay 0
set maxFanout 16
......@@ -11,9 +11,9 @@ set clock_port_mempool_tile clk_i
create_clock -name clk_i -period $clock_cycle [get_ports $clock_port_mempool_tile]
set_clock_uncertainty $uncertainty [all_clocks]
set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==in && is_on_clock_network==false"]
set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==out && is_on_clock_network==false"]
set_max_transition $maxTransition -clock_path [get_clocks clk_i]
#set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==in && is_on_clock_network==false"]
#set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==out && is_on_clock_network==false"]
#set_max_transition $maxTransition -clock_path [get_clocks clk_i]
set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i]
#set_propagated_clock [get_clocks clk_i]
......
Flows/NanGate45/mempool_tile/scripts/cadence/mmmc_setup.tcl
......@@ -4,8 +4,8 @@
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
create_rc_corner -name Cmax
create_rc_corner -name Cmin
create_rc_corner -name Cmax -qx_tech_file $qrc_max
create_rc_corner -name Cmin -qx_tech_file $qrc_min
create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
......
Flows/NanGate45/mempool_tile/scripts/cadence/run_genus_hybrid.tcl
......@@ -136,6 +136,7 @@ write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
......
Flows/NanGate45/mempool_tile/scripts/cadence/run_invs.tcl
......@@ -2,15 +2,15 @@
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
set rptDir summaryReport/
set encDir enc/
......@@ -39,6 +39,8 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setAnalysisMode -reset
setAnalysisMode -analysisType onChipVariation -cppr both
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -66,6 +68,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
refine_macro_place
}
### Write postSynth report ###
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_post_synth [extract_report postSynth]
echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
### Write out the def files ###
source ../../../../util/write_required_def.tcl
......@@ -83,8 +91,6 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......@@ -126,16 +132,21 @@ setNanoRouteMode -routeExpAdvancedTechnology true
setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
defOut -netlist -floorplan -routing ${DESIGN}_route.def
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
set rpt_post_route [extract_report postRoute]
#route_opt_design
optDesign -postRoute
set rpt_post_route [extract_report postRouteOpt]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
......
Flows/NanGate45/nvdla/scripts/cadence/mmmc_setup.tcl
......@@ -4,8 +4,8 @@
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
create_rc_corner -name Cmax
create_rc_corner -name Cmin
create_rc_corner -name Cmax -qx_tech_file $qrc_max
create_rc_corner -name Cmin -qx_tech_file $qrc_min
create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
......
Flows/NanGate45/nvdla/scripts/cadence/run_genus_hybrid.tcl
......@@ -139,6 +139,7 @@ write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
......
Flows/NanGate45/nvdla/scripts/cadence/run_invs.tcl
......@@ -2,7 +2,6 @@
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
......@@ -11,6 +10,7 @@ set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
source mmmc_setup.tcl
set rptDir summaryReport/
set encDir enc/
......@@ -39,6 +39,8 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setAnalysisMode -reset
setAnalysisMode -analysisType onChipVariation -cppr both
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -66,6 +68,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
refine_macro_place
}
### Write postSynth report ###
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_post_synth [extract_report postSynth]
echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
### Write out the def files ###
source ../../../../util/write_required_def.tcl
......@@ -83,8 +91,6 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......@@ -137,6 +143,11 @@ set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
#route_opt_design
optDesign -postRoute
set rpt_post_route [extract_report postRouteOpt]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
......
Flows/SKY130HD/ariane133/scripts/cadence/run_genus_hybrid.tcl
......@@ -136,6 +136,7 @@ write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
......
Flows/SKY130HD/ariane133/scripts/cadence/run_invs.tcl
......@@ -2,7 +2,6 @@
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
......@@ -11,6 +10,7 @@ set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
source mmmc_setup.tcl
set rptDir summaryReport/
set encDir enc/
......@@ -39,6 +39,8 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setAnalysisMode -reset
setAnalysisMode -analysisType onChipVariation -cppr both
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -66,6 +68,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
refine_macro_place
}
### Write postSynth report ###
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_post_synth [extract_report postSynth]
echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
### Write out the def files ###
source ../../../../util/write_required_def.tcl
......@@ -83,8 +91,6 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......@@ -138,6 +144,11 @@ echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
#route_opt_design
optDesign -postRoute
set rpt_post_route [extract_report postRouteOpt]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
......
Flows/SKY130HD/ariane136/scripts/cadence/run_genus_hybrid.tcl
......@@ -136,6 +136,7 @@ write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
......
Flows/SKY130HD/ariane136/scripts/cadence/run_invs.tcl
......@@ -2,7 +2,6 @@
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
......@@ -11,6 +10,7 @@ set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
source mmmc_setup.tcl
set rptDir summaryReport/
set encDir enc/
......@@ -39,6 +39,8 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setAnalysisMode -reset
setAnalysisMode -analysisType onChipVariation -cppr both
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -66,6 +68,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
refine_macro_place
}
### Write postSynth report ###
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_post_synth [extract_report postSynth]
echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
### Write out the def files ###
source ../../../../util/write_required_def.tcl
......@@ -83,8 +91,6 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......@@ -138,6 +144,11 @@ echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
#route_opt_design
optDesign -postRoute
set rpt_post_route [extract_report postRouteOpt]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
......
Flows/SKY130HD/mempool_tile/constraints/mempool_tile_wrap.sdc
set sdc_version 2.0
set_units -time ns -resistance kOhm -capacitance fF -power mW -voltage V -current uA
set clock_cycle 14
set clock_cycle 14.8
set uncertainty 0.08
set io_delay 0
set maxFanout 16
......@@ -11,9 +11,9 @@ set clock_port_mempool_tile clk_i
create_clock -name clk_i -period $clock_cycle [get_ports $clock_port_mempool_tile]
set_clock_uncertainty $uncertainty [all_clocks]
set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==in && is_on_clock_network==false"]
set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==out && is_on_clock_network==false"]
set_max_transition $maxTransition -clock_path [get_clocks clk_i]
#set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==in && is_on_clock_network==false"]
#set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==out && is_on_clock_network==false"]
#set_max_transition $maxTransition -clock_path [get_clocks clk_i]
set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i]
#set_propagated_clock [get_clocks clk_i]
......
Flows/SKY130HD/mempool_tile/scripts/cadence/run_genus_hybrid.tcl
......@@ -57,8 +57,7 @@ set_db init_hdl_search_path $rtldir
source rtl_list.tcl
foreach rtl_file $rtl_all {
#read_hdl -sv $rtl_file
read_hdl -language sv -define TARGET_SYNTHESIS -define XPULPIMG=1 $rtl_file
read_hdl -sv $rtl_file
}
elaborate $DESIGN
......@@ -137,6 +136,7 @@ write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
......
Flows/SKY130HD/mempool_tile/scripts/cadence/run_invs.tcl
......@@ -2,7 +2,6 @@
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
......@@ -11,6 +10,7 @@ set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
source mmmc_setup.tcl
set rptDir summaryReport/
set encDir enc/
......@@ -39,6 +39,8 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setAnalysisMode -reset
setAnalysisMode -analysisType onChipVariation -cppr both
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -66,6 +68,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
refine_macro_place
}
### Write postSynth report ###
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_post_synth [extract_report postSynth]
echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
### Write out the def files ###
source ../../../../util/write_required_def.tcl
......@@ -83,8 +91,6 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......@@ -138,6 +144,11 @@ echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
#route_opt_design
optDesign -postRoute
set rpt_post_route [extract_report postRouteOpt]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
......
Flows/SKY130HD/nvdla/scripts/cadence/run_invs.tcl
......@@ -2,7 +2,6 @@
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
......@@ -11,6 +10,7 @@ set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
source mmmc_setup.tcl
set rptDir summaryReport/
set encDir enc/
......@@ -39,6 +39,8 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setAnalysisMode -reset
setAnalysisMode -analysisType onChipVariation -cppr both
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -66,6 +68,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
refine_macro_place
}
### Write postSynth report ###
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_post_synth [extract_report postSynth]
echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
### Write out the def files ###
source ../../../../util/write_required_def.tcl
......@@ -83,8 +91,6 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......@@ -138,6 +144,11 @@ echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
#route_opt_design
optDesign -postRoute
set rpt_post_route [extract_report postRouteOpt]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
......
Flows/scripts/cadence/run.sh 0 → 100755
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
#!/bin/tcsh
module unload genus
module load genus/21.1
module unload innovus
module load innovus/21.1
#
# To run the Physical Synthesis (iSpatial) flow - flow2
export PHY_SYNTH=1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_CodeFlow.sh
Flows/scripts/cadence/run_genus.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
# Target library
set link_library $list_lib
set target_library $list_lib
# set path
set_db hdl_flatten_complex_port true
set_db hdl_record_naming_style %s_%s
set_db auto_ungroup none
set_db library $list_lib
#################################################
# Load Design and Initialize
#################################################
source rtl_list.tcl
foreach rtl_file $rtl_all {
read_hdl -sv $rtl_file
}
elaborate $DESIGN
time_info Elaboration
read_sdc $sdc
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
# keep hierarchy during synthesis
set_db auto_ungroup none
syn_generic
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
syn_map
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
syn_opt
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
#write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exit
Flows/scripts/cadence/run_genus_hybrid.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_mmmc mmmc_iSpatial_setup.tcl
}
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
read_physical -lefs $lefs
}
# Target library
set link_library $list_lib
set target_library $list_lib
# set pathi
set_db hdl_flatten_complex_port true
set_db hdl_record_naming_style %s_%s
set_db auto_ungroup none
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
set_db library $list_lib
}
#################################################
# Load Design and Initialize
#################################################
set_db init_hdl_search_path $rtldir
source rtl_list.tcl
foreach rtl_file $rtl_all {
read_hdl -sv $rtl_file
}
elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
#read_sdc $sdc
source $sdc
}
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
###############################################
# Read DEF
###############################################
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_def $floorplan_def
check_floorplan -detailed
}
# keep hierarchy during synthesis
set_db auto_ungroup none
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
}
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_map -physical
} else {
syn_map
}
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_opt -spatial
} else {
syn_opt
}
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exec cp ${HANDOFF_PATH}/${DESIGN}.CON.sdc ${HANDOFF_PATH}/${DESIGN}.sdc
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
}
exit
Flows/scripts/cadence/run_genus_iSpatial.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
read_mmmc mmmc_iSpatial_setup.tcl
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
read_physical -lefs $lefs
# Target library
set link_library $list_lib
set target_library $list_lib
# set path
set_db hdl_flatten_complex_port true
set_db hdl_record_naming_style %s_%s
set_db auto_ungroup none
#set_db library $list_lib
#################################################
# Load Design and Initialize
#################################################
source rtl_list.tcl
foreach rtl_file $rtl_all {
read_hdl -sv $rtl_file
}
elaborate $DESIGN
time_info Elaboration
#read_sdc $sdc
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
###############################################
# Read DEF
###############################################
read_def $floorplan_def
check_floorplan -detailed
# keep hierarchy during synthesis
set_db auto_ungroup none
syn_generic -physical
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
syn_map -physical
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
syn_opt -spatial
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
#write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
#write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exit
Flows/scripts/cadence/run_invs.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
set rptDir summaryReport/
set encDir enc/
if {![file exists $rptDir/]} {
exec mkdir $rptDir/
}
if {![file exists $encDir/]} {
exec mkdir $encDir/
}
# default settings
set init_pwr_net VDD
set init_gnd_net VSS
# default settings
set init_verilog "$netlist"
set init_design_netlisttype "Verilog"
set init_design_settop 1
set init_top_cell "$DESIGN"
set init_lef_file "$lefs"
# MCMM setup
init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setAnalysisMode -reset
setAnalysisMode -analysisType onChipVariation -cppr both
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
globalNetConnect VSS -type pgpin -pin VSS -inst * -override
globalNetConnect VDD -type tiehi -inst * -override
globalNetConnect VSS -type tielo -inst * -override
setOptMode -powerEffort low -leakageToDynamicRatio 0.5
setGenerateViaMode -auto true
generateVias
# basic path groups
createBasicPathGroups -expanded
### Write postSynth report ###
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_post_synth [extract_report postSynth]
echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
## Generate the floorplan ##
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl
gen_pb_netlist
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
}
### Write out the def files ###
source ../../../../util/write_required_def.tcl
### Add power plan ###
source ../../../../../Enablements/NanGate45/util/pdn_config.tcl
source ../../../../util/pdn_flow.tcl
saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
create_ccopt_clock_tree_spec
ccopt_design
set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks]
set_clock_propagation propagated
saveDesign $encDir/${DESIGN}_cts.enc
set rpt_post_cts [extract_report postCTS]
echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeUseAutoVia true
##Recommended by lib owners
# Prevent router modifying M1 pins shapes
setNanoRouteMode -routeWithViaInPin "1:1"
setNanoRouteMode -routeWithViaOnlyForStandardCellPin "1:1"
## limit VIAs to ongrid only for VIA1 (S1)
setNanoRouteMode -drouteOnGridOnly "via 1:1"
setNanoRouteMode -drouteAutoStop false
setNanoRouteMode -drouteExpAdvancedMarFix true
setNanoRouteMode -routeExpAdvancedTechnology true
#SM suggestion for solving long extraction runtime during GR
setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
saveDesign ${encDir}/${DESIGN}_route.enc
defOut -netlist -floorplan -routing ${DESIGN}_route.def
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
#route_opt_design
optDesign -postRoute
set rpt_post_route [extract_report postRouteOpt]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
exit
Flows/util/extract_report.tcl
......@@ -62,9 +62,12 @@ proc extract_report {stage} {
timeDesign -postCTS -prefix ${stage}
} elseif { $stage == "postRoute" } {
timeDesign -postRoute -prefix ${stage}
} elseif { $stage == "postRouetOpt" } {
} elseif { $stage == "postRouteOpt" } {
timeDesign -postRoute -prefix ${stage}
} elseif { $stage == "postSynth" } {
timeDesign -prePlace -prefix ${stage}
}
set rpt1 [extract_from_timing_rpt timingReports/${stage}.summary.gz]
report_power > power_${stage}.rpt
set rpt2 [extract_from_power_rpt power_${stage}.rpt]
......
Flows/util/gen_macro_place_def.sh 0 → 100755
#!/bin/tcsh
## Set to 1 to run refine_macro_place ##
setenv run_refine_macro_place 0
setenv SYN_HANDOFF $argv[1]
if ($#argv == 3) then
setenv pb_netlist $argv[2]
setenv plc_file $argv[3]
else
echo "Required clustered netlist and plc file to generate macro placed defs"
endif
module unload innovus
module load innovus/21.1
innovus -64 -overwrite -log log/macro_placement_generation_innovus.log -files ../../../../util/gen_macro_place_def.tcl
## Edit the design file to make sure flow2 reads the new macro placed def instead of the default one
set def_file=`ls *_fp_new_placed_macros.def | head -n1`
sed -i "s@\S*_fp_placed_macros.def@${def_file}@" design_setup.tcl
Flows/util/gen_macro_place_def.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
set handoff_dir $::env(SYN_HANDOFF)
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
# default settings
set init_pwr_net VDD
set init_gnd_net VSS
# default settings
set init_verilog "$netlist"
set init_design_netlisttype "Verilog"
set init_design_settop 1
set init_top_cell "$DESIGN"
set init_lef_file "$lefs"
# MCMM setup
init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setAnalysisMode -reset
setAnalysisMode -analysisType onChipVariation -cppr both
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
globalNetConnect VSS -type pgpin -pin VSS -inst * -override
globalNetConnect VDD -type tiehi -inst * -override
globalNetConnect VSS -type tielo -inst * -override
setOptMode -powerEffort low -leakageToDynamicRatio 0.5
setGenerateViaMode -auto true
generateVias
# basic path groups
createBasicPathGroups -expanded
## Generate the floorplan ##
defIn $floorplan_def
set origin_x [dbget top.fPlan.coreBox_llx]
set origin_y [dbget top.fPlan.coreBox_lly]
if {[info exist ::env(pb_netlist)] &&
[info exist ::env(plc_file)] &&
[file exist $::env(pb_netlist)] &&
[file exist $::env(plc_file)]} {
exec /home/sakundu/.conda/envs/py-tf/bin/python3.8 \
../../../../util/plc_pb_to_placement_tcl.py $::env(plc_file) $::env(pb_netlist) \
"macro_place.tcl" $origin_x $origin_y
}
if { [info exist ::env(run_refine_macro_place)] && $::env(run_refine_macro_place) == 1 } {
dbset [dbget top.insts.cell.subClass block -p2 ].pStatus placed
refine_macro_place
}
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
dbset [dbget top.insts.cell.subClass block -p2 ].pStatus fixed
defOut -floorplan ./${DESIGN}_fp_new_placed_macros.def
exit
Flows/util/gen_pb.tcl
......@@ -16,20 +16,16 @@ proc print_header { fp } {
set user [exec whoami]
set date [exec date]
set run_dir [exec pwd]
set fp_box_ll [dbget top.fplan.box_ll]
set fp_box_ur [dbget top.fplan.box_ur]
set canvas_width [dbget top.fplan.coreBox_sizex]
set canvas_height [dbget top.fplan.coreBox_sizey]
puts $fp "# User: $user"
puts $fp "# Date: $date"
puts $fp "# Run area: $run_dir"
puts $fp "# Block : $design"
puts $fp "# FP bbox: $fp_box_ll $fp_box_ur"
puts $fp "# FP bbox: {0.0 0.0} {$canvas_width $canvas_height}"
## Add dummy Column and Row info ##
puts $fp "# Columns : 10 Rows : 10"
## Add blockage for core to die spacing ##
foreach box [dbShape -output rect [dbget top.fplan.box] XOR [dbget top.fplan.coreBox]] {
puts $fp "# Blockage : $box 1"
}
}
#### Print helper ####
......@@ -96,7 +92,7 @@ proc print_net { net_ptr fp } {
}
#### Procedure to write Ports ####
proc write_node_port { port_ptr fp } {
proc write_node_port { port_ptr fp {origin_x 0} {origin_y 0} } {
puts $fp "node {"
set name [lindex [dbget ${port_ptr}.name] 0]
......@@ -130,19 +126,27 @@ proc write_node_port { port_ptr fp } {
set X1 [lindex [dbget ${port_ptr}.pinShapes.rect] 0 0]
set X2 [lindex [dbget ${port_ptr}.pinShapes.rect] 0 2]
set X [expr ($X1 + $X2)/2]
if {$side == "top" || $side == "bottom"} {
set X [expr $X - $origin_x]
}
print_float $fp "x" $X
### Attribute: Y ###
set Y1 [lindex [dbget ${port_ptr}.pinShapes.rect] 0 1]
set Y2 [lindex [dbget ${port_ptr}.pinShapes.rect] 0 3]
set Y [expr ($Y1 + $Y2)/2]
if {$side == "left" || $side == "right"} {
set Y [expr $Y - $origin_y]
}
print_float $fp "y" $Y
puts $fp "}"
}
#### Procedure to write Macros ####
proc write_node_macro { macro_ptr fp } {
proc write_node_macro { macro_ptr fp {origin_x 0} {origin_y 0}} {
puts $fp "node {"
set name [lindex [dbget ${macro_ptr}.name] 0]
......@@ -166,13 +170,13 @@ proc write_node_macro { macro_ptr fp } {
### Attribute: X ###
set X1 [lindex [dbget ${macro_ptr}.box] 0 0]
set X2 [lindex [dbget ${macro_ptr}.box] 0 2]
set X [expr ($X1 + $X2)/2]
set X [expr ($X1 + $X2)/2 - $origin_x]
print_float $fp "x" $X
### Attribute: Y ###
set Y1 [lindex [dbget ${macro_ptr}.box] 0 1]
set Y2 [lindex [dbget ${macro_ptr}.box] 0 3]
set Y [expr ($Y1 + $Y2)/2]
set Y [expr ($Y1 + $Y2)/2 - $origin_y]
print_float $fp "y" $Y
### Attribute: Y ###
......@@ -184,7 +188,7 @@ proc write_node_macro { macro_ptr fp } {
}
#### Procedure to Write Macro Pins ####
proc write_node_macro_pin { macro_pin_ptr fp } {
proc write_node_macro_pin { macro_pin_ptr fp {origin_x 0} {origin_y 0}} {
puts $fp "node {"
set name [lindex [dbget ${macro_pin_ptr}.name] 0]
......@@ -203,8 +207,8 @@ proc write_node_macro_pin { macro_pin_ptr fp } {
### Attribute: type ###
print_placeholder $fp "type" "macro_pin"
set X [dbget ${macro_pin_ptr}.pt_x]
set Y [dbget ${macro_pin_ptr}.pt_y]
set X [expr [dbget ${macro_pin_ptr}.pt_x] - $origin_x]
set Y [expr [dbget ${macro_pin_ptr}.pt_y] - $origin_y]
set cell_height [dbget ${macro_pin_ptr}.cellTerm.cell.size_y]
set cell_width [dbget ${macro_pin_ptr}.cellTerm.cell.size_x]
set pin_x [dbget ${macro_pin_ptr}.cellTerm.pt_x]
......@@ -228,7 +232,7 @@ proc write_node_macro_pin { macro_pin_ptr fp } {
}
#### Procedure to Write Std-cell ###
proc write_node_stdcell { inst_ptr fp } {
proc write_node_stdcell { inst_ptr fp {origin_x 0} {origin_y 0}} {
puts $fp "node {"
set name [lindex [dbget ${inst_ptr}.name] 0]
......@@ -257,13 +261,13 @@ proc write_node_stdcell { inst_ptr fp } {
### Attribute: X ###
set X1 [lindex [dbget ${inst_ptr}.box] 0 0]
set X2 [lindex [dbget ${inst_ptr}.box] 0 2]
set X [expr ($X1 + $X2)/2]
set X [expr ($X1 + $X2)/2 - $origin_x]
print_float $fp "x" $X
### Attribute: Y ###
set Y1 [lindex [dbget ${inst_ptr}.box] 0 1]
set Y2 [lindex [dbget ${inst_ptr}.box] 0 3]
set Y [expr ($Y1 + $Y2)/2]
set Y [expr ($Y1 + $Y2)/2 - $origin_y]
print_float $fp "y" $Y
puts $fp "}"
......@@ -276,20 +280,22 @@ proc gen_pb_netlist { } {
set fp [open $out_file w+]
print_header $fp
set origin_x [dbget top.fplan.coreBox_llx]
set origin_y [dbget top.fplan.coreBox_lly]
foreach port_ptr [dbget top.terms] {
write_node_port $port_ptr $fp
write_node_port $port_ptr $fp $origin_x $origin_y
}
foreach macro_ptr [dbget top.insts.cell.subClass block -p2] {
write_node_macro $macro_ptr $fp
write_node_macro $macro_ptr $fp $origin_x $origin_y
foreach macro_pin_ptr [dbget ${macro_ptr}.instTerms] {
write_node_macro_pin $macro_pin_ptr $fp
write_node_macro_pin $macro_pin_ptr $fp $origin_x $origin_y
}
}
foreach inst_ptr [dbget top.insts.cell.subClass core -p2] {
write_node_stdcell $inst_ptr $fp
write_node_stdcell $inst_ptr $fp $origin_x $origin_y
}
close $fp
......
Flows/util/gen_pb_blockage.tcl 0 → 100644
#############################################################################
# This script was written and developed by ABKGroup students at UCSD.
# However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help
# promote and foster the next generation of innovators.
# Author: Sayak Kundu, ABKGroup, UCSD
#
# Usage: First source the script in Innovus shell. then use gen_pb_netlist
# command to write out the netlist. The protobuf netlist will be available
# as <design name>.pb.txt.
#############################################################################
#### Print the design header ####
proc print_header { fp } {
set design [dbget top.name]
set user [exec whoami]
set date [exec date]
set run_dir [exec pwd]
set fp_box_ll [dbget top.fplan.box_ll]
set fp_box_ur [dbget top.fplan.box_ur]
puts $fp "# User: $user"
puts $fp "# Date: $date"
puts $fp "# Run area: $run_dir"
puts $fp "# Block : $design"
puts $fp "# FP bbox: $fp_box_ll $fp_box_ur"
## Add dummy Column and Row info ##
puts $fp "# Columns : 10 Rows : 10"
## Add blockage for core to die spacing ##
foreach box [dbShape -output rect [dbget top.fplan.box] XOR [dbget top.fplan.coreBox]] {
puts $fp "# Blockage : $box 1"
}
}
#### Print helper ####
proc print_placeholder { fp key value } {
puts $fp " attr {"
puts $fp " key: \"$key\""
puts $fp " value {"
puts $fp " placeholder: \"$value\""
puts $fp " }"
puts $fp " }"
}
proc print_float { fp key value } {
puts $fp " attr {"
puts $fp " key: \"$key\""
puts $fp " value {"
puts $fp " f: $value"
puts $fp " }"
puts $fp " }"
}
### Helper to convert Orientation format ###
proc get_orient { tmp_orient } {
set orient "N"
if { $tmp_orient == "R0"} {
set orient "N"
} elseif { $tmp_orient == "R180" } {
set orient "S"
} elseif { $tmp_orient == "R90" } {
set orient "W"
} elseif { $tmp_orient == "R270" } {
set orient "E"
} elseif { $tmp_orient == "MY" } {
set oreint "FN"
} elseif { $tmp_orient == "MX" } {
set oreint "FS"
} elseif { $tmp_orient == "MX90" } {
set orient "FW"
} elseif { $tmp_orient == "MY90" } {
set orient "FE"
}
return $orient
}
#### Procedure to print the sinks ####
proc print_net { net_ptr fp } {
### Print Terms ###
foreach term [dbget [dbget ${net_ptr}.terms.isOutput 1 -p ].name -e] {
puts $fp " input: \"${term}\""
}
### Print Macro Pins ###
foreach macro_pin [dbget [dbget [dbget ${net_ptr}.instTerms.isInput 1 -p \
].inst.cell.subClass block -p3 ].name -e] {
puts $fp " input: \"${macro_pin}\""
}
### Print Stdcells ###
foreach inst [dbget [dbget [dbget ${net_ptr}.instTerms.isInput 1 -p \
].inst.cell.subClass core -p2 ].name -e] {
puts $fp " input: \"${inst}\""
}
}
#### Procedure to write Ports ####
proc write_node_port { port_ptr fp } {
puts $fp "node {"
set name [lindex [dbget ${port_ptr}.name] 0]
puts $fp " name: \"${name}\""
if { [dbget ${port_ptr}.isInput] == 1 } {
set net_ptr [dbget ${port_ptr}.net]
print_net $net_ptr $fp
}
### Attribute: type ###
print_placeholder $fp "type" "port"
### Attribute: Side ###
set tmp_side [dbget ${port_ptr}.side]
set side ""
if {$tmp_side == "West"} {
set side "left"
} elseif {$tmp_side == "East"} {
set side "right"
} elseif {$tmp_side == "North"} {
set side "top"
} elseif {$tmp_side == "South"} {
set side "bottom"
} else {
puts "Error: Wrong Direction. Port Name: $name"
}
print_placeholder $fp "side" $side
### Attribute: X ###
set X1 [lindex [dbget ${port_ptr}.pinShapes.rect] 0 0]
set X2 [lindex [dbget ${port_ptr}.pinShapes.rect] 0 2]
set X [expr ($X1 + $X2)/2]
print_float $fp "x" $X
### Attribute: Y ###
set Y1 [lindex [dbget ${port_ptr}.pinShapes.rect] 0 1]
set Y2 [lindex [dbget ${port_ptr}.pinShapes.rect] 0 3]
set Y [expr ($Y1 + $Y2)/2]
print_float $fp "y" $Y
puts $fp "}"
}
#### Procedure to write Macros ####
proc write_node_macro { macro_ptr fp } {
puts $fp "node {"
set name [lindex [dbget ${macro_ptr}.name] 0]
puts $fp " name: \"${name}\""
### Attribute: ref_name ###
set ref_name [dbget ${macro_ptr}.cell.name]
print_placeholder $fp "ref_name" ${ref_name}
### Attribute: Width ###
set width [dbget ${macro_ptr}.box_sizex]
print_float $fp "width" $width
### Attribute: Height ###
set height [dbget ${macro_ptr}.box_sizey]
print_float $fp "height" $height
### Attribute: type ###
print_placeholder $fp "type" "macro"
### Attribute: X ###
set X1 [lindex [dbget ${macro_ptr}.box] 0 0]
set X2 [lindex [dbget ${macro_ptr}.box] 0 2]
set X [expr ($X1 + $X2)/2]
print_float $fp "x" $X
### Attribute: Y ###
set Y1 [lindex [dbget ${macro_ptr}.box] 0 1]
set Y2 [lindex [dbget ${macro_ptr}.box] 0 3]
set Y [expr ($Y1 + $Y2)/2]
print_float $fp "y" $Y
### Attribute: Y ###
set tmp_orient [dbget ${macro_ptr}.orient]
set orient [get_orient $tmp_orient]
print_placeholder $fp "orientation" $orient
puts $fp "}"
}
#### Procedure to Write Macro Pins ####
proc write_node_macro_pin { macro_pin_ptr fp } {
puts $fp "node {"
set name [lindex [dbget ${macro_pin_ptr}.name] 0]
puts $fp " name: \"${name}\""
### Print all the sinks ###
if { [dbget ${macro_pin_ptr}.isOutput] == 1} {
set net_ptr [dbget ${macro_pin_ptr}.net]
print_net $net_ptr $fp
}
### Attribute: Macro Name ###
set macro_name [lindex [dbget ${macro_pin_ptr}.inst.name] 0]
print_placeholder $fp "macro_name" $macro_name
### Attribute: type ###
print_placeholder $fp "type" "macro_pin"
set X [dbget ${macro_pin_ptr}.pt_x]
set Y [dbget ${macro_pin_ptr}.pt_y]
set cell_height [dbget ${macro_pin_ptr}.cellTerm.cell.size_y]
set cell_width [dbget ${macro_pin_ptr}.cellTerm.cell.size_x]
set pin_x [dbget ${macro_pin_ptr}.cellTerm.pt_x]
set pin_y [dbget ${macro_pin_ptr}.cellTerm.pt_y]
set x_offset [expr $pin_x - $cell_width/2]
set y_offset [expr $pin_y - $cell_height/2]
### Attribute: x_offset ###
print_float $fp "x_offset" $x_offset
### Attribute: y_offset ###
print_float $fp "y_offset" $y_offset
### Attribute: X ###
print_float $fp "x" $X
### Attribute: Y ###
print_float $fp "y" $Y
puts $fp "}"
}
#### Procedure to Write Std-cell ###
proc write_node_stdcell { inst_ptr fp } {
puts $fp "node {"
set name [lindex [dbget ${inst_ptr}.name] 0]
puts $fp " name: \"${name}\""
### Print all the sinks ###
foreach net_ptr [dbget [dbget ${inst_ptr}.instTerms.isOutput 1 -p ].net -e ] {
print_net $net_ptr $fp
}
### Attribute: ref_name ###
set ref_name [dbget ${inst_ptr}.cell.name]
print_placeholder $fp "ref_name" $ref_name
### Attribute: Width ###
set width [dbget ${inst_ptr}.box_sizex]
print_float $fp "width" $width
### Attribute: Height ###
set height [dbget ${inst_ptr}.box_sizey]
print_float $fp "height" $height
### Attribute: type ###
print_placeholder $fp "type" "stdcell"
### Attribute: X ###
set X1 [lindex [dbget ${inst_ptr}.box] 0 0]
set X2 [lindex [dbget ${inst_ptr}.box] 0 2]
set X [expr ($X1 + $X2)/2]
print_float $fp "x" $X
### Attribute: Y ###
set Y1 [lindex [dbget ${inst_ptr}.box] 0 1]
set Y2 [lindex [dbget ${inst_ptr}.box] 0 3]
set Y [expr ($Y1 + $Y2)/2]
print_float $fp "y" $Y
puts $fp "}"
}
#### Generate protobuff format netlist ####
proc gen_pb_netlist { } {
set design [dbget top.name]
set out_file "${design}.pb.txt"
set fp [open $out_file w+]
print_header $fp
foreach port_ptr [dbget top.terms] {
write_node_port $port_ptr $fp
}
foreach macro_ptr [dbget top.insts.cell.subClass block -p2] {
write_node_macro $macro_ptr $fp
foreach macro_pin_ptr [dbget ${macro_ptr}.instTerms] {
write_node_macro_pin $macro_pin_ptr $fp
}
}
foreach inst_ptr [dbget top.insts.cell.subClass core -p2] {
write_node_stdcell $inst_ptr $fp
}
close $fp
puts "Output netlist: $out_file"
}
Flows/util/pdn_flow.tcl
......@@ -113,11 +113,11 @@ while { $i < $lcount } {
} elseif { $ism == 1 } {
setAddStripeMode -extend_to_closest_target none
setAddStripeMode -inside_cell_only true
foreach mcell [dbget [dbget top.insts.cell.subClass block -p2 ].cell.name -u] {
foreach mcell [dbget [dbget top.insts.cell.subClass block -p2 ].cell.name -u -e] {
addStripe -layer $lname -direction $dir -nets $nets -width $wdth -spacing $spc \
-start_offset $sofst -set_to_set_distance $ptch -master $mcell
}
foreach inst [dbget [dbget top.insts.cell.subClass block -p2 ].name ] {
foreach inst [dbget [dbget top.insts.cell.subClass block -p2 ].name -e ] {
createRouteBlk -inst $inst -cover -layer $prevLayer -name mcro_blk
}
} elseif { $isam == 1 } {
......
Flows/util/plc_pb_to_placement_tcl.py
......@@ -9,7 +9,14 @@ plc_file = sys.argv[1]
pb_file = sys.argv[2]
place_tcl = sys.argv[3]
print(f'PLC:\t{plc_file}\nPB:\t{pb_file}\nTCL:\t{place_tcl}')
origin_x = 0
origin_y = 0
print(f"Length of Argument: {len(sys.argv)}")
if len(sys.argv) == 6:
origin_x = float(sys.argv[4])
origin_y = float(sys.argv[5])
print(f'PLC:\t{plc_file}\nPB:\t{pb_file}\nTCL:\t{place_tcl}\nOrigin X:{origin_x} Y:{origin_y}')
orientMap = {
"N" : "R0",
......@@ -94,8 +101,8 @@ for line in lines:
if id_pattern.match(words[0]) and (len(words) == 5):
idx = int(words[0])
if node_list[idx].pb_type == '"MACRO"':
x = float(words[1]) - float(node_list[idx].width)/2.0
y = float(words[2]) - float(node_list[idx].height)/2.0
x = float(words[1]) - float(node_list[idx].width)/2.0 + origin_x
y = float(words[2]) - float(node_list[idx].height)/2.0 + origin_y
orient = orientMap[words[3]]
isFixed = words[4]
macro_name = node_list[idx].name.replace('_[', '\[')
......
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