Skip to content

M
macroplacement
Commit 1ff30649 by ZhiangWang033
Options

Merge branch 'main' of https://github.com/TILOS-AI-Institute/MacroPlacement into main

parents 8b81963b 42f8b4e6
Showing with 869 additions and 127 deletions
.gitignore
Flows/*/*/run/*/
Flows/*/*/run-*
Flows/job
CodeElements/*/*/__pycache__
Flows/ASAP7/ariane133/netlist/ariane.v
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/NanGate45/ariane133/netlist/ariane.v
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/SKY130HD/ariane133/def/ariane133_mp_fp.def deleted 100644 → 0
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/SKY130HD/ariane133/netlist/ariane.v
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/SKY130HD/ariane133/scripts/cadence/design_setup.tcl
......@@ -3,9 +3,14 @@
set DESIGN ariane
set sdc ../../constraints/${DESIGN}.sdc
set rtldir ../../rtl
# def file with die size and placed IO pins
set floorplan_def ../../def/ariane133_fp.def
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set floorplan_def ../../def/ariane133_fp_placed_macros.def
} else {
set floorplan_def ../../def/ariane133_fp.def
}
#
# Effort level during optimization in syn_generic -physical (or called generic) stage
# possible values are : high, medium or low
......@@ -14,3 +19,7 @@ set GEN_EFF medium
# Effort level during optimization in syn_map -physical (or called mapping) stage
# possible values are : high, medium or low
set MAP_EFF high
#
set SITE "unithd"
set HALO_WIDTH 5
set TOP_ROUTING_LAYER 9
Flows/SKY130HD/ariane133/scripts/cadence/lib_setup.tcl
......@@ -34,3 +34,5 @@ set lefs "
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 130
set qrc_max "${qrcdir}/SKY130HD.tch"
set qrc_min "${qrcdir}/SKY130HD.tch"
Flows/SKY130HD/ariane133/scripts/cadence/mmmc_setup.tcl
......@@ -4,8 +4,8 @@
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
create_rc_corner -name Cmax
create_rc_corner -name Cmin
create_rc_corner -name Cmax -qx_tech_file $qrc_max
create_rc_corner -name Cmin -qx_tech_file $qrc_min
create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
......
Flows/SKY130HD/ariane133/scripts/cadence/run.sh 100644 → 100755
......@@ -6,6 +6,10 @@ module load genus/21.1
module unload innovus
module load innovus/21.1
#
# To run the Physical Synthesis (iSpatial) flow - flow2
export PHY_SYNTH=0
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
Flows/SKY130HD/ariane133/scripts/cadence/run_genus_hybrid.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_mmmc mmmc_iSpatial_setup.tcl
}
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
read_physical -lefs $lefs
}
# Target library
set link_library $list_lib
set target_library $list_lib
# set pathi
set_db hdl_flatten_complex_port true
set_db hdl_record_naming_style %s_%s
set_db auto_ungroup none
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
set_db library $list_lib
}
#################################################
# Load Design and Initialize
#################################################
set_db init_hdl_search_path $rtldir
source rtl_list.tcl
foreach rtl_file $rtl_all {
read_hdl -sv $rtl_file
}
elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
#read_sdc $sdc
source $sdc
}
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
###############################################
# Read DEF
###############################################
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_def $floorplan_def
check_floorplan -detailed
}
# keep hierarchy during synthesis
set_db auto_ungroup none
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
}
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_map -physical
} else {
syn_map
}
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_opt -spatial
} else {
syn_opt
}
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
}
exit
Flows/SKY130HD/ariane133/scripts/cadence/run_invs.tcl
......@@ -7,10 +7,10 @@ source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
set netlist "./syn_handoff/$DESIGN.v"
set sdc "./syn_handoff/$DESIGN.sdc"
set handoff_dir "./syn_handoff"
set site "unithd"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
set rptDir summaryReport/
set encDir enc/
......@@ -55,26 +55,20 @@ generateVias
createBasicPathGroups -expanded
## Generate the floorplan ##
#floorPlan -r 1.0 $util 10 10 10 10
defIn $floorplan_def
## Macro Placement ##
#redirect mp_config.tcl {source gen_mp_config.tcl}
#proto_design -constraints mp_config.tcl
addHaloToBlock -allMacro 5 5 5 5
place_design -concurrent_macros
refine_macro_place
saveDesign ${encDir}/${DESIGN}_floorplan.enc
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
}
## Creating Pin Blcokage for lower and upper pin layers ##
createPinBlkg -name Layer_1 -layer {met2 met3 met9} -edge 0
createPinBlkg -name side_top -edge 1
createPinBlkg -name side_right -edge 2
createPinBlkg -name side_bottom -edge 3
saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setDesignMode -topRoutingLayer 9
setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
......
Flows/SKY130HD/ariane136/def/ariane136_fp_rows.def deleted 100644 → 0
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/SKY130HD/ariane136/scripts/cadence/design_setup.tcl
......@@ -3,9 +3,14 @@
set DESIGN ariane
set sdc ../../constraints/${DESIGN}.sdc
set rtldir ../../../../../Testcases/ariane136/rtl
# def file with die size and placed IO pins
set floorplan_def ../../def/ariane136_fp.def
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set floorplan_def ../../def/ariane136_fp_placed_macros.def
} else {
set floorplan_def ../../def/ariane136_fp.def
}
#
# Effort level during optimization in syn_generic -physical (or called generic) stage
# possible values are : high, medium or low
......@@ -14,3 +19,7 @@ set GEN_EFF medium
# Effort level during optimization in syn_map -physical (or called mapping) stage
# possible values are : high, medium or low
set MAP_EFF high
#
set SITE "unithd"
set HALO_WIDTH 5
set TOP_ROUTING_LAYER 9
Flows/SKY130HD/ariane136/scripts/cadence/lib_setup.tcl
......@@ -34,3 +34,5 @@ set lefs "
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 130
set qrc_max "${qrcdir}/SKY130HD.tch"
set qrc_min "${qrcdir}/SKY130HD.tch"
Flows/SKY130HD/ariane136/scripts/cadence/mmmc_iSpatial_setup.tcl
......@@ -10,10 +10,8 @@ create_library_set -name BC_LIB -timing $libbest
create_timing_condition -name timing_wc -library_sets { WC_LIB }
create_timing_condition -name timing_bc -library_sets { BC_LIB }
#create_rc_corner -name Cmax -qrc_tech $qrc_max
#create_rc_corner -name Cmin -qrc_tech $qrc_min
create_rc_corner -name Cmax
create_rc_corner -name Cmin
create_rc_corner -name Cmax -qrc_tech $qrc_max
create_rc_corner -name Cmin -qrc_tech $qrc_min
create_delay_corner -name WC -early_timing_condition { timing_wc } \
-late_timing_condition { timing_wc } \
......
Flows/SKY130HD/ariane136/scripts/cadence/mmmc_setup.tcl
......@@ -4,8 +4,8 @@
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
create_rc_corner -name Cmax
create_rc_corner -name Cmin
create_rc_corner -name Cmax -qx_tech_file $qrc_max
create_rc_corner -name Cmin -qx_tech_file $qrc_min
create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
......
Flows/SKY130HD/ariane136/scripts/cadence/run.sh
......@@ -6,6 +6,10 @@ module load genus/21.1
module unload innovus
module load innovus/21.1
#
# To run the Physical Synthesis (iSpatial) flow - flow2
export PHY_SYNTH=0
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
Flows/SKY130HD/ariane136/scripts/cadence/run_genus_hybrid.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_mmmc mmmc_iSpatial_setup.tcl
}
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
read_physical -lefs $lefs
}
# Target library
set link_library $list_lib
set target_library $list_lib
# set pathi
set_db hdl_flatten_complex_port true
set_db hdl_record_naming_style %s_%s
set_db auto_ungroup none
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
set_db library $list_lib
}
#################################################
# Load Design and Initialize
#################################################
set_db init_hdl_search_path $rtldir
source rtl_list.tcl
foreach rtl_file $rtl_all {
read_hdl -sv $rtl_file
}
elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
#read_sdc $sdc
source $sdc
}
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
###############################################
# Read DEF
###############################################
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_def $floorplan_def
check_floorplan -detailed
}
# keep hierarchy during synthesis
set_db auto_ungroup none
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
}
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_map -physical
} else {
syn_map
}
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_opt -spatial
} else {
syn_opt
}
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
}
exit
Flows/SKY130HD/ariane136/scripts/cadence/run_invs.tcl
......@@ -7,10 +7,10 @@ source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
set netlist "./syn_handoff/$DESIGN.v"
set sdc "./syn_handoff/$DESIGN.sdc"
set handoff_dir "./syn_handoff"
set site "unithd"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
set rptDir summaryReport/
set encDir enc/
......@@ -55,26 +55,20 @@ generateVias
createBasicPathGroups -expanded
## Generate the floorplan ##
#floorPlan -r 1.0 $util 10 10 10 10
defIn $floorplan_def
## Macro Placement ##
#redirect mp_config.tcl {source gen_mp_config.tcl}
#proto_design -constraints mp_config.tcl
addHaloToBlock -allMacro 5 5 5 5
place_design -concurrent_macros
refine_macro_place
saveDesign ${encDir}/${DESIGN}_floorplan.enc
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
}
## Creating Pin Blcokage for lower and upper pin layers ##
createPinBlkg -name Layer_1 -layer {met2 met3 met9} -edge 0
createPinBlkg -name side_top -edge 1
createPinBlkg -name side_right -edge 2
createPinBlkg -name side_bottom -edge 3
saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setDesignMode -topRoutingLayer 9
setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
......
Flows/SKY130HD/mempool_tile/constraints/mempool_tile_wrap.sdc
......@@ -20,7 +20,7 @@ set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i]
# Create virtual clock.
create_clock -name "vclk_i" -period $clock_cycle
set_clock_uncertainty $clk_uncertainty [get_clocks vclk_i]
set_clock_uncertainty $uncertainty [get_clocks vclk_i]
set_clock_latency $pre_cts_clock_latency_estimate [get_clocks vclk_i]
set_max_transition $maxTransition -clock_path [get_clocks vclk_i]
......@@ -34,22 +34,22 @@ set_max_fanout $maxFanout [current_design]
set_false_path -from tile_id_i
# TCDM Master
set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "hierarchical_name =~ tcdm_master_*req_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_master_*req_*"]
set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ tcdm_master_*req_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_master_*req_*"]
set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "hierarchical_name =~ tcdm_master_*resp_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_master_*resp_*"]
set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ tcdm_master_*resp_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_master_*resp_*"]
# TCDM Slave
set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "hierarchical_name =~ tcdm_slave_*req_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_slave_*req_*"]
set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ tcdm_slave_*req_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_slave_*req_*"]
set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "hierarchical_name =~ tcdm_slave_*resp_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_slave_*resp_*"]
set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ tcdm_slave_*resp_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_slave_*resp_*"]
# Refill port
set_input_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "hierarchical_name =~ refill_*"]
set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ refill_*"]
#set_input_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ refill_*"]
#set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ refill_*"]
# Reset
set_input_delay [expr 0.30*$clock_cycle] -clock vclk_i rst_ni
......
Flows/SKY130HD/mempool_tile/def/mempool_tile_wrap_fp.def
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/SKY130HD/mempool_tile/def/mempool_tile_wrap_fp_placed_macros.def 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/SKY130HD/mempool_tile/def/mempool_tile_wrap_mp_fp.def deleted 100644 → 0
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/SKY130HD/mempool_tile/netlist/mempool_tile_wrap.v
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/SKY130HD/mempool_tile/scripts/cadence/design_setup.tcl
......@@ -6,7 +6,11 @@ set rtldir ../../../../../Testcases/mempool/rtl
set sdc ../../constraints/${DESIGN}.sdc
# def file with die size and placed IO pins
set floorplan_def ../../def/mempool_tile_wrap_fp.def
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set floorplan_def ../../def/${DESIGN}_fp_placed_macros.def
} else {
set floorplan_def ../../def/${DESIGN}_fp.def
}
#
# Effort level during optimization in syn_generic -physical (or called generic) stage
# possible values are : high, medium or low
......@@ -15,3 +19,7 @@ set GEN_EFF medium
# Effort level during optimization in syn_map -physical (or called mapping) stage
# possible values are : high, medium or low
set MAP_EFF high
#
set SITE "unithd"
set HALO_WIDTH 5
set TOP_ROUTING_LAYER 9
Flows/SKY130HD/mempool_tile/scripts/cadence/lib_setup.tcl
......@@ -37,3 +37,5 @@ set lefs "
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 130
set qrc_max "${qrcdir}/SKY130HD.tch"
set qrc_min "${qrcdir}/SKY130HD.tch"
Flows/SKY130HD/mempool_tile/scripts/cadence/mmmc_iSpatial_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
#create_opcond -name op_cond_wc -process 1.0 -voltage 0.72 -temperature 125
#create_opcond -name op_cond_bc -process 1.0 -voltage 0.88 -temperature -40
create_timing_condition -name timing_wc -library_sets { WC_LIB }
create_timing_condition -name timing_bc -library_sets { BC_LIB }
create_rc_corner -name Cmax -qrc_tech $qrc_max
create_rc_corner -name Cmin -qrc_tech $qrc_min
create_delay_corner -name WC -early_timing_condition { timing_wc } \
-late_timing_condition { timing_wc } \
-early_rc_corner Cmax \
-late_rc_corner Cmax
create_delay_corner -name BC -early_timing_condition { timing_bc } \
-late_timing_condition { timing_bc } \
-early_rc_corner Cmin \
-late_rc_corner Cmin
create_constraint_mode -name CON -sdc_file $sdc
create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
set_analysis_view -setup WC_VIEW -hold BC_VIEW
Flows/SKY130HD/mempool_tile/scripts/cadence/mmmc_setup.tcl
......@@ -4,8 +4,8 @@
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
create_rc_corner -name Cmax
create_rc_corner -name Cmin
create_rc_corner -name Cmax -qx_tech_file $qrc_max
create_rc_corner -name Cmin -qx_tech_file $qrc_min
create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
......
Flows/SKY130HD/mempool_tile/scripts/cadence/run deleted 100644 → 0
# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
#!/bin/tcsh
module unload innovus
module load innovus/21.1
mkdir -p log
innovus -64 -init run_invs.tcl -log log/run.log
Flows/SKY130HD/mempool_tile/scripts/cadence/run.sh 100644 → 100755
......@@ -6,6 +6,10 @@ module load genus/21.1
module unload innovus
module load innovus/21.1
#
# To run the Physical Synthesis (iSpatial) flow - flow2
export PHY_SYNTH=0
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
Flows/SKY130HD/mempool_tile/scripts/cadence/run_genus_hybrid.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_mmmc mmmc_iSpatial_setup.tcl
}
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
read_physical -lefs $lefs
}
# Target library
set link_library $list_lib
set target_library $list_lib
# set pathi
set_db hdl_flatten_complex_port true
set_db hdl_record_naming_style %s_%s
set_db auto_ungroup none
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
set_db library $list_lib
}
#################################################
# Load Design and Initialize
#################################################
set_db init_hdl_search_path $rtldir
source rtl_list.tcl
foreach rtl_file $rtl_all {
#read_hdl -sv $rtl_file
read_hdl -language sv -define TARGET_SYNTHESIS -define XPULPIMG=1 $rtl_file
}
elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
#read_sdc $sdc
source $sdc
}
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
###############################################
# Read DEF
###############################################
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_def $floorplan_def
check_floorplan -detailed
}
# keep hierarchy during synthesis
set_db auto_ungroup none
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
}
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_map -physical
} else {
syn_map
}
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_opt -spatial
} else {
syn_opt
}
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
}
exit
Flows/SKY130HD/mempool_tile/scripts/cadence/run_invs.tcl
......@@ -7,10 +7,10 @@ source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
set netlist "./syn_handoff/$DESIGN.v"
set sdc "./syn_handoff/$DESIGN.sdc"
set handoff_dir "./syn_handoff"
set site "unithd"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
set rptDir summaryReport/
set encDir enc/
......@@ -55,26 +55,20 @@ generateVias
createBasicPathGroups -expanded
## Generate the floorplan ##
#floorPlan -r 1.0 $util 10 10 10 10
defIn $floorplan_def
## Macro Placement ##
#redirect mp_config.tcl {source gen_mp_config.tcl}
#proto_design -constraints mp_config.tcl
addHaloToBlock -allMacro 5 5 5 5
place_design -concurrent_macros
refine_macro_place
saveDesign ${encDir}/${DESIGN}_floorplan.enc
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
}
## Creating Pin Blcokage for lower and upper pin layers ##
createPinBlkg -name Layer_1 -layer {met2 met3 met9} -edge 0
createPinBlkg -name side_top -edge 1
createPinBlkg -name side_right -edge 2
createPinBlkg -name side_bottom -edge 3
saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setDesignMode -topRoutingLayer 9
setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
......
Flows/SKY130HD/nvdla/def/NV_NVDLA_partition_c_fp_placed_macros.def 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/SKY130HD/nvdla/scripts/cadence/design_setup.tcl
......@@ -3,11 +3,14 @@
set DESIGN NV_NVDLA_partition_c
set sdc ../../constraints/${DESIGN}.sdc
set rtldir ../../../../../Testcases/nvdla/rtl/
# def file with die size and placed IO pins
set floorplan_def ../../def/${DESIGN}_fp.def
set rtl_path ../../../../../Testcases/nvdla/rtl/
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set floorplan_def ../../def/${DESIGN}_fp_placed_macros.def
} else {
set floorplan_def ../../def/${DESIGN}_fp.def
}
#
# Effort level during optimization in syn_generic -physical (or called generic) stage
......@@ -17,3 +20,7 @@ set GEN_EFF medium
# Effort level during optimization in syn_map -physical (or called mapping) stage
# possible values are : high, medium or low
set MAP_EFF high
#
set SITE "unithd"
set HALO_WIDTH 5
set TOP_ROUTING_LAYER 9
Flows/SKY130HD/nvdla/scripts/cadence/lib_setup.tcl
......@@ -34,3 +34,5 @@ set lefs "
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 130
set qrc_max "${qrcdir}/SKY130HD.tch"
set qrc_min "${qrcdir}/SKY130HD.tch"
Flows/SKY130HD/nvdla/scripts/cadence/mmmc_setup.tcl
......@@ -4,8 +4,8 @@
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
create_rc_corner -name Cmax
create_rc_corner -name Cmin
create_rc_corner -name Cmax -qx_tech_file $qrc_max
create_rc_corner -name Cmin -qx_tech_file $qrc_min
create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
......
Flows/SKY130HD/nvdla/scripts/cadence/rtl_list.tcl
......@@ -371,7 +371,7 @@ nv_ram_rwsthp_80x15.v
nv_ram_rwsthp_80x17.v
nv_ram_rwsthp_80x72.v
nv_ram_rwsthp_80x9.v
fakeram_256x64_dp.v
fakeram130_256x64_dp.v
-v NV_NVDLA_XXIF_libs.v
Flows/SKY130HD/nvdla/scripts/cadence/run.sh 100644 → 100755
......@@ -6,6 +6,10 @@ module load genus/21.1
module unload innovus
module load innovus/21.1
#
# To run the Physical Synthesis (iSpatial) flow - flow2
export PHY_SYNTH=0
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
Flows/SKY130HD/nvdla/scripts/cadence/run_genus_hybrid.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_mmmc mmmc_iSpatial_setup.tcl
}
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
read_physical -lefs $lefs
}
# Target library
set link_library $list_lib
set target_library $list_lib
# set pathi
set_db hdl_flatten_complex_port true
set_db hdl_record_naming_style %s_%s
set_db auto_ungroup none
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
set_db library $list_lib
}
#################################################
# Load Design and Initialize
#################################################
set_db init_hdl_search_path $rtldir
read_hdl -f rtl_list.tcl
#source rtl_list.tcl
#
#foreach rtl_file $rtl_all {
# read_hdl -sv $rtl_file
#}
elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
#read_sdc $sdc
source $sdc
}
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
###############################################
# Read DEF
###############################################
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_def $floorplan_def
check_floorplan -detailed
}
# keep hierarchy during synthesis
set_db auto_ungroup none
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
}
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_map -physical
} else {
syn_map
}
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_opt -spatial
} else {
syn_opt
}
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
}
exit
Flows/SKY130HD/nvdla/scripts/cadence/run_invs.tcl
......@@ -7,10 +7,10 @@ source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
set netlist "./syn_handoff/$DESIGN.v"
set sdc "./syn_handoff/$DESIGN.sdc"
set handoff_dir "./syn_handoff"
set site "unithd"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
set rptDir summaryReport/
set encDir enc/
......@@ -55,26 +55,20 @@ generateVias
createBasicPathGroups -expanded
## Generate the floorplan ##
#floorPlan -r 1.0 $util 10 10 10 10
defIn $floorplan_def
## Macro Placement ##
#redirect mp_config.tcl {source gen_mp_config.tcl}
#proto_design -constraints mp_config.tcl
addHaloToBlock -allMacro 5 5 5 5
place_design -concurrent_macros
refine_macro_place
saveDesign ${encDir}/${DESIGN}_floorplan.enc
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
}
## Creating Pin Blcokage for lower and upper pin layers ##
createPinBlkg -name Layer_1 -layer {met2 met3 met9} -edge 0
createPinBlkg -name side_top -edge 1
createPinBlkg -name side_right -edge 2
createPinBlkg -name side_bottom -edge 3
saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setDesignMode -topRoutingLayer 9
setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
......
Flows/util/genJobList.py
......@@ -5,7 +5,7 @@ import re
import time
testcases = ['ariane136', 'ariane133', 'mempool_tile', 'nvdla']
enablements = ['NanGate45', 'ASAP7']
enablements = ['NanGate45', 'ASAP7', 'SKY130HD']
flows = [1, 2]
job_file = "all_jobs"
......
Flows/util/gen_plc_from_pb.py 0 → 100644
'''
To run this scripts use the below command
python gen_plc_from_pb.py <netlist.pb.txt file>
This will generate the 'init.plc' as output
'''
import sys
import numpy as np
class pb_object:
def __init__(self, id):
self.name = None
self.node_id = id
self.height = 0
self.width = 0
self.weight = 0
self.x = -1
self.x_offset = 0
self.y = -1
self.y_offset = 0
self.m_name = None
self.pb_type = None
self.side = None
self.orientation = None
pb_file = sys.argv[1]
print(f'Protocol buffer file {pb_file}')
fp = open(pb_file, "r")
lines = fp.readlines()
key1 = ['"height"', '"weight"', '"width"', '"x"', '"x_offset"', '"y"', '"y_offset"']
key2 = ['"macro_name"', '"orientation"', '"side"', '"type"']
node_list = []
node_id = 0
key = ""
keys = set()
for line in lines:
words = line.split()
if words[0] == 'node':
node_list.append(pb_object(node_id))
node_id += 1
elif words[0] == 'name:':
node_list[-1].name = words[1]
elif words[0] == 'key:' :
key = words[1]
keys.add(key)
elif words[0] == 'placeholder:' :
if key == key2[0]:
node_list[-1].m_name = words[1]
elif key == key2[1]:
node_list[-1].orientation = words[1]
elif key == key2[2]:
node_list[-1].side = words[1]
elif key == key2[3]:
node_list[-1].pb_type = words[1]
elif words[0] == 'f:' :
if key == key1[0]:
node_list[-1].height = words[1]
elif key == key1[1]:
node_list[-1].weight = words[1]
elif key == key1[2]:
node_list[-1].width = words[1]
elif key == key1[3]:
node_list[-1].x = words[1]
elif key == key1[4]:
node_list[-1].x_offset = words[1]
elif key == key1[5]:
node_list[-1].y = words[1]
elif key == key1[6]:
node_list[-1].y_offset = words[1]
fp.close()
fp = open("init.plc", "w")
hard_macro_list = []
soft_macro_list = []
port_list = []
for node in node_list:
if node.pb_type == '"MACRO"':
hard_macro_list.append(node)
elif node.pb_type == '"macro"':
soft_macro_list.append(node)
elif node.pb_type == '"port"' or node.pb_type == '"PORT"':
port_list.append(node)
area1 = 0
area2 = 0
soft_macro_count = 0
hard_macro_count = 0
for node in port_list:
fp.write(f"{node.node_id} {np.round(float(node.x),3)} {np.round(float(node.y),3)} - 1\n")
for node in hard_macro_list:
fp.write(f"{node.node_id} {np.round(float(node.x),3)} {np.round(float(node.y),3)} N 0\n")
area1 += float(node.height)*float(node.width)
hard_macro_count += 1
for node in soft_macro_list:
fp.write(f"{node.node_id} {np.round(float(node.x),3)} {np.round(float(node.y),3)} N 0\n")
area2 += float(node.height)*float(node.width)
soft_macro_count += 1
area = area1 + area2
fp.write(f"# Area: {area}\n")
fp.write(f"# SOFT MACRO COUNT: {soft_macro_count}\n")
fp.write(f"# HARD MACRO COUNT: {hard_macro_count}\n")
fp.close()
\ No newline at end of file
README.md
......@@ -92,7 +92,7 @@ In the following table, we provide the status details of each testcase on each o
<td class="tg-0lax">N/A</td>
<td class="tg-0lax">N/A</td>
<td class="tg-0lax"><a href="https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/Flows/SKY130HD/ariane136">Link</a></td>
<td class="tg-0lax">N/A</td>
<td class="tg-0lax"><a href="https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/Flows/SKY130HD/ariane136">Link</a></td>
<td class="tg-0lax">N/A</td>
<td class="tg-0lax">N/A</td>
</tr>
......@@ -107,7 +107,7 @@ In the following table, we provide the status details of each testcase on each o
<td class="tg-0lax">N/A</td>
<td class="tg-0lax">N/A</td>
<td class="tg-0lax"><a href="https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/Flows/SKY130HD/ariane133">Link</a></td>
<td class="tg-0lax">N/A</td>
<td class="tg-0lax"><a href="https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/Flows/SKY130HD/ariane133">Link</a></td>
<td class="tg-0lax">N/A</td>
<td class="tg-0lax">N/A</td>
</tr>
......@@ -122,7 +122,7 @@ In the following table, we provide the status details of each testcase on each o
<td class="tg-0lax">N/A</td>
<td class="tg-0lax">N/A</td>
<td class="tg-0lax"><a href="https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/Flows/SKY130HD/mempool_tile">Link</a></td>
<td class="tg-0lax">N/A</td>
<td class="tg-0lax"><a href="https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/Flows/SKY130HD/mempool_tile">Link</a></td>
<td class="tg-0lax">N/A</td>
<td class="tg-0lax">N/A</td>
</tr>
......@@ -137,7 +137,7 @@ In the following table, we provide the status details of each testcase on each o
<td class="tg-0lax">N/A</td>
<td class="tg-0lax">N/A</td>
<td class="tg-0lax"><a href="https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/Flows/SKY130HD/nvdla">Link</a></td>
<td class="tg-0lax">N/A</td>
<td class="tg-0lax"><a href="https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/Flows/SKY130HD/nvdla">Link</a></td>
<td class="tg-0lax">N/A</td>
<td class="tg-0lax">N/A</td>
</tr>
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment