Merge branch 'flow_scripts' of github.com:TILOS-AI-Institute/MacroPlacement into flow_scripts

.gitignore

@@ -3,3 +3,9 @@ Flows/*/*/run-*
 Flows/job
 Flows/util/__pycache__
 CodeElements/*/*/__pycache__
+CodeElements/Plc_client/test/
+CodeElements/Plc_client/test/*/*
+CodeElements/Plc_client/plc_client_os.py
+CodeElements/Plc_client/__pycache__/*
+CodeElements/Plc_client/proto_reader.py
+CodeElements/Plc_client/plc_client.py

CodeElements/Gridding/src/gridding.py

@@ -2,7 +2,6 @@
 ### Input:  a list of macros (each macro has a width and a height)
 ### Output: best choice of n_rows and n_cols
 
-
 import os
 from math import floor
 from math import ceil
@@ -22,6 +21,7 @@ class Grid:
         self.y_       = y
         self.placed_  = False  # if there is macro placed on the center of this grid
         self.macros_id_ = [] # the id of macros intersecting with this grid
+        self.macro_area = 0.0
 
 # Check if there is an overlap with other placed macros
 def CheckOverlap(lx, ly, ux, uy, macro_box):
@@ -33,19 +33,30 @@ def CheckOverlap(lx, ly, ux, uy, macro_box):
             pass
         else:
             return True  # there is an overlap
-
     return False
 
 
+# Get overlap area
+def GetOverlapArea(box_a, box_b):
+    box_a_lx, box_a_ly, box_a_ux, box_a_uy = box_a
+    box_b_lx, box_b_ly, box_b_ux, box_b_uy = box_b
+    if (box_a_lx >= box_b_ux or box_a_ly >= box_b_uy or box_a_ux <= box_b_lx or box_a_uy <= box_b_ly):
+        return 0.0
+    else:
+        width = min(box_a_ux, box_b_ux) - max(box_a_lx, box_b_lx)
+        height = min(box_a_uy, box_b_uy) - max(box_a_ly, box_b_ly)
+        return width * height
 
 # Place macros one by one
 # n = num_cols
 def PlaceMacros(macro_map, grid_list, chip_width, chip_height, n):
     ### All the macro must be placed on the center of one grid
-
     #Initialize the position of macros
+    ver_sum = 0.0
+    ver_span_sum = 0.0
+    hor_sum = 0.0
+    hor_span_sum = 0.0
     macro_bbox = []
-
     # Place macro one by one
     for key, value in macro_map.items():
         width = value[0]
@@ -55,7 +66,6 @@ def PlaceMacros(macro_map, grid_list, chip_width, chip_height, n):
         for grid in grid_list:
             if (grid.placed_ == True):
                 continue # this grid has been occupied
-
             # if the macro is placed on this
             x = grid.x_
             y = grid.y_
@@ -67,12 +77,10 @@ def PlaceMacros(macro_map, grid_list, chip_width, chip_height, n):
             # check if the macro is within the outline
             if (ux > chip_width or uy > chip_height):
                 continue
-
             # check if there is an overlap with other macros
             if (CheckOverlap(lx, ly, ux, uy, macro_bbox) == True):
                 continue
 
-
             # place current macro on this grid
             grid.placed_ = True
             placed_flag  = True
@@ -91,22 +99,43 @@ def PlaceMacros(macro_map, grid_list, chip_width, chip_height, n):
                 for j in range(min_col_id, max_col_id + 1):
                     grid_id = i * n + j # n is the num_cols
                     grid_list[grid_id].macros_id_.append(macro_id)
+                    grid_box = [i * grid_width, j * grid_height, (i + 1) * grid_width, (j + 1) * grid_height]
+                    overlap_area = GetOverlapArea(grid_box, [lx, ly, ux, uy])
+                    grid_list[grid_id].macro_area += overlap_area
+
+            ver_sum += height
+            ver_span_sum += (max_row_id + 1 - min_row_id) * grid_height
+            hor_sum += width
+            hor_span_sum += (max_col_id + 1 - min_col_id) * grid_width
             break # stop search remaining candidates
 
         # cannot find a valid position for the macro
         if (placed_flag == False):
-            return False
+            return False, [0.0, 0.0, 0.0, 0.0]
 
-    return  True
+    return  True, [ver_sum, ver_span_sum, hor_sum, hor_span_sum]
 
 # Define the gridding function
 def Gridding(macro_width_list, macro_height_list,
-             chip_width, chip_height, tolerance = 0.1,
-             min_n_rows = 10, min_n_cols = 10,
-             max_n_rows = 100, max_n_cols = 100,
-             max_rows_times_cols = 3000,
-             min_rows_times_cols = 500,
-             max_aspect_ratio = 1.5):
+             chip_width, chip_height,
+             min_n_rows = 10,  min_n_cols = 10,
+             max_n_rows = 128, max_n_cols = 128,
+             min_num_grid_cells = 500,
+             max_num_grid_cells = 2500,
+             max_aspect_ratio = 1.5,
+             tolerance = 0.05):
+    """
+    Arguments:
+        macro_width_list, macro_height_list :  macro information
+        chip_width, chip_height : canvas size or core size of the chip
+        min_n_rows, min_n_cols : mininum number of rows/cols sweep
+        max_n_rows, max_n_rows : maximum number of rows/cols sweep
+        min_num_grid_cells, max_num_grid_cells :  mininum or maxinum grid cells
+        max_aspect_ratio : maximum aspect ratio of a grid cell (either w/h or h/w)
+        tolerance : tolerance to choose lower number of grids
+    Return:
+      the best number of rows and cols
+    """
     ### Sort all the macros in a non-decreasing order
     if (len(macro_width_list) != len(macro_height_list)):
       print("[Error] The macro information is wrong!!!")
@@ -116,30 +145,34 @@ def Gridding(macro_width_list, macro_height_list,
     macro_map = {  }
     for i in range(len(macro_width_list)):
         macro_map[i] = [macro_width_list[i], macro_height_list[i]]
-
     macro_map = dict(sorted(macro_map.items(), key=lambda item: item[1][0] * item[1][1], reverse = True))
-    macro_bbox = [] # (lx, ly, ux, uy) for each bounding box
 
+    ### Print information
     print("*"*80)
-    print("[INFO] Outline Information :  outline_width =", chip_width,  "  outline_height =", chip_height)
+    print("[INFO] Canvas Information :  canvas_width =", chip_width,  "canvas_height =", chip_height)
     print("\n")
     print("[INFO] Sorted Macro Information")
     for key, value in macro_map.items():
-        print("macro_" + str(key), "  macro_width =", round(value[0], 2), "  macro_height =", round(value[1], 2), "  macro_area =", round(value[0] * value[1], 2))
+        line = "macro_" + str(key) + " "
+        line += "macro_width = " + str(round(value[0], 2)) + " "
+        line += "macro_height = " + str(round(value[1], 2)) + " "
+        line += "macro_area = " + str(round(value[0] * value[1], 2))
+        print(line)
     print("\n")
 
+    ### Sweep the n_rows (m) and n_cols (n) in a row-based manner
+    macro_bbox = [] # (lx, ly, ux, uy) for each bounding box
     # we use m for max_n_rows and n for max_n_cols
     m_best = -1
     n_best = -1
-    best_cost = 2.0 # cost should be less than 2.0 based on definition
-    choice_map = {  }
-
-    for m in range(min_n_rows, max_n_rows + 1):
+    best_metric = -1.0
+    choice_map = {  }  # [m][n] : (ver_cost, hor_cost, empty_ratio)
+    for m in range(min_n_rows, max_n_rows):
         choice_map[m] = {  }
-        for n in range(min_n_cols, max_n_cols + 1):
-            if (m * n > max_rows_times_cols):
+        for n in range(min_n_cols, max_n_cols):
+            if (m * n > max_num_grid_cells):
                 break
-            if (m * n < min_rows_times_cols):
+            if (m * n < min_num_grid_cells):
                 continue
 
             ### Step1:  Divide the canvas into grids
@@ -148,10 +181,10 @@ def Gridding(macro_width_list, macro_height_list,
             grid_width  = chip_width / n
             if (grid_height / grid_width > max_aspect_ratio):
                 continue
-
             if (grid_width / grid_height > max_aspect_ratio):
                 continue
 
+            ### Step2:  Try to place macros on canvas
             grid_list = []
             for i in range(m):
                 for j in range(n):
@@ -160,24 +193,24 @@ def Gridding(macro_width_list, macro_height_list,
                     grid_id = len(grid_list)
                     grid_list.append(Grid(grid_id, grid_width, grid_height, x, y))
 
+            value = [0.0, 0.0, 0.0, 0.0]
             ### Place macros one by one
-            if (PlaceMacros(macro_map, grid_list, chip_width, chip_height, n) == False):
+            result_flag, value = PlaceMacros(macro_map, grid_list, chip_width, chip_height, n)
+            if (result_flag == False):
                 continue
             else:
-                ### Calculate the cost
-                total_grid_width = 0.0
-                total_grid_height = 0.0
+                ### compute the empty ratio
+                used_threshold = 1e-5
+                num_empty_grids = 0
                 for grid in grid_list:
-                    if (len(grid.macros_id_) > 0):
-                        total_grid_width += grid.width_
-                        total_grid_height += grid.height_
-
-                # calculate h_cost
-                cost = 1.0 - sum(macro_width_list) / total_grid_width
-                cost += 1.0 - sum(macro_height_list) / total_grid_height
-                choice_map[m][n] = cost
-                if (cost < best_cost):
-                    best_cost = cost
+                    if (grid.macro_area / (grid_width * grid_height) < used_threshold):
+                        num_empty_grids += 1
+                metric = 1.0 - value[0] / value[1]
+                metric += 1.0 - value[2] / value[3]
+                metric += num_empty_grids / len(grid_list)
+                choice_map[m][n] = metric
+                if (metric > best_metric):
+                    best_metric = metric
                     m_best = m
                     n_best = n
     m_opt = m_best
@@ -188,9 +221,9 @@ def Gridding(macro_width_list, macro_height_list,
     print("n_best = ", n_best)
     print("tolerance = ", tolerance)
     for [m, m_map] in choice_map.items():
-        for [n, cost] in m_map.items():
-            print("m = ", m , "  n = ", n, "  cost = ", cost)
-            if ((cost <= (1.0 + tolerance) * best_cost) and (m * n < num_grids_opt)):
+        for [n, metric] in m_map.items():
+            print("m = ", m , "  n = ", n, "  metric = ", metric)
+            if ((metric >= (1.0 - tolerance) * best_metric) and (m * n < num_grids_opt)):
                 m_opt = m
                 n_opt = n
                 num_grids_opt = m * n
@@ -201,7 +234,7 @@ def Gridding(macro_width_list, macro_height_list,
 
 class GriddingLefDefInterface:
     def __init__(self, src_dir, design, setup_file = "setup.tcl", tolerance = 0.05,
-                 halo_width = 5.0, min_n_rows = 10, min_n_cols = 10, max_n_rows = 128,
+                 halo_width = 0.0, min_n_rows = 10, min_n_cols = 10, max_n_rows = 128,
                  max_n_cols = 128, max_rows_times_cols = 2500,  min_rows_times_cols = 500,
                  max_aspect_ratio = 1.5):
         self.src_dir = src_dir
@@ -227,11 +260,11 @@ class GriddingLefDefInterface:
         self.GenerateHypergraph()
         self.ExtractInputs()
         self.m_opt, self.n_opt = Gridding(self.macro_width_list, self.macro_height_list,
-                                          self.chip_width, self.chip_height, self.tolerance,
+                                          self.chip_width, self.chip_height,
                                           self.min_n_rows, self.min_n_cols,
                                           self.max_n_rows, self.max_n_cols,
-                                          self.max_rows_times_cols, self.min_rows_times_cols,
-                                          self.max_aspect_ratio)
+                                          self.min_rows_times_cols, self.max_rows_times_cols,
+                                          self.max_aspect_ratio, self.tolerance)
 
     def GetNumRows(self):
         return self.m_opt
@@ -278,6 +311,7 @@ class GriddingLefDefInterface:
         f.close()
 
         items = content[0].split()
+        print(items)
         self.chip_width = float(items[2]) - float(items[0])
         self.chip_height = float(items[3]) - float(items[1])
 

CodeElements/Plc_client/README.md

@@ -9,7 +9,20 @@ curl 'https://raw.githubusercontent.com/google-research/circuit_training/main/ci
 sudo curl https://storage.googleapis.com/rl-infra-public/circuit-training/placement_cost/plc_wrapper_main \
   -o  /usr/local/bin/plc_wrapper_main
 # Run plc testbench
-python -m Plc_client.plc_client_os_test
+# python -m Plc_client.plc_client_os_test [-h] [--helpfull] --netlist NETLIST [--plc PLC] --width WIDTH --height HEIGHT --col COL --row ROW [--rpmh RPMH] [--rpmv RPMV] [--marh MARH] [--marv MARV] [--smooth SMOOTH]
+
+# Example
+python -m Plc_client.plc_client_os_test --netlist ./Plc_client/test/ariane/netlist.pb.txt\
+          --plc ./Plc_client/test/ariane/initial.plc\
+          --width 356.592\
+          --height 356.640\
+          --col 35\
+          --row 33\
+          --rpmh 10\
+          --rpmv 10\
+          --marh 5\
+          --marv 5\
+          --smooth 2
 ```
 
 ## HPWL Computation
@@ -27,15 +40,15 @@ $$
 HPWL(netlist) = \sum_{i}^{N_{netlist}} W_{i\_{source}} \cdot [max_{b\in i}(x_b) - min_{b\in i}(x_b) + max_{b\in i}(y_b) - min_{b\in i}(y_b)]
 $$
 
-## Density  Cost Computation
+## Density Cost Computation
 Density cost is computed from grid cells density.
 
 By default, any given input will have grid col/row set to 10/10 until user later defines in the .plc file.
 
-Grid cell density is represented as an 1D array where the length is set to be 
+Grid cell density is represented as an 1D array where the length is set to be the following:
 
 $$
-grid_\{col} \cdot grid_\{row}
+grid_{col} \cdot grid_{row}
 $$
 
 Each entry of this array represents the current occupied precentage within this cell.

CodeElements/Plc_client/placement_util_os.py

+# coding=utf-8
+# Copyright 2021 The Circuit Training Team Authors.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+"""A collection of non-prod utility functions for placement.
+
+All the dependencies in this files should be non-prod.
+"""
+
+import os
+import datetime
+import re
+import textwrap
+from typing import Dict, Iterator, List, Optional, Tuple, Any, Union
+
+from absl import logging
+logging.set_verbosity(logging.INFO)
+# from circuit_training.environment import plc_client
+from Plc_client import plc_client_os as plc_client
+import numpy as np
+
+# Internal gfile dependencies
+
+# done
+def nodes_of_types(plc: plc_client.PlacementCost,
+                   type_list: List[str]) -> Iterator[int]:
+  """Yields the index of a node of certain types."""
+  i = 0
+  while True:
+    node_type = plc.get_node_type(i)
+    if not node_type:
+      break
+    if node_type in type_list:
+      yield i
+    i += 1
+
+
+def get_node_xy_coordinates(
+    plc: plc_client.PlacementCost) -> Dict[int, Tuple[float, float]]:
+  """Returns all node x,y coordinates (canvas) in a dict."""
+  node_coords = dict()
+  for node_index in nodes_of_types(plc, ['MACRO', 'STDCELL', 'PORT']):
+    if plc.is_node_placed(node_index):
+      node_coords[node_index] = plc.get_node_location(node_index)
+  return node_coords
+
+
+def get_macro_orientations(plc: plc_client.PlacementCost) -> Dict[int, int]:
+  """Returns all macros' orientations in a dict."""
+  macro_orientations = dict()
+  for node_index in nodes_of_types(plc, ['MACRO']):
+    macro_orientations[node_index] = plc.get_macro_orientation(node_index)
+  return macro_orientations
+
+
+def restore_node_xy_coordinates(
+    plc: plc_client.PlacementCost,
+    node_coords: Dict[int, Tuple[float, float]]) -> None:
+  for node_index, coords in node_coords.items():
+    if not plc.is_node_fixed(node_index):
+      plc.update_node_coords(node_index, coords[0], coords[1])
+
+
+def restore_macro_orientations(plc: plc_client.PlacementCost,
+                               macro_orientations: Dict[int, int]) -> None:
+  for node_index, orientation in macro_orientations.items():
+    plc.update_macro_orientation(node_index, orientation)
+
+# 
+def extract_attribute_from_comments(attribute: str,
+                                    filenames: List[str]) -> Optional[str]:
+  """Parses the files' comments section, tries to extract the attribute.
+
+  Args:
+    attribute: attribute to look for (case sensetive).
+    filenames: List of protobuf file or a plc file.
+
+  Returns:
+    Attribute name string, or None if not found.
+  """
+  for filename in filenames:
+    if filename:
+      f = filename.split(',')[0]
+      if f:
+        with open(f, 'rt') as infile:
+          for line in infile:
+            if line.startswith('#'):
+              match = re.search(fr'{attribute} : ([-\w]+)', line)
+              if match:
+                return match.group(1)
+            else:
+              # Do not parse the rest of the file, since all the comments are at
+              # the top.
+              break
+  return None
+
+#done
+def get_blockages_from_comments(
+    filenames: Union[str, List[str]]) -> Optional[List[List[float]]]:
+  """Returns list of blockages if they exist in the file's comments section."""
+  for filename in filenames:
+    if not filename:
+      continue
+    blockages = []
+    # Read the first file if filename is comma separated list.
+    # Expected blockage info line format is:
+    # "# Blockage : <float> <float> <float> <float> <float>"
+    # where first four float numbers correspond to minx, miny, maxx, maxy of
+    # the rectangular region, the fifth one is the blockage rate. It's usually
+    # set to 1.
+    try:
+      with open(filename, 'rt') as infile:
+        for line in infile:
+          if line.startswith('# Blockage : '):
+            blockages.append([float(x) for x in line.split()[3:8]])
+          elif not line.startswith('#'):
+            break
+    except OSError:
+      logging.error('could not read file %s.', filename)
+    if blockages:
+      return blockages
+
+#done
+def extract_sizes_from_comments(
+    filenames: List[str]) -> Optional[Tuple[float, float, int, int]]:
+  """Parses the file's comments section, tries to extract canvas/grid sizes.
+
+  Args:
+    filenames: A list of netlist (.pb.txt) or placement (.plc) files.
+
+  Returns:
+    Tuple of canvas_width, canvas_height, grid_cols, grid_rows
+  """
+  for filename in filenames:
+    if not filename:
+      continue
+    canvas_width, canvas_height = None, None
+    grid_cols, grid_rows = None, None
+    with open(filename, 'rt') as infile:
+      for line in infile:
+        if line.startswith('#'):
+          fp_re = re.search(
+              r'FP bbox: \{([\d\.]+) ([\d\.]+)\} \{([\d\.]+) ([\d\.]+)\}', line)
+          if fp_re:
+            canvas_width = float(fp_re.group(3))
+            canvas_height = float(fp_re.group(4))
+            continue
+          plc_wh = re.search(r'Width : ([\d\.]+)  Height : ([\d\.]+)', line)
+          if plc_wh:
+            canvas_width = float(plc_wh.group(1))
+            canvas_height = float(plc_wh.group(2))
+            continue
+          plc_cr = re.search(r'Columns : ([\d]+)  Rows : ([\d]+)', line)
+          if plc_cr:
+            grid_cols = int(plc_cr.group(1))
+            grid_rows = int(plc_cr.group(2))
+        else:
+          # Do not parse the rest of the file, since all the comments are at the
+          # top.
+          break
+    if canvas_width and canvas_height and grid_cols and grid_rows:
+      return canvas_width, canvas_height, grid_cols, grid_rows
+
+
+def fix_port_coordinates(plc: plc_client.PlacementCost) -> None:
+  """Find all ports and fix their coordinates.
+
+  Args:
+    plc: the placement cost object.
+  """
+  for node in nodes_of_types(plc, ['PORT']):
+    # print("node to fix:", node)
+    plc.fix_node_coord(node)
+
+
+# The routing capacities are calculated based on the public information about
+# 7nm technology (https://en.wikichip.org/wiki/7_nm_lithography_process)
+# with an arbitary, yet reasonable, assumption of 18% of the tracks for
+# the power grids.
+def create_placement_cost(
+    netlist_file: str,
+    init_placement: Optional[str] = None,
+    overlap_threshold: float = 4e-3,
+    congestion_smooth_range: int = 2,
+    # TODO(b/211039937): Increase macro spacing to 3-5um, after matching the
+    # performance for Ariane.
+    macro_macro_x_spacing: float = 0.1,
+    macro_macro_y_spacing: float = 0.1,
+    boundary_check: bool = False,
+    horizontal_routes_per_micron: float = 70.33,
+    vertical_routes_per_micron: float = 74.51,
+    macro_horizontal_routing_allocation: float = 51.79,
+    macro_vertical_routing_allocation: float = 51.79,
+) -> plc_client.PlacementCost:
+    """Creates a placement_cost object.
+
+    Args:
+        netlist_file: Path to the netlist proto text file.
+        init_placement: Path to the inital placement .plc file.
+        overlap_threshold: Used for macro overlap detection.
+        congestion_smooth_range: Smoothing factor used for congestion estimation.
+        Congestion is distributed to this many neighboring columns/rows.'
+        macro_macro_x_spacing: Macro-to-macro x spacing in microns.
+        macro_macro_y_spacing: Macro-to-macro y spacing in microns.
+        boundary_check: Do a boundary check during node placement.
+        horizontal_routes_per_micron: Horizontal route capacity per micros.
+        vertical_routes_per_micron: Vertical route capacity per micros.
+        macro_horizontal_routing_allocation: Macro horizontal routing allocation.
+        macro_vertical_routing_allocation: Macro vertical routing allocation.
+
+    Returns:
+        A PlacementCost object.
+    """
+    if not netlist_file:
+        raise ValueError('netlist_file should be provided.')
+
+    block_name = extract_attribute_from_comments('Block',
+                                                [init_placement, netlist_file])
+    if not block_name:
+        logging.warning(
+            'block_name is not set. '
+            'Please add the block_name in:\n%s\nor in:\n%s', netlist_file,
+            init_placement)
+
+    plc = plc_client.PlacementCost(netlist_file, macro_macro_x_spacing,
+                                    macro_macro_y_spacing)
+
+    blockages = get_blockages_from_comments([netlist_file, init_placement])
+    if blockages:
+        print(blockages)
+        for blockage in blockages:
+            print(*blockage)
+            plc.create_blockage(*blockage)
+
+    sizes = extract_sizes_from_comments([netlist_file, init_placement])
+    print(sizes)
+    if sizes:
+        canvas_width, canvas_height, grid_cols, grid_rows = sizes
+        if canvas_width and canvas_height and grid_cols and grid_rows:
+            plc.set_canvas_size(canvas_width, canvas_height)
+            plc.set_placement_grid(grid_cols, grid_rows)
+
+    plc.set_project_name('circuit_training')
+    plc.set_block_name(block_name or 'unset_block')
+    plc.set_routes_per_micron(horizontal_routes_per_micron,
+                                vertical_routes_per_micron)
+    plc.set_macro_routing_allocation(macro_horizontal_routing_allocation,
+                                    macro_vertical_routing_allocation)
+    plc.set_congestion_smooth_range(congestion_smooth_range)
+    plc.set_overlap_threshold(overlap_threshold)
+    plc.set_canvas_boundary_check(boundary_check)
+    plc.make_soft_macros_square()
+    # exit(0)
+    # print(plc.get_soft_macros_count())
+    if init_placement:
+        plc.restore_placement(init_placement)
+        fix_port_coordinates(plc)
+
+    return plc
+
+
+def get_node_type_counts(plc: plc_client.PlacementCost) -> Dict[str, int]:
+  """Returns number of each type of nodes in the netlist.
+
+  Args:
+    plc: the placement cost object.
+
+  Returns:
+    Number of each type of node in a dict.
+  """
+  counts = {
+      'MACRO': 0,
+      'STDCELL': 0,
+      'PORT': 0,
+      'MACRO_PIN': 0,
+      'SOFT_MACRO': 0,
+      'HARD_MACRO': 0,
+      'SOFT_MACRO_PIN': 0,
+      'HARD_MACRO_PIN': 0
+  }
+
+  for node_index in nodes_of_types(plc,
+                                   ['MACRO', 'STDCELL', 'PORT', 'MACRO_PIN']):
+    node_type = plc.get_node_type(node_index)
+    counts[node_type] += 1
+    if node_type == 'MACRO':
+      if plc.is_node_soft_macro(node_index):
+        counts['SOFT_MACRO'] += 1
+      else:
+        counts['HARD_MACRO'] += 1
+    if node_type == 'MACRO_PIN':
+      ref_id = plc.get_ref_node_id(node_index)
+      if plc.is_node_soft_macro(ref_id):
+        counts['SOFT_MACRO_PIN'] += 1
+      else:
+        counts['HARD_MACRO_PIN'] += 1
+  return counts
+
+
+def make_blockage_text(plc: plc_client.PlacementCost) -> str:
+  ret = ''
+  for blockage in plc.get_blockages():
+    ret += 'Blockage : {}\n'.format(' '.join([str(b) for b in blockage]))
+  return ret
+
+
+def save_placement(plc: plc_client.PlacementCost,
+                   filename: str,
+                   user_comments: str = '') -> None:
+  """Saves the placement file with some information in the comments section."""
+  cols, rows = plc.get_grid_num_columns_rows()
+  width, height = plc.get_canvas_width_height()
+  hor_routes, ver_routes = plc.get_routes_per_micron()
+  hor_macro_alloc, ver_macro_alloc = plc.get_macro_routing_allocation()
+  smooth = plc.get_congestion_smooth_range()
+  info = textwrap.dedent("""\
+    Placement file for Circuit Training
+    Source input file(s) : {src_filename}
+    This file : {filename}
+    Date : {date}
+    Columns : {cols}  Rows : {rows}
+    Width : {width:.3f}  Height : {height:.3f}
+    Area : {area}
+    Wirelength : {wl:.3f}
+    Wirelength cost : {wlc:.4f}
+    Congestion cost : {cong:.4f}
+    Density cost : {density:.4f}
+    Project : {project}
+    Block : {block_name}
+    Routes per micron, hor : {hor_routes:.3f}  ver : {ver_routes:.3f}
+    Routes used by macros, hor : {hor_macro_alloc:.3f}  ver : {ver_macro_alloc:.3f}
+    Smoothing factor : {smooth}
+    Overlap threshold : {overlap_threshold}
+  """.format(
+      src_filename=plc.get_source_filename(),
+      filename=filename,
+      date=datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S'),
+      cols=cols,
+      rows=rows,
+      width=width,
+      height=height,
+      area=plc.get_area(),
+      wl=plc.get_wirelength(),
+      wlc=plc.get_cost(),
+      cong=plc.get_congestion_cost(),
+      density=plc.get_density_cost(),
+      project=plc.get_project_name(),
+      block_name=plc.get_block_name(),
+      hor_routes=hor_routes,
+      ver_routes=ver_routes,
+      hor_macro_alloc=hor_macro_alloc,
+      ver_macro_alloc=ver_macro_alloc,
+      smooth=smooth,
+      overlap_threshold=plc.get_overlap_threshold()))
+
+  info += '\n' + make_blockage_text(plc) + '\n'
+  info += '\nCounts of node types:\n'
+  node_type_counts = get_node_type_counts(plc)
+  for node_type in sorted(node_type_counts):
+    info += '{:<15} : {:>9}\n'.format(node_type + 's',
+                                      node_type_counts[node_type])
+  if user_comments:
+    info += '\nUser comments:\n' + user_comments + '\n'
+  info += '\nnode_index x y orientation fixed'
+  return plc.save_placement(filename, info)
+
+
+def fd_placement_schedule(plc: plc_client.PlacementCost,
+                          num_steps: Tuple[int, ...] = (100, 100, 100),
+                          io_factor: float = 1.0,
+                          move_distance_factors: Tuple[float,
+                                                       ...] = (1.0, 1.0, 1.0),
+                          attract_factor: Tuple[float,
+                                                ...] = (100.0, 1.0e-3, 1.0e-5),
+                          repel_factor: Tuple[float, ...] = (0.0, 1.0e6, 1.0e7),
+                          use_current_loc: bool = False,
+                          move_macros: bool = False) -> None:
+  """A placement schedule that uses force directed method.
+
+  Args:
+    plc: The plc object.
+    num_steps: Number of steps of the force-directed algorithm during each call.
+    io_factor: I/O attract factor.
+    move_distance_factors: Maximum distance relative to canvas size that a node
+      can move in a single step of the force-directed algorithm.
+    attract_factor: The spring constants between two connected nodes in the
+      force-directed algorithm. The FD algorithm will be called size of this
+      list times. Make sure that the size of fd_repel_factor has the same size.
+    repel_factor: The repellent factor for spreading the nodes to avoid
+      congestion in the force-directed algorithm.'
+    use_current_loc: If true, use the current location as the initial location.
+    move_macros: If true, also move the macros.
+  """
+  assert len(num_steps) == len(move_distance_factors)
+  assert len(num_steps) == len(repel_factor)
+  assert len(num_steps) == len(attract_factor)
+  canvas_size = max(plc.get_canvas_width_height())
+  max_move_distance = [
+      f * canvas_size / s for s, f in zip(num_steps, move_distance_factors)
+  ]
+  move_stdcells = True
+  log_scale_conns = False
+  use_sizes = False
+  plc.optimize_stdcells(use_current_loc, move_stdcells, move_macros,
+                        log_scale_conns, use_sizes, io_factor, num_steps,
+                        max_move_distance, attract_factor, repel_factor)
+
+
+def get_ordered_node_indices(mode: str,
+                             plc: plc_client.PlacementCost,
+                             exclude_fixed_nodes: bool = True) -> List[int]:
+  """Returns an ordering of node indices according to the specified mode.
+
+  Args:
+    mode: node ordering mode
+    plc: placement cost object
+    exclude_fixed_nodes: Whether fixed nodes should be excluded.
+
+  Returns:
+    Node indices sorted according to the mode.
+  """
+  macro_indices = plc.get_macro_indices()
+  hard_macro_indices = [
+      m for m in macro_indices if not plc.is_node_soft_macro(m)
+  ]
+  soft_macro_indices = [m for m in macro_indices if plc.is_node_soft_macro(m)]
+
+  def macro_area(idx):
+    w, h = plc.get_node_width_height(idx)
+    return w * h
+
+  if mode == 'descending_size_macro_first':
+    ordered_indices = (
+        sorted(hard_macro_indices, key=macro_area)[::-1] +
+        sorted(soft_macro_indices, key=macro_area)[::-1])
+  elif mode == 'random':
+    np.random.shuffle(macro_indices)
+    ordered_indices = macro_indices
+  elif mode == 'random_macro_first':
+    np.random.shuffle(hard_macro_indices)
+    ordered_indices = hard_macro_indices + soft_macro_indices
+  else:
+    raise ValueError('{} is an unsupported node placement mode.'.format(mode))
+
+  if exclude_fixed_nodes:
+    ordered_indices = [m for m in ordered_indices if not plc.is_node_fixed(m)]
+  return ordered_indices
+
+
+def extract_parameters_from_comments(
+    filename: str) -> Tuple[float, float, int, int]:
+  """Parses the file's comments section, tries to extract canvas/grid sizes.
+
+  Args:
+    filename: protobuf file or a plc file.
+
+  Returns:
+    Tuple of canvas_width, canvas_height, grid_cols, grid_rows
+  """
+  filename0 = filename.split(',')[0]
+  canvas_width, canvas_height = None, None
+  grid_cols, grid_rows = None, None
+  with open(filename0, 'r') as infile:
+    for line in infile:
+      if line.startswith('#'):
+        fp_re = re.search(
+            r'FP bbox: \{([\d\.]+) ([\d\.]+)\} \{([\d\.]+) ([\d\.]+)\}', line)
+        if fp_re:
+          canvas_width = float(fp_re.group(3))
+          canvas_height = float(fp_re.group(4))
+          continue
+        plc_wh = re.search(r'Width : ([\d\.]+)  Height : ([\d\.]+)', line)
+        if plc_wh:
+          canvas_width = float(plc_wh.group(1))
+          canvas_height = float(plc_wh.group(2))
+          continue
+        plc_cr = re.search(r'Columns : ([\d]+)  Rows : ([\d]+)', line)
+        if plc_cr:
+          grid_cols = int(plc_cr.group(1))
+          grid_rows = int(plc_cr.group(2))
+      else:
+        # Do not parse the rest of the file, since all the comments are at the
+        # top.
+        break
+  return canvas_width, canvas_height, grid_cols, grid_rows
+
+
+def get_routing_resources() -> Dict[str, float]:
+  """Currently we only use default parameter settings.
+
+  In the future, for specific project, the resources may need to be tuned.
+
+  Returns:
+    Routing resources.
+  """
+
+  return {
+      'horizontal_routes_per_micron': 57.031,
+      'vertical_routes_per_micron': 56.818,
+      'macro_horizontal_routing_allocation': 39.583,
+      'macro_vertical_routing_allocation': 30.303,
+  }
+
+
+def nodes_of_types(plc: plc_client.PlacementCost, type_list: List[str]):
+  """Yields the index of a node of certain types."""
+  i = 0
+  while True:
+    node_type = plc.get_node_type(i)
+    if not node_type:
+      break
+    if node_type in type_list:
+      yield i
+    i += 1
+
+
+def num_nodes_of_type(plc, node_type):
+  """Returns number of node of a particular type."""
+  count = 0
+  for _ in nodes_of_types(plc, [node_type]):
+    count += 1
+  return count
+
+
+def extract_blockages_from_tcl(filename: str,
+                               block_name: str,
+                               canvas_width: float,
+                               canvas_height: float,
+                               is_rectilinear: bool = False):
+  """Reads blockage information from a given tcl file."""
+  # Assumptions: project is viperlite or viperfish.
+  # This is not a TCL parser, it just reads in a line of the format:
+  # dict set ::clockstrap <block name> <blockage index> <corner> <float number>
+  # corner is expected to be one of lly, ury.
+  blockage_info = dict()
+  try:
+    with open(filename, 'r') as infile:
+      for line in infile:
+        if line.startswith('dict set ::clockstrap '):
+          block, index, corner, value = line.split()[3:7]
+          if block != block_name:
+            continue
+          blockage_info[corner + index] = float(value)
+  except gfile.FileError:
+    logging.error('could not read file %s', filename)
+    return []
+  blockages = []
+
+  if is_rectilinear:
+    # Use blockage to model rectilinear floorplan.
+    index = 0
+    while ('llx' + str(index) in blockage_info and
+           'lly' + str(index) in blockage_info and
+           'urx' + str(index) in blockage_info and
+           'ury' + str(index) in blockage_info):
+      minx = blockage_info['llx' + str(index)]
+      maxx = blockage_info['urx' + str(index)]
+      miny = blockage_info['lly' + str(index)]
+      maxy = blockage_info['ury' + str(index)]
+      if minx < 0:
+        raise ValueError(f'Illegal blockage at index {index}: llx {minx} < 0')
+      if maxx > canvas_width:
+        raise ValueError(
+            f'Illegal blockage at index {index}: urx {maxx} > canvas '
+            f'width {canvas_width}')
+      if miny < 0:
+        raise ValueError(f'Illegal blockage at index {index}: lly {miny} < 0')
+      if maxy > canvas_height:
+        raise ValueError(
+            f'Illegal blockage at index {index}: ury {maxy} > canvas '
+            f'height {canvas_height}')
+      blockages.append([minx, miny, maxx, maxy, 1])
+      index += 1
+  else:
+    # Fully horizontal or vertical blockage.
+    # Horizontal straps.
+    index = 0
+    while 'lly' + str(index) in blockage_info and 'ury' + str(
+        index) in blockage_info:
+      minx = 0.0
+      maxx = canvas_width
+      miny = blockage_info['lly' + str(index)]
+      maxy = blockage_info['ury' + str(index)]
+      blockages.append([minx, miny, maxx, maxy, 1])
+      index += 1
+    # We don't have any vertical straps, now. Should we still support it?
+    # Vertical straps.
+    index = 0
+    while 'llx' + str(index) in blockage_info and 'urx' + str(
+        index) in blockage_info:
+      minx = blockage_info['llx' + str(index)]
+      maxx = blockage_info['urx' + str(index)]
+      miny = 0.0
+      maxy = canvas_height
+      blockages.append([minx, miny, maxx, maxy, 1])
+      index += 1
+  return blockages
+
+
+def get_ascii_picture(vect: List[Any],
+                      cols: int,
+                      rows: int,
+                      scale: float = 10) -> str:
+  """Returns an ascii picture for the input as a human readable matrix."""
+  ret_str = '   '
+  for c in range(cols):
+    ret_str += '|' + str(int(c / 10) % 10)
+  ret_str += '|\n   '
+  for c in range(cols):
+    ret_str += '|' + str(c % 10)
+  ret_str += '|\n   -' + '-' * 2 * cols + '\n'
+  for r in range(rows - 1, -1, -1):
+    ret_str += format('%3d' % r)
+    for c in range(cols):
+      mindex = r * cols + c
+      val = int(scale * vect[mindex])
+      if val > scale:
+        ret_str += '|!'
+      elif val == scale:
+        ret_str += '|#'
+      elif val == 0:
+        ret_str += '| '
+      else:
+        ret_str += '|' + str(val)
+    ret_str += '|\n'
+  ret_str += '   -' + '-' * 2 * cols + '\n'
+  return ret_str
+
+
+def get_hard_macro_density_map(plc: plc_client.PlacementCost) -> List[float]:
+  """Returns the placement density map for hard macros only."""
+  # Unplaces all standard cells and soft macros, so that grid cell density
+  # only contains hard macros.
+  placements_to_restore = dict()
+  for node_index in nodes_of_types(plc, ['STDCELL']):
+    if plc.is_node_placed(node_index):
+      placements_to_restore[node_index] = plc.get_node_location(node_index)
+      plc.unplace_node(node_index)
+  for node_index in nodes_of_types(plc, ['MACRO']):
+    if plc.is_node_soft_macro(node_index) and plc.is_node_placed(node_index):
+      placements_to_restore[node_index] = plc.get_node_location(node_index)
+      plc.unplace_node(node_index)
+  hard_macro_density = plc.get_grid_cells_density()
+  check_boundary = plc.get_canvas_boundary_check()
+  # Restores placements, but original placement may be illegal (outside canvas
+  # area), ignore those cases.
+  plc.set_canvas_boundary_check(False)
+  for node_index, coords in placements_to_restore.items():
+    plc.update_node_coords(node_index, coords[0], coords[1])
+  plc.set_canvas_boundary_check(check_boundary)
+  return hard_macro_density
+
+
+def save_placement_with_info(plc: plc_client.PlacementCost,
+                             filename: str,
+                             user_comments: str = '') -> None:
+  """Saves the placement file with some information in the comments section."""
+  cols, rows = plc.get_grid_num_columns_rows()
+  width, height = plc.get_canvas_width_height()
+  hor_routes, ver_routes = plc.get_routes_per_micron()
+  hor_macro_alloc, ver_macro_alloc = plc.get_macro_routing_allocation()
+  smooth = plc.get_congestion_smooth_range()
+  init_placement_config = ''
+  # Do not change the format of the comments section before updating
+  # extract_parameters_from_comments and extract_netlist_file_from_comments
+  # functions.
+  info = textwrap.dedent("""\
+    Placement file for Circuit Training
+    Source input file(s) : {src_filename}
+    This file : {filename}
+    Original initial placement : {init_placement_config}
+    Date : {date}
+    Columns : {cols}  Rows : {rows}
+    Width : {width:.3f}  Height : {height:.3f}
+    Area (stdcell+macros) : {area}
+    Wirelength : {wl:.3f}
+    Wirelength cost : {wlc:.4f}
+    Congestion cost : {cong:.4f}
+    Density cost : {density:.4f}
+    Fake net cost : {fake_net:.4f}
+    90% Congestion metric: {cong90}
+    Project : {project}
+    Block : {block_name}
+    Routes per micron, hor : {hor_routes:.3f}  ver : {ver_routes:.3f}
+    Routes used by macros, hor : {hor_macro_alloc:.3f}  ver : {ver_macro_alloc:.3f}
+    Smoothing factor : {smooth}
+    Use incremental cost : {incr_cost}
+
+    To view this file (most options are default):
+    viewer_binary\
+    --netlist_file {src_filename}\
+    --canvas_width {width} --canvas_height {height}\
+    --grid_cols {cols} --grid_rows={rows}\
+    --init_placement {filename}\
+    --project {project}\
+    --block_name {block_name}\
+    --congestion_smooth_range {smooth}\
+    --overlap_threshold {overlap_threshold}\
+    --noboundary_check
+    or you can simply run:
+    viewer_binary\
+    --init_placement {filename}
+  """.format(
+      src_filename=plc.get_source_filename(),
+      filename=filename,
+      init_placement_config=init_placement_config,
+      date=datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S'),
+      cols=cols,
+      rows=rows,
+      width=width,
+      height=height,
+      area=plc.get_area(),
+      wl=plc.get_wirelength(),
+      wlc=plc.get_cost(),
+      cong=plc.get_congestion_cost(),
+      cong90=plc.get_congestion_cost_threshold(0.9),
+      density=plc.get_density_cost(),
+      fake_net=plc.get_fake_net_cost(),
+      project=plc.get_project_name(),
+      block_name=plc.get_block_name(),
+      hor_routes=hor_routes,
+      ver_routes=ver_routes,
+      hor_macro_alloc=hor_macro_alloc,
+      ver_macro_alloc=ver_macro_alloc,
+      smooth=smooth,
+      incr_cost=plc.get_use_incremental_cost(),
+      overlap_threshold=plc.get_overlap_threshold()))
+
+  info += '\n' + make_blockage_text(plc) + '\n'
+  info += '\nCounts of node types:\n'
+  node_type_counts = get_node_type_counts(plc)
+  for node_type in sorted(node_type_counts):
+    info += '{:<15} : {:>9}\n'.format(node_type + 's',
+                                      node_type_counts[node_type])
+  info += '\nHard Macro Placements:\n'
+  info += get_ascii_picture(get_hard_macro_density_map(plc), cols, rows)
+  info += '\nOverall Placement Density:\n'
+  info += get_ascii_picture(plc.get_grid_cells_density(), cols, rows)
+  info += '\nHorizontal Routing Congestion:\n'
+  info += get_ascii_picture(plc.get_horizontal_routing_congestion(), cols, rows)
+  info += '\nVertical Routing Congestion:\n'
+  info += get_ascii_picture(plc.get_vertical_routing_congestion(), cols, rows)
+  if user_comments:
+    info += '\nUser comments:\n' + user_comments + '\n'
+  info += '\nnode_index x y orientation fixed'
+  return plc.save_placement(filename, info)
+
+
+def create_placement_cost_using_common_arguments(
+    netlist_file: str,
+    init_placement: Optional[str] = None,
+    canvas_width: Optional[float] = None,
+    canvas_height: Optional[float] = None,
+    grid_cols: Optional[int] = None,
+    grid_rows: Optional[int] = None,
+    project: Optional[str] = None,
+    block_name: Optional[str] = None,
+    congestion_smooth_range: Optional[int] = None,
+    overlap_threshold: Optional[float] = None,
+    use_incremental_cost: Optional[bool] = None,
+    boundary_check: Optional[bool] = None,
+    blockages: Optional[List[List[float]]] = None,
+    fix_ports: Optional[bool] = True) -> plc_client.PlacementCost:
+  """Creates a placement_cost object using the common arguments."""
+  if not project:
+    logging.info('Reading project name from file.')
+    project = extract_attribute_from_comments('Project',
+                                              [init_placement, netlist_file])
+  if init_placement and not block_name:
+    logging.info('Reading block name from file.')
+    block_name = extract_attribute_from_comments('Block',
+                                                 [init_placement, netlist_file])
+  if not block_name:
+    logging.warning('block_name is not set. Please add the block_name in:\n%s',
+                    init_placement)
+
+  plc = plc_client.PlacementCost(netlist_file)
+  # Create blockages.
+  if blockages is None:
+    # Try to read blockages from input files. To avoid file I/O, pass blockages,
+    # or an empty list if there are none.
+    logging.info('Reading blockages from file.')
+    for filename in [netlist_file, init_placement]:
+      if filename is None:
+        continue
+      blockages = get_blockages_from_comments([filename])
+      # Only read blockages from one file.
+      if blockages:
+        break
+  if blockages:
+    for blockage in blockages:
+      plc.create_blockage(*blockage)
+  # Give precedence to command line parameters for canvas/grid sizes.
+  canvas_size_set = False
+  if canvas_width and canvas_height:
+    plc.set_canvas_size(canvas_width, canvas_height)
+    canvas_size_set = True
+  grid_size_set = False
+  if grid_cols and grid_rows:
+    grid_size_set = True
+    plc.set_placement_grid(grid_cols, grid_rows)
+  # Extract and set canvas, grid sizes if they are not already set.
+  if not canvas_size_set or not grid_size_set:
+    logging.info('Reading netlist sizes from file.')
+    for filename in [netlist_file, init_placement]:
+      if filename is None:
+        continue
+      sizes = extract_parameters_from_comments(filename)
+      canvas_width, canvas_height, grid_cols, grid_rows = sizes
+      if canvas_width and canvas_height and not canvas_size_set:
+        plc.set_canvas_size(canvas_width, canvas_height)
+      if grid_cols and grid_rows and not grid_size_set:
+        plc.set_placement_grid(grid_cols, grid_rows)
+
+  routing_resources = get_routing_resources()
+  plc.set_project_name(project or 'unset_project')
+  plc.set_block_name(block_name or 'unset_block')
+  plc.set_routes_per_micron(routing_resources['horizontal_routes_per_micron'],
+                            routing_resources['vertical_routes_per_micron'])
+  plc.set_macro_routing_allocation(
+      routing_resources['macro_horizontal_routing_allocation'],
+      routing_resources['macro_vertical_routing_allocation'])
+  plc.set_congestion_smooth_range(congestion_smooth_range)
+  plc.set_overlap_threshold(overlap_threshold)
+  plc.set_canvas_boundary_check(boundary_check)
+
+  # Set macros to initial locations.
+  if init_placement:
+    logging.info('Reading init_placement from file %s', init_placement)
+    # I/O is forbidden in forked child processes.
+    # Reads init placement from file only if init_locations are not provided.
+    plc.restore_placement(init_placement)
+
+  if fix_ports:
+    fix_port_coordinates(plc)
+  plc.set_use_incremental_cost(use_incremental_cost)
+
+  return plc
+
+
+def get_node_locations(plc: plc_client.PlacementCost) -> Dict[int, int]:
+  """Returns all node grid locations (macros and stdcells) in a dict."""
+  node_locations = dict()
+  for i in nodes_of_types(plc, ['MACRO', 'STDCELL']):
+    node_locations[i] = plc.get_grid_cell_of_node(i)
+  return node_locations
+
+
+def get_node_ordering_by_size(plc: plc_client.PlacementCost) -> List[int]:
+  """Returns the list of nodes (macros and stdcells) ordered by area."""
+  node_areas = dict()
+  for i in nodes_of_types(plc, ['MACRO', 'STDCELL']):
+    if plc.is_node_fixed(i):
+      continue
+    w, h = plc.get_node_width_height(i)
+    node_areas[i] = w * h
+  return sorted(node_areas, key=node_areas.get, reverse=True)
+
+
+def grid_locations_near(plc: plc_client.PlacementCost,
+                        start_grid_index: int) -> Iterator[int]:
+  """Yields node indices closest to the start_grid_index."""
+  # Starting from the start_grid_index, it goes around the area from closest
+  # (manhattan distance) to the farthest. For example, if the start grid index
+  # is at 0, the order of the next grid cells will be like:
+  #          24
+  #       22 12 23
+  #    20 10  4 11 21
+  # 18  8  2  0  3  9 19
+  #    16  6  1  7 17
+  #       14  5 15
+  #          13
+  cols, rows = plc.get_grid_num_columns_rows()
+  start_col, start_row = start_grid_index % cols, int(start_grid_index / cols)
+  # TODO(mustafay): This may be improved, but it's not crucial now.
+  for distance in range(cols + rows):
+    for row_offset in range(-distance, distance + 1):
+      for col_offset in range(-distance, distance + 1):
+        if abs(row_offset) + abs(col_offset) != distance:
+          continue
+        new_col = start_col + col_offset
+        new_row = start_row + row_offset
+        if new_col < 0 or new_row < 0 or new_col >= cols or new_row >= rows:
+          continue
+        yield int(new_col + new_row * cols)
+
+
+def place_near(plc: plc_client.PlacementCost, node_index: int,
+               location: int) -> bool:
+  """Places a node (legally) closest to the given location.
+
+  Args:
+    plc: placement_cost object.
+    node_index: index of a node.
+    location: target grid cell location. (row * num_cols + num_cols)
+
+  Returns:
+    True on success, False if this node was not placed on any grid legally.
+  """
+  for loc in grid_locations_near(plc, location):
+    if plc.can_place_node(node_index, loc):
+      plc.place_node(node_index, loc)
+      return True
+  return False
+
+
+def disconnect_high_fanout_nets(plc: plc_client.PlacementCost,
+                                max_allowed_fanouts: int = 500) -> None:
+  high_fanout_nets = []
+  for i in nodes_of_types(plc, ['PORT', 'STDCELL', 'MACRO_PIN']):
+    num_fanouts = len(plc.get_fan_outs_of_node(i))
+    if num_fanouts > max_allowed_fanouts:
+      print('Disconnecting node: {} with {} fanouts.'.format(
+          plc.get_node_name(i), num_fanouts))
+      high_fanout_nets.append(i)
+  plc.disconnect_nets(high_fanout_nets)
+
+
+def legalize_placement(plc: plc_client.PlacementCost) -> bool:
+	"""Places the nodes to legal positions snapping to grid cells."""
+	# Unplace all except i/o's.
+	fix_port_coordinates(plc)
+	# First save each node's locations on the grid.
+	# Note that the orientations are not changed by this utility, we do not
+	# need saving/restoring existing orientations.
+	node_locations = get_node_locations(plc)
+	previous_xy_coords = get_node_xy_coordinates(plc)
+	total_macro_displacement = 0
+	total_macros = 0
+	plc.unplace_all_nodes()
+	# Starting with the biggest, place them trying to be as close as possible
+	# to the original position.
+	ordered_nodes = get_node_ordering_by_size(plc)
+	for node in ordered_nodes:
+		if not place_near(plc, node, node_locations[node]):
+			print('Could not place node')
+			return False
+		if node in previous_xy_coords and not plc.is_node_soft_macro(node):
+			x, y = plc.get_node_location(node)
+			px, py = previous_xy_coords[node]
+			print('x/y displacement: dx = {}, dy = {}, macro: {}'.format(
+				x - px, y - py, plc.get_node_name(node)))
+			total_macro_displacement += abs(x - px) + abs(y - py)
+			total_macros += 1
+	print('Total macro displacement: {}, avg: {}'.format(
+		total_macro_displacement, total_macro_displacement / total_macros))
+	return True
+
+def main():
+    """ Run Command:
+    python3 -m Plc_client.placement_util_os
+    """
+    test_netlist_dir = './Plc_client/test/'+'ariane'
+    netlist_file = os.path.join(test_netlist_dir,'netlist.pb.txt')
+    init_placement = os.path.join(test_netlist_dir,'initial.plc')
+    plc = create_placement_cost(netlist_file=netlist_file, init_placement=init_placement)
+    plc = create_placement_cost_using_common_arguments(netlist_file=netlist_file, init_placement=init_placement, 
+          grid_cols=10, grid_rows=10, congestion_smooth_range=2.0, overlap_threshold=0.004, use_incremental_cost=False)
+    # plc.nodes_of_types()
+
+if __name__ == '__main__':
+	main()
\ No newline at end of file

CodeElements/Plc_client/plc_client_os.py

@@ -9,6 +9,24 @@ from collections import namedtuple
 import matplotlib.pyplot as plt
 from matplotlib.patches import Rectangle
 import numpy as np
+import traceback, sys
+
+"""plc_client_os docstrings.
+
+Open-sourced effort for plc_client and Google's API, plc_wrapper_main. This module
+is used to initialize a PlacementCost object that computes the meta-information and
+proxy cost function for RL agent's reward signal at the end of each placement.
+
+Example:
+    For testing, please refer to plc_client_os_test.py for more information.
+
+Todo:
+    * Add Documentation
+    * Clean up
+    * location information update not correctly after restore placement
+    * test if cell < 5, congestion cost computation
+
+"""
 
 Block = namedtuple('Block', 'x_max y_max x_min y_min')
 
@@ -25,6 +43,13 @@ class PlacementCost(object):
         self.macro_macro_x_spacing = macro_macro_x_spacing
         self.macro_macro_y_spacing = macro_macro_y_spacing
 
+        # Update flags
+        self.FLAG_UPDATE_WIRELENGTH = True
+        self.FLAG_UPDATE_DENSITY = True
+        self.FLAG_UPDATE_CONGESTION = True
+        self.FLAG_UPDATE_MACRO_ADJ = True
+        self.FLAG_UPDATE_MACRO_AND_CLUSTERED_PORT_ADJ = True
+
         # Check netlist existance
         assert os.path.isfile(self.netlist_file)
 
@@ -38,9 +63,9 @@ class PlacementCost(object):
         self.overlap_thres = 0.0
         self.hrouting_alloc = 0.0
         self.vrouting_alloc = 0.0
-
         self.macro_horizontal_routing_allocation = 0.0
         self.macro_vertical_routing_allocation = 0.0
+        self.canvas_boundary_check = True
 
         # net information
         self.net_cnt = 0
@@ -60,6 +85,11 @@ class PlacementCost(object):
         # macro to pins look-up table: [MACRO_NAME] => [PIN_NAME]
         self.hard_macros_to_inpins = {}
         self.soft_macros_to_inpins = {}
+
+        # unknown
+        self.use_incremental_cost = False
+        # blockage
+        self.blockages = []
         # read netlist
         self.__read_protobuf()
 
@@ -78,16 +108,16 @@ class PlacementCost(object):
         # initial grid mask
         self.global_node_mask = [0] * self.grid_col * self.grid_row
         # store module/component count
-        self.port_cnt = len(self.port_indices)
+        self.ports_cnt = len(self.port_indices)
         self.hard_macro_cnt = len(self.hard_macro_indices)
-        self.hard_macro_pin_cnt = len(self.hard_macro_pin_indices)
-        self.soft_macro_cnt = len(self.soft_macro_indices)
-        self.soft_macro_pin_cnt = len(self.soft_macro_pin_indices)
-        self.module_cnt = self.hard_macro_cnt + self.soft_macro_cnt + self.port_cnt
+        self.hard_macro_pins_cnt = len(self.hard_macro_pin_indices)
+        self.soft_macros_cnt = len(self.soft_macro_indices)
+        self.soft_macro_pins_cnt = len(self.soft_macro_pin_indices)
+        self.module_cnt = self.hard_macro_cnt + self.soft_macros_cnt + self.ports_cnt
         # assert module and pin count are correct
         assert (len(self.modules)) == self.module_cnt
         assert (len(self.modules_w_pins) - \
-            self.hard_macro_pin_cnt - self.soft_macro_pin_cnt) \
+            self.hard_macro_pins_cnt - self.soft_macro_pins_cnt) \
                 == self.module_cnt
 
     def __peek(self, f:io.TextIOWrapper):
@@ -185,12 +215,12 @@ class PlacementCost(object):
                         try:
                             assert 'x' in attr_dict.keys()
                         except AssertionError:
-                            logging.warning('x is not defined')
+                            logging.warning('[NETLIST PARSER ERROR] x is not defined')
 
                         try:
                             assert 'y' in attr_dict.keys()
                         except AssertionError:
-                            logging.warning('y is not defined')
+                            logging.warning('[NETLIST PARSER ERROR] y is not defined')
 
                         soft_macro = self.SoftMacro(name=node_name, width=attr_dict['width'][1],
                                                     height = attr_dict['height'][1],
@@ -317,30 +347,213 @@ class PlacementCost(object):
         # mapping connection degree to each macros
         self.__update_connection()
 
-    def __read_plc(self):
+    def __read_plc(self, plc_pth: str):
         """
         Plc file Parser
         """
-        with open(self.init_plc) as fp:
-            line = fp.readline()
-
-            while line:
-                # skip comments
-                if re.search(r"\S", line)[0] == '#':
-                    # IMPORTANT: Advance pt
-                    line = fp.readline()
-                    continue
-
-                # words itemize into list
-                line_item = re.findall(r'[0-9A-Za-z\.\-]+', line)
-
-                # skip empty lines
-                if len(line_item) == 0:
-                    # IMPORTANT: Advance pt
-                    line = fp.readline()
-                    continue
-
-            line = fp.readline()
+        # meta information
+        _columns = 0
+        _rows = 0
+        _width = 0.0
+        _height = 0.0
+        _area = 0.0
+        _block = None
+        _routes_per_micron_hor = 0.0
+        _routes_per_micron_ver = 0.0
+        _routes_used_by_macros_hor = 0.0
+        _routes_used_by_macros_ver = 0.0
+        _smoothing_factor = 0
+        _overlap_threshold = 0.0
+
+        # node information
+        _hard_macros_cnt = 0
+        _hard_macro_pins_cnt = 0
+        _macros_cnt = 0
+        _macro_pin_cnt = 0
+        _ports_cnt = 0
+        _soft_macros_cnt = 0
+        _soft_macro_pins_cnt = 0
+        _stdcells_cnt = 0
+
+        # node placement
+        _node_plc = {}
+
+        for cnt, line in enumerate(open(plc_pth, 'r')):
+            line_item = re.findall(r'[0-9A-Za-z\.\-]+', line)
+
+            # skip empty lines
+            if len(line_item) == 0:
+                continue
+
+            if 'Columns' in line_item and 'Rows' in line_item:
+                # Columns and Rows should be defined on the same one-line
+                _columns = int(line_item[1])
+                _rows = int(line_item[3])
+            elif "Width" in line_item and "Height" in line_item:
+                # Width and Height should be defined on the same one-line
+                _width = float(line_item[1])
+                _height = float(line_item[3])
+            elif "Area" in line_item:
+                # Total core area of modules
+                _area = float(line_item[1])
+            elif "Block" in line_item:
+                # The block name of the testcase
+                _block = str(line_item[1])
+            elif all(it in line_item for it in\
+                ['Routes', 'per', 'micron', 'hor', 'ver']):
+                # For routing congestion computation
+                _routes_per_micron_hor = float(line_item[4])
+                _routes_per_micron_ver = float(line_item[6])
+            elif all(it in line_item for it in\
+                    ['Routes', 'used', 'by', 'macros', 'hor', 'ver']):
+                # For MACRO congestion computation
+                _routes_used_by_macros_hor = float(line_item[5])
+                _routes_used_by_macros_ver = float(line_item[7])
+            elif all(it in line_item for it in ['Smoothing', 'factor']):
+                # smoothing factor for routing congestion
+                _smoothing_factor = int(line_item[2])
+            elif all(it in line_item for it in ['Overlap', 'threshold']):
+                # overlap
+                _overlap_threshold = float(line_item[2])
+            elif all(it in line_item for it in ['HARD', 'MACROs'])\
+                and len(line_item) == 3:
+                _hard_macros_cnt = int(line_item[2])
+            elif all(it in line_item for it in ['HARD', 'MACRO', 'PINs'])\
+                and len(line_item) == 4:
+                _hard_macro_pins_cnt = int(line_item[3])
+            elif all(it in line_item for it in ['PORTs'])\
+                and len(line_item) == 2:
+                _ports_cnt = int(line_item[1])
+            elif all(it in line_item for it in ['SOFT', 'MACROs'])\
+                and len(line_item) == 3:
+                _soft_macros_cnt = int(line_item[2])
+            elif all(it in line_item for it in ['SOFT', 'MACRO', 'PINs'])\
+                and len(line_item) == 4:
+                _soft_macro_pins_cnt = int(line_item[3])
+            elif all(it in line_item for it in ['STDCELLs'])\
+                and len(line_item) == 2:
+                _stdcells_cnt = int(line_item[1])
+            elif all(it in line_item for it in ['MACROs'])\
+                and len(line_item) == 2:
+                _macros_cnt = int(line_item[1])
+            elif all(re.match(r'[0-9NEWS\.\-]+', it) for it in line_item)\
+                and len(line_item) == 5:
+                # [node_index] [x] [y] [orientation] [fixed]
+                _node_plc[int(line_item[0])] = line_item[1:]
+        
+        # return as dictionary
+        info_dict = {   "columns":_columns, 
+                        "rows":_rows,
+                        "width":_width,
+                        "height":_height,
+                        "area":_area,
+                        "block":_block,
+                        "routes_per_micron_hor":_routes_per_micron_hor,
+                        "routes_per_micron_ver":_routes_per_micron_ver,
+                        "routes_used_by_macros_hor":_routes_used_by_macros_hor,
+                        "routes_used_by_macros_ver":_routes_used_by_macros_ver,
+                        "smoothing_factor":_smoothing_factor,
+                        "overlap_threshold":_overlap_threshold,
+                        "hard_macros_cnt":_hard_macros_cnt,
+                        "hard_macro_pins_cnt":_hard_macro_pins_cnt,
+                        "macros_cnt":_macros_cnt,
+                        "macro_pin_cnt":_macro_pin_cnt,
+                        "ports_cnt":_ports_cnt,
+                        "soft_macros_cnt":_soft_macros_cnt,
+                        "soft_macro_pins_cnt":_soft_macro_pins_cnt,
+                        "stdcells_cnt":_stdcells_cnt,
+                        "node_plc":_node_plc
+                    }
+
+        return info_dict
+
+    def restore_placement(self, plc_pth: str, ifInital=True, ifValidate=False, ifReadComment = False):
+        """
+            Read and retrieve .plc file information
+            NOTE: DO NOT always set self.init_plc because this function is also 
+            used to read final placement file.
+
+            ifReadComment: By default, Google's plc_client does not extract 
+            information from .plc comment. This is purely done in 
+            placement_util.py. For purpose of testing, we included this option.
+        """
+        # if plc is an initial placement
+        if ifInital:
+            self.init_plc = plc_pth
+        
+        # recompute cost from new location
+        self.FLAG_UPDATE_CONGESTION = True
+        self.FLAG_UPDATE_DENSITY = True
+        self.FLAG_UPDATE_WIRELENGTH = True
+        
+        # extracted information from .plc file
+        info_dict = self.__read_plc(plc_pth)
+
+        # validate netlist.pb.txt is on par with .plc
+        if ifValidate:
+            try:
+                assert(self.hard_macro_cnt == info_dict['hard_macros_cnt'])
+                assert(self.hard_macro_pins_cnt == info_dict['hard_macro_pins_cnt'])
+                assert(self.soft_macros_cnt == info_dict['soft_macros_cnt'])
+                assert(self.soft_macro_pins_cnt == info_dict['soft_macro_pins_cnt'])
+                assert(self.ports_cnt == info_dict['ports_cnt'])
+            except AssertionError:
+                _, _, tb = sys.exc_info()
+                traceback.print_tb(tb)
+                tb_info = traceback.extract_tb(tb)
+                _, line, _, text = tb_info[-1]
+                print('[NETLIST/PLC MISMATCH ERROR] at line {} in statement {}'\
+                    .format(line, text))
+                exit(1)
+        
+        # restore placement for each module
+        try:
+            assert sorted(self.port_indices +\
+                self.hard_macro_indices +\
+                self.soft_macro_indices) == list(info_dict['node_plc'].keys())
+        except AssertionError:
+            print('[PLC INDICES MISMATCH ERROR]', len(sorted(self.port_indices +\
+                self.hard_macro_indices +\
+                self.soft_macro_indices)), len(list(info_dict['node_plc'].keys())))
+            exit(1)
+        
+        for mod_idx in info_dict['node_plc'].keys():
+            mod_x = mod_y = mod_orient = mod_ifFixed = None
+            try:
+                mod_x = float(info_dict['node_plc'][mod_idx][0])
+                mod_y = float(info_dict['node_plc'][mod_idx][1])
+                mod_orient = info_dict['node_plc'][mod_idx][2]
+                mod_ifFixed = int(info_dict['node_plc'][mod_idx][3])
+            except Exception as e:
+                print('[PLC PARSER ERROR] %s' % str(e))
+
+            #TODO ValueError: Error in calling RestorePlacement with ('./Plc_client/test/ariane/initial.plc',): Can't place macro i_ariane/i_frontend/i_icache/sram_block_3__tag_sram/mem/mem_inst_mem_256x45_256x16_0x0 at (341.75, 8.8835). Exceeds the boundaries of the placement area..
+
+            self.modules_w_pins[mod_idx].set_pos(mod_x, mod_y)
+            
+            if mod_orient and mod_orient != '-':
+                self.modules_w_pins[mod_idx].set_orientation(mod_orient)
+            
+            if mod_ifFixed == 0:
+                self.modules_w_pins[mod_idx].set_fix_flag(False)
+            elif mod_ifFixed == 1:
+                self.modules_w_pins[mod_idx].set_fix_flag(True)
+        
+        # set meta information
+        if ifReadComment:
+            self.set_canvas_size(info_dict['width'], info_dict['height'])
+            self.set_placement_grid(info_dict['columns'], info_dict['rows'])
+            self.set_block_name(info_dict['block'])
+            self.set_routes_per_micron(
+                info_dict['routes_per_micron_hor'],
+                info_dict['routes_per_micron_ver']
+                )
+            self.set_macro_routing_allocation(
+                info_dict['routes_used_by_macros_hor'],
+                info_dict['routes_used_by_macros_ver']
+                )
+            self.set_congestion_smooth_range(info_dict['smoothing_factor'])
+            self.set_overlap_threshold(info_dict['overlap_threshold'])
 
     def __update_connection(self):
         """
@@ -371,17 +584,15 @@ class PlacementCost(object):
                         if macro_type == "MACRO" or macro_type == "macro":
                             weight = pin.get_weight()
                             macro.add_connections(inputs[k], weight)
-    
-    def __update_placement(self):
-        # assign modules to grid cells
-        pass
-
 
     def get_cost(self) -> float:
         """
         Compute wirelength cost from wirelength
         """
-        return self.get_wirelength() / ((self.get_canvas_width_height()[0] + self.get_canvas_width_height()[1]) * self.net_cnt)
+        if self.FLAG_UPDATE_WIRELENGTH:
+            self.FLAG_UPDATE_WIRELENGTH = False
+        return self.get_wirelength() / ((self.get_canvas_width_height()[0]\
+            + self.get_canvas_width_height()[1]) * self.net_cnt)
 
     def get_area(self) -> float:
         """
@@ -393,20 +604,20 @@ class PlacementCost(object):
                 total_area += mod.get_area()
         return total_area
 
-    def get_hard_macro_count(self) -> int:
+    def get_hard_macros_count(self) -> int:
         return self.hard_macro_cnt
 
-    def get_port_count(self) -> int:
-        return self.port_cnt
+    def get_ports_count(self) -> int:
+        return self.ports_cnt
 
-    def get_soft_macro_count(self) -> int:
-        return self.soft_macro_cnt
+    def get_soft_macros_count(self) -> int:
+        return self.soft_macros_cnt
 
-    def get_hard_macro_pin_count(self) -> int:
-        return self.hard_macro_pin_cnt
+    def get_hard_macro_pins_count(self) -> int:
+        return self.hard_macro_pins_cnt
 
-    def get_soft_macro_pin_count(self) -> int:
-        return self.soft_macro_pin_cnt
+    def get_soft_macro_pins_count(self) -> int:
+        return self.soft_macro_pins_cnt
 
     def get_wirelength(self) -> float:
         """
@@ -521,33 +732,15 @@ class PlacementCost(object):
     
     def get_congestion_cost(self):
         #return max(self.get_H_congestion_cost(), self.get_V_congestion_cost())
+        # TODO need to test if cong is smaller than 5
         return self.abu(self.V_routing_cong + self.H_routing_cong, 0.05)
-        # temp_cong = [sum(x) for x in zip(self.V_routing_cong, self.H_routing_cong)]
-
-        # occupied_cells = sorted([gc for gc in temp_cong if gc != 0.0], reverse=True)
-        # cong_cost = 0.0
-
-        # # take top 10%
-        # cong_cnt = math.floor(len(temp_cong) * 0.1)
-
-        # # if grid cell smaller than 10, take the average over occupied cells
-        # if len(temp_cong) < 10:
-        #     cong_cost = float(sum(occupied_cells) / len(occupied_cells))
-        #     return cong_cost
-
-        # idx = 0
-        # sum_cong = 0
-        # # take top 10%
-        # while idx < cong_cnt and idx < len(occupied_cells):
-        #     sum_cong += occupied_cells[idx]
-        #     idx += 1
-
-        # return float(sum_cong / cong_cnt)
 
     def __get_grid_cell_location(self, x_pos, y_pos):
         """
         private function for getting grid cell row/col ranging from 0...N
         """
+        self.grid_width = float(self.width/self.grid_col)
+        self.grid_height = float(self.height/self.grid_row)
         row = math.floor(y_pos / self.grid_height)
         col = math.floor(x_pos / self.grid_width)
         return row, col
@@ -661,6 +854,10 @@ class PlacementCost(object):
         """
         compute average of top 10% of grid cell density and take half of it
         """
+        if self.FLAG_UPDATE_DENSITY:
+            self.get_grid_cells_density()
+            self.FLAG_UPDATE_DENSITY=False
+
         occupied_cells = sorted([gc for gc in self.grid_cells if gc != 0.0], reverse=True)
         density_cost = 0.0
 
@@ -688,6 +885,11 @@ class PlacementCost(object):
         self.width = width
         self.height = height
 
+        # Flag updates
+        self.FLAG_UPDATE_CONGESTION = True
+        self.FLAG_UPDATE_DENSITY = True
+        self.FLAG_UPDATE_MACRO_AND_CLUSTERED_PORT_ADJ = True
+
         self.grid_width = float(self.width/self.grid_col)
         self.grid_height = float(self.height/self.grid_row)
         return True
@@ -702,9 +904,15 @@ class PlacementCost(object):
         """
         Set grid col/row
         """
+        print("#[PLACEMENT GRID] Col: %d, Row: %d" % (grid_col, grid_row))
         self.grid_col = grid_col
         self.grid_row = grid_row
 
+        # Flag updates
+        self.FLAG_UPDATE_CONGESTION = True
+        self.FLAG_UPDATE_DENSITY = True
+        self.FLAG_UPDATE_MACRO_AND_CLUSTERED_PORT_ADJ = True
+
         self.V_routing_cong = [0] * self.grid_col * self.grid_row
         self.H_routing_cong = [0] * self.grid_col * self.grid_row
         self.V_macro_routing_cong = [0] * self.grid_col * self.grid_row
@@ -726,11 +934,23 @@ class PlacementCost(object):
         """
         return sorted(self.hard_macro_indices + self.soft_macro_indices)
 
+    def set_project_name(self, project_name):
+        """
+        Set Project name
+        """
+        self.project_name = project_name
+
     def get_project_name(self) -> str:
         """
         Return Project name
         """
         return self.project_name
+    
+    def set_block_name(self, block_name:str) -> None:
+        """
+        Return Block name
+        """
+        self.block_name = block_name
 
     def get_block_name(self) -> str:
         """
@@ -742,6 +962,10 @@ class PlacementCost(object):
         """
         Set Routes per Micron
         """
+        print("#[ROUTES PER MICRON] Hor: %.2f, Ver: %.2f" % (hroutes_per_micron, vroutes_per_micron))
+        # Flag updates
+        self.FLAG_UPDATE_CONGESTION = True
+
         self.hroutes_per_micron = hroutes_per_micron
         self.vroutes_per_micron = vroutes_per_micron
 
@@ -755,7 +979,11 @@ class PlacementCost(object):
         """
         Set congestion smooth range
         """
-        self.smooth_range = int(smooth_range)
+        print("#[CONGESTION SMOOTH RANGE] Smooth Range: %d" % (smooth_range))
+        # Flag updates
+        self.FLAG_UPDATE_CONGESTION = True
+
+        self.smooth_range = math.floor(smooth_range)
 
     def get_congestion_smooth_range(self) -> float:
         """
@@ -767,6 +995,7 @@ class PlacementCost(object):
         """
         Set Overlap Threshold
         """
+        print("#[OVERLAP THRESHOLD] Threshold: %.4f" % (overlap_thres))
         self.overlap_thres = overlap_thres
 
     def get_overlap_threshold(self) -> float:
@@ -775,13 +1004,25 @@ class PlacementCost(object):
         """
         return self.overlap_thres
 
+    def set_canvas_boundary_check(self, ifCheck:bool) -> None:
+        """
+        boundary_check: Do a boundary check during node placement.
+        """
+        self.canvas_boundary_check = ifCheck
+
     def get_canvas_boundary_check(self) -> bool:
-        return False
+        """
+        return canvas_boundary_check
+        """
+        return self.canvas_boundary_check
 
     def set_macro_routing_allocation(self, hrouting_alloc:float, vrouting_alloc:float) -> None:
         """
         Set Vertical/Horizontal Macro Allocation
         """
+        # Flag updates
+        self.FLAG_UPDATE_CONGESTION = True
+
         self.hrouting_alloc = hrouting_alloc
         self.vrouting_alloc = vrouting_alloc
 
@@ -915,7 +1156,6 @@ class PlacementCost(object):
         self.t_routing(temp_gcell, weight)
         return
 
-
     def __macro_route_over_grid_cell(self, mod_x, mod_y, mod_w, mod_h):
         """
         private function for add module to grid cells
@@ -1019,29 +1259,38 @@ class PlacementCost(object):
 
     def get_vertical_routing_congestion(self):
         # TODO: detect if we need to run
-        self.get_routing()
+        if self.FLAG_UPDATE_CONGESTION:
+            self.get_routing()
+        
         return self.V_routing_cong
 
     def get_horizontal_routing_congestion(self):
         # TODO: detect if we need to run
-        self.get_routing()
+        if self.FLAG_UPDATE_CONGESTION:
+            self.get_routing()
+        
         return self.H_routing_cong
 
     def get_routing(self):
-        self.grid_width = float(self.width/self.grid_col)
-        self.grid_height = float(self.height/self.grid_row)
+        """
+            Route between modules
+        """
+        if self.FLAG_UPDATE_CONGESTION:
+            self.grid_width = float(self.width/self.grid_col)
+            self.grid_height = float(self.height/self.grid_row)
 
-        self.grid_v_routes = self.grid_width * self.vroutes_per_micron
-        self.grid_h_routes = self.grid_height * self.hroutes_per_micron
+            self.grid_v_routes = self.grid_width * self.vroutes_per_micron
+            self.grid_h_routes = self.grid_height * self.hroutes_per_micron
 
-        # reset grid
-        self.H_routing_cong = [0] * self.grid_row * self.grid_col
-        self.V_routing_cong = [0] * self.grid_row * self.grid_col
+            # reset grid
+            self.H_routing_cong = [0] * self.grid_row * self.grid_col
+            self.V_routing_cong = [0] * self.grid_row * self.grid_col
 
-        self.H_macro_routing_cong = [0] * self.grid_row * self.grid_col
-        self.V_macro_routing_cong = [0] * self.grid_row * self.grid_col
+            self.H_macro_routing_cong = [0] * self.grid_row * self.grid_col
+            self.V_macro_routing_cong = [0] * self.grid_row * self.grid_col
+
+            self.FLAG_UPDATE_CONGESTION = False
 
-        net_count = 0
         for mod in self.modules_w_pins:
             norm_fact = 1.0
             curr_type = mod.get_type()
@@ -1117,8 +1366,7 @@ class PlacementCost(object):
         # sum up routing congestion with macro congestion
         self.V_routing_cong = [sum(x) for x in zip(self.V_routing_cong, self.V_macro_routing_cong)]
         self.H_routing_cong = [sum(x) for x in zip(self.H_routing_cong, self.H_macro_routing_cong)]
-
-    
+ 
     def __smooth_routing_cong(self):
         temp_V_routing_cong = [0] * self.grid_col * self.grid_row
         temp_H_routing_cong = [0] * self.grid_col * self.grid_row
@@ -1194,20 +1442,36 @@ class PlacementCost(object):
         """
         Return Vertical/Horizontal Macro Allocation
         """
-        return self.modules[node_idx].get_type()
+        try:
+            return self.modules_w_pins[node_idx].get_type()
+        except IndexError:
+            # NOTE: Google's API return NONE if out of range
+            print("[INDEX OUT OF RANGE WARNING] Can not process index at {}".format(node_idx))
+            return None
 
     def make_soft_macros_square(self):
         pass
 
+    def set_use_incremental_cost(self, use_incremental_cost):
+        self.use_incremental_cost = use_incremental_cost
+
+    def get_use_incremental_cost(self):
+        return self.use_incremental_cost
+
     def get_macro_adjacency(self) -> list:
         """
         Compute Adjacency Matrix
         """
         # NOTE: in pb.txt, netlist input count exceed certain threshold will be ommitted
         #[MACRO][macro]
+
+        if self.FLAG_UPDATE_MACRO_ADJ:
+            # do some update
+            self.FLAG_UPDATE_MACRO_ADJ = False
+
         module_indices = self.hard_macro_indices + self.soft_macro_indices
-        macro_adj = [0] * (self.hard_macro_cnt + self.soft_macro_cnt) * (self.hard_macro_cnt + self.soft_macro_cnt)
-        assert len(macro_adj) == (self.hard_macro_cnt + self.soft_macro_cnt) * (self.hard_macro_cnt + self.soft_macro_cnt)
+        macro_adj = [0] * (self.hard_macro_cnt + self.soft_macros_cnt) * (self.hard_macro_cnt + self.soft_macros_cnt)
+        assert len(macro_adj) == (self.hard_macro_cnt + self.soft_macros_cnt) * (self.hard_macro_cnt + self.soft_macros_cnt)
 
         for row_idx, module_idx in enumerate(sorted(module_indices)):
             # row index
@@ -1230,41 +1494,17 @@ class PlacementCost(object):
                 if h_module_name in curr_module.get_connection():
                     entry += curr_module.get_connection()[h_module_name]
 
-                macro_adj[row_idx * (self.hard_macro_cnt + self.soft_macro_cnt) + col_idx] = entry
-                macro_adj[col_idx * (self.hard_macro_cnt + self.soft_macro_cnt) + row_idx] = entry
+                macro_adj[row_idx * (self.hard_macro_cnt + self.soft_macros_cnt) + col_idx] = entry
+                macro_adj[col_idx * (self.hard_macro_cnt + self.soft_macros_cnt) + row_idx] = entry
 
         return macro_adj
 
-    def is_node_fixed(self):
-        pass
-
-    def restore_placement(self, init_plc_pth: str):
-        """
-        Read and retrieve .plc file information
-        """
-        self.init_plc = init_plc_pth
-        self.__read_plc()
-
-    def optimize_stdcells(self):
-        pass
-
-    def update_node_coords(self):
-        pass
-
-    def fix_node_coord(self):
-        pass
-
-    def update_port_sides(self):
-        pass
-
-    def snap_ports_to_edges(self):
-        pass
-
     def get_macro_and_clustered_port_adjacency(self):
         """
         Compute Adjacency Matrix (Unclustered PORTs)
-        if module is a PORT, assign nearest cell location even if OOB
+        if module is a PORT, assign it to nearest cell location even if OOB
         """
+
         #[MACRO][macro]
         module_indices = self.hard_macro_indices + self.soft_macro_indices
 
@@ -1359,9 +1599,24 @@ class PlacementCost(object):
                 
         return macro_adj, sorted(cell_location)
 
-    def get_node_location(self, node_idx):
+    def is_node_fixed(self):
         pass
 
+    def optimize_stdcells(self):
+        pass
+
+    def update_node_coords(self):
+        pass
+
+    def update_port_sides(self):
+        pass
+
+    def snap_ports_to_edges(self):
+        pass
+
+    def get_node_location(self, node_idx):
+        pass
+                       
     def get_grid_cell_of_node(self, node_idx):
         """ if grid_cell at grid crossing, break-tie to upper right
         """
@@ -1377,11 +1632,9 @@ class PlacementCost(object):
         """In case plc is loaded with fixed macros
         """
         pass
-
-    def fix_node_coord(self):
-        """Find all ports and fix their coordinates.
-        """
-        pass
+    
+    def fix_node_coord(self, node_idx):
+        self.modules_w_pins[node_idx].set_fix_flag(True)
 
     def unplace_all_nodes(self):
         pass
@@ -1410,6 +1663,9 @@ class PlacementCost(object):
     def get_blockages(self):
         pass
 
+    def create_blockage(self, minx, miny, maxx, maxy, blockage_rate):
+        self.blockages.append([minx, miny, maxx, maxy, blockage_rate])
+
     def get_ref_node_id(self, node_idx=-1):
         """ref_node_id is used for macro_pins. Refers to the macro it belongs to.
         """
@@ -1473,7 +1729,6 @@ class PlacementCost(object):
         plt.show()
         plt.close('all')
 
-
     # Board Entity Definition
     class Port:
         def __init__(self, name, x = 0.0, y = 0.0, side = "BOTTOM"):
@@ -1483,7 +1738,7 @@ class PlacementCost(object):
             self.side = side # "BOTTOM", "TOP", "LEFT", "RIGHT"
             self.sink = {} # standard cells, macro pins, ports driven by this cell
             self.connection = {} # [module_name] => edge degree
-            self.ifFixed = True
+            self.fix_flag = True
             self.placement = 0 # needs to be updated
 
         def get_name(self):
@@ -1551,6 +1806,12 @@ class PlacementCost(object):
 
         def get_type(self):
             return "PORT"
+        
+        def set_fix_flag(self, fix_flag):
+            self.fix_flag = fix_flag
+        
+        def get_fix_flag(self):
+            return self.fix_flag
 
     class SoftMacro:
         def __init__(self, name, width, height, x = 0.0, y = 0.0):
@@ -1560,7 +1821,8 @@ class PlacementCost(object):
             self.x = float(x)
             self.y = float(y)
             self.connection = {} # [module_name] => edge degree
-            self.ifFixed = False
+            self.orientation = None
+            self.fix_flag = False
             self.ifPlaced = True
             self.location = 0 # needs to be updated
 
@@ -1602,6 +1864,12 @@ class PlacementCost(object):
 
         def get_connection(self):
             return self.connection
+        
+        def set_orientation(self, orientation):
+            self.orientation = orientation
+        
+        def get_orientation(self):
+            return self.orientation
 
         def get_area(self):
             return self.width * self.height
@@ -1617,6 +1885,12 @@ class PlacementCost(object):
         
         def get_location(self):
             return self.location
+        
+        def set_fix_flag(self, fix_flag):
+            self.fix_flag = fix_flag
+        
+        def get_fix_flag(self):
+            return self.fix_flag
 
     class SoftMacroPin:
         def __init__(   self, name,
@@ -1694,7 +1968,7 @@ class PlacementCost(object):
             self.y = float(y)
             self.orientation = orientation
             self.connection = {} # [module_name] => edge degree
-            self.ifFixed = False
+            self.fix_flag = False
             self.ifPlaced = True
             self.location = 0 # needs to be updated
 
@@ -1736,6 +2010,9 @@ class PlacementCost(object):
 
         def set_orientation(self, orientation):
             self.orientation = orientation
+        
+        def get_orientation(self):
+            return self.orientation
 
         def get_type(self):
             return "MACRO"
@@ -1754,6 +2031,12 @@ class PlacementCost(object):
         
         def get_location(self):
             return self.location
+        
+        def set_fix_flag(self, fix_flag):
+            self.fix_flag = fix_flag
+        
+        def get_fix_flag(self):
+            return self.fix_flag
 
     class HardMacroPin:
         def __init__(self, name,
@@ -1843,13 +2126,13 @@ def main():
     print(plc.get_block_name())
     print("Area: ", plc.get_area())
     print("Wirelength: ", plc.get_wirelength())
-    print("# HARD_MACROs     :         %d"%(plc.get_hard_macro_count()))
-    print("# HARD_MACRO_PINs :         %d"%(plc.get_hard_macro_pin_count()))
-    print("# MACROs          :         %d"%(plc.get_hard_macro_count() + plc.get_soft_macro_count()))
-    print("# MACRO_PINs      :         %d"%(plc.get_hard_macro_pin_count() + plc.get_soft_macro_pin_count()))
-    print("# PORTs           :         %d"%(plc.get_port_count()))
-    print("# SOFT_MACROs     :         %d"%(plc.get_soft_macro_count()))
-    print("# SOFT_MACRO_PINs :         %d"%(plc.get_soft_macro_pin_count()))
+    print("# HARD_MACROs     :         %d"%(plc.get_hard_macros_count()))
+    print("# HARD_MACRO_PINs :         %d"%(plc.get_hard_macro_pins_count()))
+    print("# MACROs          :         %d"%(plc.get_hard_macros_count() + plc.get_soft_macros_count()))
+    print("# MACRO_PINs      :         %d"%(plc.get_hard_macro_pins_count() + plc.get_soft_macro_pins_count()))
+    print("# PORTs           :         %d"%(plc.get_ports_count()))
+    print("# SOFT_MACROs     :         %d"%(plc.get_soft_macros_count()))
+    print("# SOFT_MACRO_PINs :         %d"%(plc.get_soft_macro_pins_count()))
     print("# STDCELLs        :         0")
 
 if __name__ == '__main__':

CodeElements/Plc_client/plc_client_os_test.py

+import numpy as np
+import sys,os,traceback
+import argparse
+import math
 from absl import flags
+from absl.flags import argparse_flags
 from absl import app
-from torch import feature_alpha_dropout
 from Plc_client import plc_client_os as plc_client_os
-from Plc_client import plc_client as plc_client
-import numpy as np
-import sys
-import time
-import math
+try:
+    from Plc_client import plc_client as plc_client
+except ImportError:
+    print("[PLC CLIENT MISSING] Downloading Google's API for testing!")
+    os.system("curl 'https://raw.githubusercontent.com/google-research/circuit_training/main/circuit_training/environment/plc_client.py' > ./Plc_client/plc_client.py")
+    from Plc_client import plc_client as plc_client
 np.set_printoptions(threshold=sys.maxsize)
-FLAGS = flags.FLAGS
-
-class CircuitDataBaseTest():
-    # NETLIST_PATH = "./Plc_client/test/sample_clustered_uniform_two_soft/netlist.pb.txt"
-    # NETLIST_PATH = "./Plc_client/test/ariane_hard2soft/netlist.pb.txt"
-    # NETLIST_PATH = "./Plc_client/test/ariane_soft2hard/netlist.pb.txt"
-    # NETLIST_PATH = "./Plc_client/test/ariane_port2soft/netlist.pb.txt"
-    # NETLIST_PATH = "./Plc_client/test/sample_clustered_nomacro/netlist.pb.txt"
-    # NETLIST_PATH = "./Plc_client/test/sample_clustered_macroxy/netlist.pb.txt"
-    # NETLIST_PATH = "./Plc_client/test/ariane/netlist.pb.txt"
-    # NETLIST_PATH = "./Plc_client/test/ariane133/netlist.pb.txt"
-    NETLIST_PATH = "./Plc_client/test/testcases/TC1_MP1_0_0_P2_0_1.pb.txt"
-    # NETLIST_PATH = "./Plc_client/test/testcases/TC24_MP1_0_0_MP2_4_4.pb.txt"
-    # NETLIST_PATH = "./Plc_client/test/0P1M1m/netlist.pb.txt"
-    # NETLIST_PATH = "./Plc_client/test/0P2M0m/netlist.pb.txt"
-    # NETLIST_PATH = "./Plc_client/test/0P3M0m/netlist.pb.txt"
-    # NETLIST_PATH = "./Plc_client/test/0P4M0m/netlist.pb.txt"
-    # NETLIST_PATH = "./Plc_client/test/testcases_xm/TC_MP1_4_1_MP2_2_2_MP3_3_4_MP4_0_0.pb.txt"
-
-    # Google's Ariane
-    # CANVAS_WIDTH = 356.592
-    # CANVAS_HEIGHT = 356.640
-    # GRID_COL = 35
-    # GRID_ROW = 33
-
-    # Ariane133
-    CANVAS_WIDTH = 1599.99
-    CANVAS_HEIGHT = 1600.06
-    GRID_COL = 24
-    GRID_ROW = 21
-
-    # Sample clustered
-    # CANVAS_WIDTH = 400
-    # CANVAS_HEIGHT = 400
-    # GRID_COL = 4
-    # GRID_ROW = 4
-
-    # PMm
-    # CANVAS_WIDTH = 100
-    # CANVAS_HEIGHT = 100
-    # GRID_COL = 5
-    # GRID_ROW = 5
-
-    def __init__(self, NETLIST_PATH) -> None:
+# FLAGS = flags.FLAGS
+
+"""plc_client_os_test docstrings
+
+Test Utility Class for Google's API plc_wrapper_main with plc_client.py and plc_client_os.py
+
+Example:
+    At ./MacroPlacement/CodeElement, run the following command:
+
+        $ python3 -m Plc_client.plc_client_os_test --netlist ./Plc_client/test/ariane/netlist.pb.txt\
+            --plc ./Plc_client/test/ariane/initial.plc\
+            --width 356.592\
+            --height 356.640\
+            --col 35\
+            --row 33\
+            --rpmh 10\
+            --rpmv 10\
+            --marh 5\
+            --marv 5\
+            --smooth 2
+        
+        $ python3 -m Plc_client.plc_client_os_test --netlist ./Plc_client/test/ariane133/netlist.pb.txt\
+            --plc ./Plc_client/test/ariane133/initial.plc\
+            --width 1599\
+            --height 1600.06\
+            --col 24\
+            --row 21\
+            --rpmh 10\
+            --rpmv 10\
+            --marh 5\
+            --marv 5\
+            --smooth 2
+
+Todo:
+    * Clean up code
+    * Extract argument from command line
+    * Report index for each mismatch array entry 
+
+"""
+
+class PlacementCostTest():
+
+    """ Canvas Setting Reference Table
+        ++ Google's Ariane ++
+        - CANVAS_WIDTH = 356.592
+        - CANVAS_HEIGHT = 356.640
+        - GRID_COL = 35
+        - GRID_ROW = 33
+
+        ++ Ariane133 ++
+        - CANVAS_WIDTH = 1599.99
+        - CANVAS_HEIGHT = 1600.06
+        - GRID_COL = 24
+        - GRID_ROW = 21
+
+        ++ Sample clustered ++
+        - CANVAS_WIDTH = 400
+        - CANVAS_HEIGHT = 400
+        - GRID_COL = 4
+        - GRID_ROW = 4
+
+        ++ PMm ++
+        - CANVAS_WIDTH = 100
+        - CANVAS_HEIGHT = 100
+        - GRID_COL = 5
+        - GRID_ROW = 5
+    """
+
+
+    def __init__(self, NETLIST_PATH, PLC_PATH=None,
+                width=0, height=0,
+                column=0, row=0, rpmv=10, rpmh=10,
+                marh=10, marv=10, smooth=1) -> None:
         self.NETLIST_PATH = NETLIST_PATH
+        self.PLC_PATH = PLC_PATH
+        self.CANVAS_WIDTH = width
+        self.CANVAS_HEIGHT = height
+        self.GRID_COL = column
+        self.GRID_ROW = row
+
+        # for congestion computation
+        self.RPMV = rpmv
+        self.RPMH = rpmh
+        self.MARH = marh
+        self.MARV = marv
+        self.SMOOTH = smooth
 
-    def test_proxy_congestion(self):
+    
+    def test_metadata(self):
+        print("############################ TEST METADATA ############################")
+        # Google's Binary Executable
+        self.plc = plc_client.PlacementCost(self.NETLIST_PATH)
+        # Open-sourced Implementation
+        self.plc_os = plc_client_os.PlacementCost(netlist_file=self.NETLIST_PATH,
+                                                macro_macro_x_spacing = 50,
+                                                macro_macro_y_spacing = 50)
+
+        # NOTE: must set canvas before restoring placement, otherwise OOB error
+        self.plc.set_canvas_size(self.CANVAS_WIDTH, self.CANVAS_HEIGHT)
+        self.plc.set_placement_grid(self.GRID_COL, self.GRID_ROW)
+        self.plc_os.set_canvas_size(self.CANVAS_WIDTH, self.CANVAS_HEIGHT)
+        self.plc_os.set_placement_grid(self.GRID_COL, self.GRID_ROW)
+
+        if self.PLC_PATH:
+            print("[PLC FILE FOUND] Loading info from .plc file")
+            self.plc_os.set_canvas_boundary_check(False)
+            self.plc_os.restore_placement(self.PLC_PATH,
+                                            ifInital=True,
+                                            ifValidate=True,
+                                            ifReadComment=False)
+            self.plc.set_canvas_boundary_check(False)
+            self.plc.restore_placement(self.PLC_PATH)
+        else:
+            print("[PLC FILE MISSING] Using only netlist info")
+
+        try:
+            assert int(self.plc_os.get_area()) == int(self.plc.get_area())
+            
+            self.plc.set_routes_per_micron(1.0, 2.0)
+            self.plc_os.set_routes_per_micron(1.0, 2.0)
+            assert self.plc.get_routes_per_micron() == self.plc_os.get_routes_per_micron()
+
+            self.plc.set_overlap_threshold(2.0)
+            self.plc_os.set_overlap_threshold(2.0)
+            assert self.plc.get_overlap_threshold() == self.plc_os.get_overlap_threshold()
+
+            self.plc.set_congestion_smooth_range(2.0)
+            self.plc_os.set_congestion_smooth_range(2.0)
+            assert self.plc.get_congestion_smooth_range() == self.plc_os.get_congestion_smooth_range()
+
+            self.plc.set_macro_routing_allocation(3.0, 4.0)
+            self.plc_os.set_macro_routing_allocation(3.0, 4.0)
+            assert self.plc.get_macro_routing_allocation() == self.plc_os.get_macro_routing_allocation()
+        except Exception as e:
+            _, _, tb = sys.exc_info()
+            traceback.print_tb(tb)
+            tb_info = traceback.extract_tb(tb)
+            _, line, _, text = tb_info[-1]
+            print('[METADATA ERROR] at line {} in statement {}'\
+                .format(line, text))
+            exit(1)
+        
+        # test get_macro_adjacency
+        plc_macroadj = self.plc.get_macro_adjacency()
+        plc_macroadj = np.array(plc_macroadj).reshape(int(math.sqrt(len(plc_macroadj))),\
+             int(math.sqrt(len(plc_macroadj))))
+
+        plcos_macroadj = self.plc_os.get_macro_adjacency()
+        plcos_macroadj = np.array(plcos_macroadj).reshape(int(math.sqrt(len(plcos_macroadj))),\
+             int(math.sqrt(len(plcos_macroadj))))
+
+        try:
+            assert(np.sum(np.nonzero(plc_macroadj - plcos_macroadj)) == 0)
+        except Exception as e:
+            print("[MACRO ADJ ERROR] Mismatched found -- {}".format(str(e)))
+            exit(1)
+        
+        # test get_macro_and_clustered_port_adjacency
+        plc_clusteradj, plc_cell = self.plc.get_macro_and_clustered_port_adjacency()
+        plc_clusteradj = np.array(plc_clusteradj).reshape(int(math.sqrt(len(plc_clusteradj))),\
+             int(math.sqrt(len(plc_clusteradj))))
+
+        plcos_clusteradj, plcos_cell = self.plc_os.get_macro_and_clustered_port_adjacency()
+        plcos_clusteradj = np.array(plcos_clusteradj).reshape(int(math.sqrt(len(plcos_clusteradj))),\
+             int(math.sqrt(len(plcos_clusteradj))))
+
+        try:
+            for plc_adj, plcos_adj in zip(plc_clusteradj, plcos_clusteradj):
+                assert(np.sum(np.nonzero(plc_adj - plcos_adj)) == 0)
+        except Exception as e:
+            print("[MACRO AND CLUSTERED PORT ADJ ERROR] Mismatched found -- {}".format(str(e)))
+            exit(1)
+        
+        print("                  +++++++++++++++++++++++++++")
+        print("                  +++ TEST METADATA: PASS +++")
+        print("                  +++++++++++++++++++++++++++")
+    
+    def view_canvas(self):
+        print("############################ VIEW CANVAS ############################")
+        self.plc_os = plc_client_os.PlacementCost(netlist_file=self.NETLIST_PATH,
+                                                macro_macro_x_spacing = 50,
+                                                macro_macro_y_spacing = 50)
+        self.plc.set_canvas_size(self.CANVAS_WIDTH, self.CANVAS_HEIGHT)
+        self.plc.set_placement_grid(self.GRID_COL, self.GRID_ROW)
+        self.plc_os.set_canvas_size(self.CANVAS_WIDTH, self.CANVAS_HEIGHT)
+        self.plc_os.set_placement_grid(self.GRID_COL, self.GRID_ROW)
+        # show canvas
+        self.plc_os.display_canvas()
+
+    def test_proxy_cost(self):
+        print("############################ TEST PROXY COST ############################")
         # Google's Binary Executable
         self.plc = plc_client.PlacementCost(self.NETLIST_PATH)
+        
+        # Open-sourced Implementation
+        self.plc_os = plc_client_os.PlacementCost(netlist_file=self.NETLIST_PATH,
+                                                macro_macro_x_spacing = 50,
+                                                macro_macro_y_spacing = 50)
+        
+        if self.PLC_PATH:
+            print("[PLC FILE FOUND] Loading info from .plc file")
+            self.plc_os.set_canvas_boundary_check(False)
+            self.plc_os.restore_placement(self.PLC_PATH,
+                                            ifInital=True,
+                                            ifValidate=True,
+                                            ifReadComment=False)
+            self.plc.set_canvas_boundary_check(False)
+            # self.plc.restore_placement(self.PLC_PATH)
+        else:
+            print("[PLC FILE MISSING] Using only netlist info")
+
+        self.plc.set_routes_per_micron(self.RPMH, self.RPMV)
+        self.plc_os.set_routes_per_micron(self.RPMH, self.RPMV)
+
+        self.plc.set_macro_routing_allocation(self.MARH, self.MARV)
+        self.plc_os.set_macro_routing_allocation(self.MARH, self.MARV)
+
+        self.plc.set_congestion_smooth_range(self.SMOOTH)
+        self.plc_os.set_congestion_smooth_range(self.SMOOTH)
+
+        self.plc.set_canvas_size(self.CANVAS_WIDTH, self.CANVAS_HEIGHT)
+        self.plc.set_placement_grid(self.GRID_COL, self.GRID_ROW)
+        self.plc_os.set_canvas_size(self.CANVAS_WIDTH, self.CANVAS_HEIGHT)
+        self.plc_os.set_placement_grid(self.GRID_COL, self.GRID_ROW)
+
+        # TODO: [IGNORE] Setting blockage has no effect on proxy cost computation
+        if False:
+            self.plc.create_blockage(0, 0, 400, 400, 1)
+            self.plc.create_blockage(0, 0, 200, 200, 1)
+            print(self.plc.get_blockages())
+            print(self.plc.make_soft_macros_square())
+            print(self.plc.set_use_incremental_cost(True))
+            print(self.plc_os.get_soft_macros_count())
+
+        # HPWL
+        try:
+            assert int(self.plc_os.get_wirelength()) == int(self.plc.get_wirelength())
+            assert abs(self.plc.get_cost() - self.plc_os.get_cost()) <= 1e-3
+        except Exception as e:
+            print("[WIRELENGTH ERROR] Discrepancies found when computing wirelength -- {}, {}".format(str(self.plc.get_cost()), self.plc_os.get_cost()))
+            exit(1)
+
+        # Density
+        try:
+            assert int(sum(self.plc_os.get_grid_cells_density())) == int(sum(self.plc.get_grid_cells_density()))
+            assert int(self.plc_os.get_density_cost()) == int(self.plc.get_density_cost())
+        except Exception as e:
+            print("[DENSITY ERROR] Discrepancies found when computing density -- {}, {}".format(str(self.plc.get_density_cost()), self.plc_os.get_density_cost()))
+            exit(1)
+
+        # Congestion
+        try:
+            assert abs(sum(self.plc_os.get_horizontal_routing_congestion()) - sum(self.plc.get_horizontal_routing_congestion())) < 1e-3
+            assert abs(sum(self.plc_os.get_vertical_routing_congestion()) - sum(self.plc.get_vertical_routing_congestion())) < 1e-3
+            assert abs(self.plc.get_congestion_cost() - self.plc_os.get_congestion_cost()) < 1e-3
+        except Exception as e:
+            print("[CONGESTION ERROR] Discrepancies found when computing congestion -- {}".format(str(e)))
+            exit(1)
+
+        print("                  +++++++++++++++++++++++++++++")
+        print("                  +++ TEST PROXY COST: PASS +++")
+        print("                  +++++++++++++++++++++++++++++")
+
+    def test_miscellaneous(self):
+        # Google's Binary Executable
+        self.plc = plc_client.PlacementCost(self.NETLIST_PATH)
+        self.plc_os = plc_client_os.PlacementCost(netlist_file=self.NETLIST_PATH,
+                                                macro_macro_x_spacing = 50,
+                                                macro_macro_y_spacing = 50)
+        print("****************** miscellaneous ******************")
+        self.plc.set_canvas_size(self.CANVAS_WIDTH, self.CANVAS_HEIGHT)
+        self.plc.set_placement_grid(self.GRID_COL, self.GRID_ROW)
+        self.plc_os.set_canvas_size(self.CANVAS_WIDTH, self.CANVAS_HEIGHT)
+        self.plc_os.set_placement_grid(self.GRID_COL, self.GRID_ROW)
+        NODE_IDX = 0
+        print("get_macro_indices", self.plc.get_macro_indices(), self.plc_os.get_macro_indices())
+        print("get_node_name", self.plc.get_node_name(NODE_IDX))
+        print("get_node_location", self.plc.get_node_location(NODE_IDX))
+        print("get_grid_cell_of_node", self.plc.get_grid_cell_of_node(NODE_IDX))
+        print("get_node_location", self.plc.get_node_location(NODE_IDX))
+        print("get_macro_orientation", self.plc.get_macro_orientation(NODE_IDX))
+        print("is_node_placed", self.plc.is_node_placed(NODE_IDX))
+        print("get_source_filename", self.plc.get_source_filename())
+        print("get_blockages", self.plc.get_blockages())
+        print("get_ref_node_id", self.plc.get_ref_node_id(NODE_IDX), self.plc.get_ref_node_id(NODE_IDX))
+        print("get_node_mask\n", np.array(self.plc.get_node_mask(NODE_IDX)).reshape((4,4)))
+        print("can_place_node", self.plc.can_place_node(0, 1))
+        print("***************************************************")
+    
+    def test_proxy_congestion(self):
+        # Google's API
+        self.plc = plc_client.PlacementCost(self.NETLIST_PATH)
         self.plc_os = plc_client_os.PlacementCost(self.NETLIST_PATH)
 
         # set rpm
         self.plc.set_routes_per_micron(10, 10)
         self.plc_os.set_routes_per_micron(10, 10)
 
-        # self.plc.set_macro_routing_allocation(5, 5)
-        # self.plc_os.set_macro_routing_allocation(5, 5)
-
-        self.plc.set_macro_routing_allocation(0, 0)
-        self.plc_os.set_macro_routing_allocation(0, 0)
+        self.plc.set_macro_routing_allocation(10, 10)
+        self.plc_os.set_macro_routing_allocation(10, 10)
 
         self.plc.set_congestion_smooth_range(0.0)
         self.plc_os.set_congestion_smooth_range(0.0)
@@ -77,18 +322,14 @@ class CircuitDataBaseTest():
         self.plc_os.set_canvas_size(self.CANVAS_WIDTH, self.CANVAS_HEIGHT)
         self.plc_os.set_placement_grid(self.GRID_COL, self.GRID_ROW)
 
-        print("Name: ", self.plc.get_source_filename().rsplit("/", 1)[1])
 
-        # self.plc_os.display_canvas(amplify=True)
-
-        # start = time.time()
         temp_gl_h = np.array(self.plc.get_horizontal_routing_congestion())
         temp_os_h =  np.array(self.plc_os.get_horizontal_routing_congestion())
         print(temp_gl_h.reshape(self.GRID_COL, self.GRID_ROW))
         print(temp_os_h.reshape(self.GRID_COL, self.GRID_ROW))
 
-        print("GL H Congestion: ", temp_gl_h)
-        print("OS H Congestion: ", temp_os_h)
+        print("GL H Congestion: ", self.plc.get_horizontal_routing_congestion())
+        print("OS H Congestion: ", self.plc_os.get_horizontal_routing_congestion())
 
         temp_gl_v = np.array(self.plc.get_vertical_routing_congestion())
         temp_os_v = np.array(self.plc_os.get_vertical_routing_congestion())
@@ -133,140 +374,44 @@ class CircuitDataBaseTest():
         ####################################################################### BY ENTRY
         print("**************BY ENTRY DIFF")
         print(temp_gl_h_mc[0][6], temp_os_h_mc[0][6])
-        # print(temp_gl_v_mc[1][6], temp_os_v_mc[1][6])
-
-
-        ######################################################################
-        # end = time.time()
-        # print("time elapsed:", end - start)
-
-        # for idx in range(len(temp_gl_h)):
-        #     print("gl, os:", temp_gl_h[idx], temp_os_h[idx], temp_gl_v[idx], temp_os_v[idx])
-
-        # print("congestion summation gl os", sum(temp_gl_h), sum(temp_os_h), sum(temp_gl_v), sum(temp_os_v))
-
-    def test_proxy_cost(self):
-        # Google's Binary Executable
-        self.plc = plc_client.PlacementCost(self.NETLIST_PATH)
-        
-        # Open-sourced Implementation
-        self.plc_os = plc_client_os.PlacementCost(netlist_file=self.NETLIST_PATH,
-                                                macro_macro_x_spacing = 50,
-                                                macro_macro_y_spacing = 50)
-
-        self.plc.set_canvas_size(self.CANVAS_WIDTH, self.CANVAS_HEIGHT)
-        self.plc.set_placement_grid(self.GRID_COL, self.GRID_ROW)
-        self.plc_os.set_canvas_size(self.CANVAS_WIDTH, self.CANVAS_HEIGHT)
-        self.plc_os.set_placement_grid(self.GRID_COL, self.GRID_ROW)
-
-        # print(self.plc_os.display_canvas())
-        
-        print(self.plc_os.get_wirelength(), self.plc.get_wirelength())
-
-        assert int(self.plc_os.get_wirelength()) == int(self.plc.get_wirelength())
-        print("os wl cost", self.plc_os.get_cost())
-        print("gl wl cost", self.plc.get_cost())
-        assert abs(self.plc.get_cost() - self.plc_os.get_cost()) <= 10e-3
-        print("gl density\n", np.array(self.plc.get_grid_cells_density()).reshape(self.GRID_COL, self.GRID_ROW))
-        print("os density\n", np.array(self.plc_os.get_grid_cells_density()).reshape(self.GRID_COL, self.GRID_ROW))
-
-        assert int(sum(self.plc_os.get_grid_cells_density())) == int(sum(self.plc.get_grid_cells_density()))
-        assert int(self.plc_os.get_density_cost()) == int(self.plc.get_density_cost())
-        print("os density cost", self.plc_os.get_density_cost())
-        print("gl density cost", self.plc.get_density_cost())
-    
-    def test_metadata(self):
-        # Google's Binary Executable
-        self.plc = plc_client.PlacementCost(self.NETLIST_PATH)
-        # Open-sourced Implementation
-        self.plc_os = plc_client_os.PlacementCost(netlist_file=self.NETLIST_PATH,
-                                                macro_macro_x_spacing = 50,
-                                                macro_macro_y_spacing = 50)
-        
-        self.plc.set_canvas_size(self.CANVAS_WIDTH, self.CANVAS_HEIGHT)
-        self.plc.set_placement_grid(self.GRID_COL, self.GRID_ROW)
-        self.plc_os.set_canvas_size(self.CANVAS_WIDTH, self.CANVAS_HEIGHT)
-        self.plc_os.set_placement_grid(self.GRID_COL, self.GRID_ROW)
-
-        self.plc_os.get_grid_cells_density()
-
-        assert int(self.plc_os.get_area()) == int(self.plc.get_area())
-        
-        self.plc.set_routes_per_micron(1.0, 2.0)
-        self.plc_os.set_routes_per_micron(1.0, 2.0)
-        assert self.plc.get_routes_per_micron() == self.plc_os.get_routes_per_micron()
-
-        self.plc.set_overlap_threshold(2.0)
-        self.plc_os.set_overlap_threshold(2.0)
-        assert self.plc.get_overlap_threshold() == self.plc_os.get_overlap_threshold()
-
-        self.plc.set_congestion_smooth_range(2.0)
-        self.plc_os.set_congestion_smooth_range(2.0)
-        assert self.plc.get_congestion_smooth_range() == self.plc_os.get_congestion_smooth_range()
-
-        self.plc.set_macro_routing_allocation(3.0, 4.0)
-        self.plc_os.set_macro_routing_allocation(3.0, 4.0)
-        assert self.plc.get_macro_routing_allocation() == self.plc_os.get_macro_routing_allocation()
-        
-        # test get_macro_adjacency
-        plc_macroadj = self.plc.get_macro_adjacency()
-        plc_macroadj = np.array(plc_macroadj).reshape(int(math.sqrt(len(plc_macroadj))),\
-             int(math.sqrt(len(plc_macroadj))))
-
-        plcos_macroadj = self.plc_os.get_macro_adjacency()
-        plcos_macroadj = np.array(plcos_macroadj).reshape(int(math.sqrt(len(plcos_macroadj))),\
-             int(math.sqrt(len(plcos_macroadj))))
-
-        assert(np.sum(np.nonzero(plc_macroadj - plcos_macroadj)) == 0)
-        
-        # test get_macro_and_clustered_port_adjacency
-        plc_clusteradj, plc_cell = self.plc.get_macro_and_clustered_port_adjacency()
-        plc_clusteradj = np.array(plc_clusteradj).reshape(int(math.sqrt(len(plc_clusteradj))),\
-             int(math.sqrt(len(plc_clusteradj))))
-
-        plcos_clusteradj, plcos_cell = self.plc_os.get_macro_and_clustered_port_adjacency()
-        plcos_clusteradj = np.array(plcos_clusteradj).reshape(int(math.sqrt(len(plcos_clusteradj))),\
-             int(math.sqrt(len(plcos_clusteradj))))
 
-        assert(plc_cell == plcos_cell)
-
-        for plc_adj, plcos_adj in zip(plc_clusteradj, plcos_clusteradj):
-            assert(np.sum(np.nonzero(plc_adj - plcos_adj)) == 0)
-
-    def test_miscellaneous(self):
-        # Google's Binary Executable
-        self.plc = plc_client.PlacementCost(self.NETLIST_PATH)
-        self.plc_os = plc_client_os.PlacementCost(netlist_file=self.NETLIST_PATH,
-                                                macro_macro_x_spacing = 50,
-                                                macro_macro_y_spacing = 50)
-        print("****************** miscellaneous ******************")
-        self.plc.set_canvas_size(self.CANVAS_WIDTH, self.CANVAS_HEIGHT)
-        self.plc.set_placement_grid(self.GRID_COL, self.GRID_ROW)
-        self.plc_os.set_canvas_size(self.CANVAS_WIDTH, self.CANVAS_HEIGHT)
-        self.plc_os.set_placement_grid(self.GRID_COL, self.GRID_ROW)
-        NODE_IDX = 0
-        print("get_macro_indices", self.plc.get_macro_indices(), self.plc_os.get_macro_indices())
-        print("get_node_name", self.plc.get_node_name(NODE_IDX))
-        print("get_node_location", self.plc.get_node_location(NODE_IDX))
-        print("get_grid_cell_of_node", self.plc.get_grid_cell_of_node(NODE_IDX))
-        print("get_node_location", self.plc.get_node_location(NODE_IDX))
-        print("get_macro_orientation", self.plc.get_macro_orientation(NODE_IDX))
-        print("is_node_placed", self.plc.is_node_placed(NODE_IDX))
-        print("get_source_filename", self.plc.get_source_filename())
-        print("get_blockages", self.plc.get_blockages())
-        print("get_ref_node_id", self.plc.get_ref_node_id(NODE_IDX), self.plc.get_ref_node_id(NODE_IDX))
-        print("get_node_mask\n", np.array(self.plc.get_node_mask(NODE_IDX)).reshape((4,4)))
-        print("can_place_node", self.plc.can_place_node(0, 1))
-        print("***************************************************")
-
-        
-def main(argv):
-    args = sys.argv[1:]
-    temp = CircuitDataBaseTest(args[0])
-    temp.test_proxy_congestion()
-    # temp.test_proxy_cost()
-    # temp.test_metadata()
-    # temp.test_miscellaneous()
-
-if __name__ == "__main__":
+def parse_flags(argv):
+    parser = argparse_flags.ArgumentParser(description='An argparse + app.run example')
+    parser.add_argument("--netlist", required=True,
+        help="Path to netlist in pb.txt")
+    parser.add_argument("--plc", required=False,
+        help="Path to plc in .plc")
+    parser.add_argument("--width", type=float, required=True,
+        help="Canvas width")
+    parser.add_argument("--height", type=float, required=True,
+        help="Canvas height")
+    parser.add_argument("--col", type=int, required=True,
+        help="Grid column")
+    parser.add_argument("--row", type=int, required=True,
+        help="Grid row")
+    parser.add_argument("--rpmh", type=float, default=10, required=False,
+        help="Grid row")
+    parser.add_argument("--rpmv", type=float, default=10, required=False,
+        help="Grid row")
+    parser.add_argument("--marh", type=float, default=10, required=False,
+        help="Grid row")
+    parser.add_argument("--marv", type=float, default=10, required=False,
+        help="Grid row")
+    parser.add_argument("--smooth", type=float, default=1, required=False,
+        help="Grid row")
+    return parser.parse_args(argv[1:])
+
+def main(args):
+    if args.plc:
+        PCT = PlacementCostTest(args.netlist, args.plc, args.width, args.height,
+                                args.col, args.row, args.rpmv, args.rpmv,
+                                args.marh, args.marv, args.smooth)
+    else:
+        PCT = PlacementCostTest(args.netlist, args.width, args.height,
+                                args.col, args.row, args.rpmv, args.rpmv,
+                                args.marh, args.marv, args.smooth)
+    PCT.test_metadata()
+    PCT.test_proxy_cost()
+
+if __name__ == '__main__':
+    app.run(main, flags_parser=parse_flags)
\ No newline at end of file
-  app.run(main)
\ No newline at end of file

Enablements/NanGate45/lef/fakeram45_128x116.lef

+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+MACRO fakeram45_128x116
+  FOREIGN fakeram45_128x116 0 0 ;
+  SYMMETRY X Y R90 ;
+  SIZE 121.030 BY 117.600 ;
+  CLASS BLOCK ;
+  PIN w_mask_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.065 0.070 2.135 ;
+    END
+  END w_mask_in[0]
+  PIN w_mask_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.275 0.070 2.345 ;
+    END
+  END w_mask_in[1]
+  PIN w_mask_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.485 0.070 2.555 ;
+    END
+  END w_mask_in[2]
+  PIN w_mask_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.695 0.070 2.765 ;
+    END
+  END w_mask_in[3]
+  PIN w_mask_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.905 0.070 2.975 ;
+    END
+  END w_mask_in[4]
+  PIN w_mask_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.115 0.070 3.185 ;
+    END
+  END w_mask_in[5]
+  PIN w_mask_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.325 0.070 3.395 ;
+    END
+  END w_mask_in[6]
+  PIN w_mask_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.535 0.070 3.605 ;
+    END
+  END w_mask_in[7]
+  PIN w_mask_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.745 0.070 3.815 ;
+    END
+  END w_mask_in[8]
+  PIN w_mask_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.955 0.070 4.025 ;
+    END
+  END w_mask_in[9]
+  PIN w_mask_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 4.165 0.070 4.235 ;
+    END
+  END w_mask_in[10]
+  PIN w_mask_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 4.375 0.070 4.445 ;
+    END
+  END w_mask_in[11]
+  PIN w_mask_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 4.585 0.070 4.655 ;
+    END
+  END w_mask_in[12]
+  PIN w_mask_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 4.795 0.070 4.865 ;
+    END
+  END w_mask_in[13]
+  PIN w_mask_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.005 0.070 5.075 ;
+    END
+  END w_mask_in[14]
+  PIN w_mask_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.215 0.070 5.285 ;
+    END
+  END w_mask_in[15]
+  PIN w_mask_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.425 0.070 5.495 ;
+    END
+  END w_mask_in[16]
+  PIN w_mask_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.635 0.070 5.705 ;
+    END
+  END w_mask_in[17]
+  PIN w_mask_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.845 0.070 5.915 ;
+    END
+  END w_mask_in[18]
+  PIN w_mask_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.055 0.070 6.125 ;
+    END
+  END w_mask_in[19]
+  PIN w_mask_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.265 0.070 6.335 ;
+    END
+  END w_mask_in[20]
+  PIN w_mask_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.475 0.070 6.545 ;
+    END
+  END w_mask_in[21]
+  PIN w_mask_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.685 0.070 6.755 ;
+    END
+  END w_mask_in[22]
+  PIN w_mask_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.895 0.070 6.965 ;
+    END
+  END w_mask_in[23]
+  PIN w_mask_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.105 0.070 7.175 ;
+    END
+  END w_mask_in[24]
+  PIN w_mask_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.315 0.070 7.385 ;
+    END
+  END w_mask_in[25]
+  PIN w_mask_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.525 0.070 7.595 ;
+    END
+  END w_mask_in[26]
+  PIN w_mask_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.735 0.070 7.805 ;
+    END
+  END w_mask_in[27]
+  PIN w_mask_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.945 0.070 8.015 ;
+    END
+  END w_mask_in[28]
+  PIN w_mask_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.155 0.070 8.225 ;
+    END
+  END w_mask_in[29]
+  PIN w_mask_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.365 0.070 8.435 ;
+    END
+  END w_mask_in[30]
+  PIN w_mask_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.575 0.070 8.645 ;
+    END
+  END w_mask_in[31]
+  PIN w_mask_in[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.785 0.070 8.855 ;
+    END
+  END w_mask_in[32]
+  PIN w_mask_in[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.995 0.070 9.065 ;
+    END
+  END w_mask_in[33]
+  PIN w_mask_in[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 9.205 0.070 9.275 ;
+    END
+  END w_mask_in[34]
+  PIN w_mask_in[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 9.415 0.070 9.485 ;
+    END
+  END w_mask_in[35]
+  PIN w_mask_in[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 9.625 0.070 9.695 ;
+    END
+  END w_mask_in[36]
+  PIN w_mask_in[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 9.835 0.070 9.905 ;
+    END
+  END w_mask_in[37]
+  PIN w_mask_in[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.045 0.070 10.115 ;
+    END
+  END w_mask_in[38]
+  PIN w_mask_in[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.255 0.070 10.325 ;
+    END
+  END w_mask_in[39]
+  PIN w_mask_in[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.465 0.070 10.535 ;
+    END
+  END w_mask_in[40]
+  PIN w_mask_in[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.675 0.070 10.745 ;
+    END
+  END w_mask_in[41]
+  PIN w_mask_in[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.885 0.070 10.955 ;
+    END
+  END w_mask_in[42]
+  PIN w_mask_in[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.095 0.070 11.165 ;
+    END
+  END w_mask_in[43]
+  PIN w_mask_in[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.305 0.070 11.375 ;
+    END
+  END w_mask_in[44]
+  PIN w_mask_in[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.515 0.070 11.585 ;
+    END
+  END w_mask_in[45]
+  PIN w_mask_in[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.725 0.070 11.795 ;
+    END
+  END w_mask_in[46]
+  PIN w_mask_in[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.935 0.070 12.005 ;
+    END
+  END w_mask_in[47]
+  PIN w_mask_in[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.145 0.070 12.215 ;
+    END
+  END w_mask_in[48]
+  PIN w_mask_in[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.355 0.070 12.425 ;
+    END
+  END w_mask_in[49]
+  PIN w_mask_in[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.565 0.070 12.635 ;
+    END
+  END w_mask_in[50]
+  PIN w_mask_in[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.775 0.070 12.845 ;
+    END
+  END w_mask_in[51]
+  PIN w_mask_in[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.985 0.070 13.055 ;
+    END
+  END w_mask_in[52]
+  PIN w_mask_in[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 13.195 0.070 13.265 ;
+    END
+  END w_mask_in[53]
+  PIN w_mask_in[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 13.405 0.070 13.475 ;
+    END
+  END w_mask_in[54]
+  PIN w_mask_in[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 13.615 0.070 13.685 ;
+    END
+  END w_mask_in[55]
+  PIN w_mask_in[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 13.825 0.070 13.895 ;
+    END
+  END w_mask_in[56]
+  PIN w_mask_in[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.035 0.070 14.105 ;
+    END
+  END w_mask_in[57]
+  PIN w_mask_in[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.245 0.070 14.315 ;
+    END
+  END w_mask_in[58]
+  PIN w_mask_in[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.455 0.070 14.525 ;
+    END
+  END w_mask_in[59]
+  PIN w_mask_in[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.665 0.070 14.735 ;
+    END
+  END w_mask_in[60]
+  PIN w_mask_in[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.875 0.070 14.945 ;
+    END
+  END w_mask_in[61]
+  PIN w_mask_in[62]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.085 0.070 15.155 ;
+    END
+  END w_mask_in[62]
+  PIN w_mask_in[63]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.295 0.070 15.365 ;
+    END
+  END w_mask_in[63]
+  PIN w_mask_in[64]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.505 0.070 15.575 ;
+    END
+  END w_mask_in[64]
+  PIN w_mask_in[65]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.715 0.070 15.785 ;
+    END
+  END w_mask_in[65]
+  PIN w_mask_in[66]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.925 0.070 15.995 ;
+    END
+  END w_mask_in[66]
+  PIN w_mask_in[67]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.135 0.070 16.205 ;
+    END
+  END w_mask_in[67]
+  PIN w_mask_in[68]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.345 0.070 16.415 ;
+    END
+  END w_mask_in[68]
+  PIN w_mask_in[69]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.555 0.070 16.625 ;
+    END
+  END w_mask_in[69]
+  PIN w_mask_in[70]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.765 0.070 16.835 ;
+    END
+  END w_mask_in[70]
+  PIN w_mask_in[71]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.975 0.070 17.045 ;
+    END
+  END w_mask_in[71]
+  PIN w_mask_in[72]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 17.185 0.070 17.255 ;
+    END
+  END w_mask_in[72]
+  PIN w_mask_in[73]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 17.395 0.070 17.465 ;
+    END
+  END w_mask_in[73]
+  PIN w_mask_in[74]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 17.605 0.070 17.675 ;
+    END
+  END w_mask_in[74]
+  PIN w_mask_in[75]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 17.815 0.070 17.885 ;
+    END
+  END w_mask_in[75]
+  PIN w_mask_in[76]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 18.025 0.070 18.095 ;
+    END
+  END w_mask_in[76]
+  PIN w_mask_in[77]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 18.235 0.070 18.305 ;
+    END
+  END w_mask_in[77]
+  PIN w_mask_in[78]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 18.445 0.070 18.515 ;
+    END
+  END w_mask_in[78]
+  PIN w_mask_in[79]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 18.655 0.070 18.725 ;
+    END
+  END w_mask_in[79]
+  PIN w_mask_in[80]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 18.865 0.070 18.935 ;
+    END
+  END w_mask_in[80]
+  PIN w_mask_in[81]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.075 0.070 19.145 ;
+    END
+  END w_mask_in[81]
+  PIN w_mask_in[82]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.285 0.070 19.355 ;
+    END
+  END w_mask_in[82]
+  PIN w_mask_in[83]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.495 0.070 19.565 ;
+    END
+  END w_mask_in[83]
+  PIN w_mask_in[84]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.705 0.070 19.775 ;
+    END
+  END w_mask_in[84]
+  PIN w_mask_in[85]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.915 0.070 19.985 ;
+    END
+  END w_mask_in[85]
+  PIN w_mask_in[86]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.125 0.070 20.195 ;
+    END
+  END w_mask_in[86]
+  PIN w_mask_in[87]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.335 0.070 20.405 ;
+    END
+  END w_mask_in[87]
+  PIN w_mask_in[88]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.545 0.070 20.615 ;
+    END
+  END w_mask_in[88]
+  PIN w_mask_in[89]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.755 0.070 20.825 ;
+    END
+  END w_mask_in[89]
+  PIN w_mask_in[90]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.965 0.070 21.035 ;
+    END
+  END w_mask_in[90]
+  PIN w_mask_in[91]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 21.175 0.070 21.245 ;
+    END
+  END w_mask_in[91]
+  PIN w_mask_in[92]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 21.385 0.070 21.455 ;
+    END
+  END w_mask_in[92]
+  PIN w_mask_in[93]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 21.595 0.070 21.665 ;
+    END
+  END w_mask_in[93]
+  PIN w_mask_in[94]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 21.805 0.070 21.875 ;
+    END
+  END w_mask_in[94]
+  PIN w_mask_in[95]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.015 0.070 22.085 ;
+    END
+  END w_mask_in[95]
+  PIN w_mask_in[96]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.225 0.070 22.295 ;
+    END
+  END w_mask_in[96]
+  PIN w_mask_in[97]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.435 0.070 22.505 ;
+    END
+  END w_mask_in[97]
+  PIN w_mask_in[98]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.645 0.070 22.715 ;
+    END
+  END w_mask_in[98]
+  PIN w_mask_in[99]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.855 0.070 22.925 ;
+    END
+  END w_mask_in[99]
+  PIN w_mask_in[100]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.065 0.070 23.135 ;
+    END
+  END w_mask_in[100]
+  PIN w_mask_in[101]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.275 0.070 23.345 ;
+    END
+  END w_mask_in[101]
+  PIN w_mask_in[102]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.485 0.070 23.555 ;
+    END
+  END w_mask_in[102]
+  PIN w_mask_in[103]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.695 0.070 23.765 ;
+    END
+  END w_mask_in[103]
+  PIN w_mask_in[104]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.905 0.070 23.975 ;
+    END
+  END w_mask_in[104]
+  PIN w_mask_in[105]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.115 0.070 24.185 ;
+    END
+  END w_mask_in[105]
+  PIN w_mask_in[106]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.325 0.070 24.395 ;
+    END
+  END w_mask_in[106]
+  PIN w_mask_in[107]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.535 0.070 24.605 ;
+    END
+  END w_mask_in[107]
+  PIN w_mask_in[108]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.745 0.070 24.815 ;
+    END
+  END w_mask_in[108]
+  PIN w_mask_in[109]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.955 0.070 25.025 ;
+    END
+  END w_mask_in[109]
+  PIN w_mask_in[110]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 25.165 0.070 25.235 ;
+    END
+  END w_mask_in[110]
+  PIN w_mask_in[111]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 25.375 0.070 25.445 ;
+    END
+  END w_mask_in[111]
+  PIN w_mask_in[112]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 25.585 0.070 25.655 ;
+    END
+  END w_mask_in[112]
+  PIN w_mask_in[113]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 25.795 0.070 25.865 ;
+    END
+  END w_mask_in[113]
+  PIN w_mask_in[114]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 26.005 0.070 26.075 ;
+    END
+  END w_mask_in[114]
+  PIN w_mask_in[115]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 26.215 0.070 26.285 ;
+    END
+  END w_mask_in[115]
+  PIN rd_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 35.665 0.070 35.735 ;
+    END
+  END rd_out[0]
+  PIN rd_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 35.875 0.070 35.945 ;
+    END
+  END rd_out[1]
+  PIN rd_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 36.085 0.070 36.155 ;
+    END
+  END rd_out[2]
+  PIN rd_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 36.295 0.070 36.365 ;
+    END
+  END rd_out[3]
+  PIN rd_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 36.505 0.070 36.575 ;
+    END
+  END rd_out[4]
+  PIN rd_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 36.715 0.070 36.785 ;
+    END
+  END rd_out[5]
+  PIN rd_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 36.925 0.070 36.995 ;
+    END
+  END rd_out[6]
+  PIN rd_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 37.135 0.070 37.205 ;
+    END
+  END rd_out[7]
+  PIN rd_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 37.345 0.070 37.415 ;
+    END
+  END rd_out[8]
+  PIN rd_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 37.555 0.070 37.625 ;
+    END
+  END rd_out[9]
+  PIN rd_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 37.765 0.070 37.835 ;
+    END
+  END rd_out[10]
+  PIN rd_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 37.975 0.070 38.045 ;
+    END
+  END rd_out[11]
+  PIN rd_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 38.185 0.070 38.255 ;
+    END
+  END rd_out[12]
+  PIN rd_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 38.395 0.070 38.465 ;
+    END
+  END rd_out[13]
+  PIN rd_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 38.605 0.070 38.675 ;
+    END
+  END rd_out[14]
+  PIN rd_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 38.815 0.070 38.885 ;
+    END
+  END rd_out[15]
+  PIN rd_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 39.025 0.070 39.095 ;
+    END
+  END rd_out[16]
+  PIN rd_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 39.235 0.070 39.305 ;
+    END
+  END rd_out[17]
+  PIN rd_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 39.445 0.070 39.515 ;
+    END
+  END rd_out[18]
+  PIN rd_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 39.655 0.070 39.725 ;
+    END
+  END rd_out[19]
+  PIN rd_out[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 39.865 0.070 39.935 ;
+    END
+  END rd_out[20]
+  PIN rd_out[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 40.075 0.070 40.145 ;
+    END
+  END rd_out[21]
+  PIN rd_out[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 40.285 0.070 40.355 ;
+    END
+  END rd_out[22]
+  PIN rd_out[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 40.495 0.070 40.565 ;
+    END
+  END rd_out[23]
+  PIN rd_out[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 40.705 0.070 40.775 ;
+    END
+  END rd_out[24]
+  PIN rd_out[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 40.915 0.070 40.985 ;
+    END
+  END rd_out[25]
+  PIN rd_out[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 41.125 0.070 41.195 ;
+    END
+  END rd_out[26]
+  PIN rd_out[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 41.335 0.070 41.405 ;
+    END
+  END rd_out[27]
+  PIN rd_out[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 41.545 0.070 41.615 ;
+    END
+  END rd_out[28]
+  PIN rd_out[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 41.755 0.070 41.825 ;
+    END
+  END rd_out[29]
+  PIN rd_out[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 41.965 0.070 42.035 ;
+    END
+  END rd_out[30]
+  PIN rd_out[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 42.175 0.070 42.245 ;
+    END
+  END rd_out[31]
+  PIN rd_out[32]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 42.385 0.070 42.455 ;
+    END
+  END rd_out[32]
+  PIN rd_out[33]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 42.595 0.070 42.665 ;
+    END
+  END rd_out[33]
+  PIN rd_out[34]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 42.805 0.070 42.875 ;
+    END
+  END rd_out[34]
+  PIN rd_out[35]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 43.015 0.070 43.085 ;
+    END
+  END rd_out[35]
+  PIN rd_out[36]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 43.225 0.070 43.295 ;
+    END
+  END rd_out[36]
+  PIN rd_out[37]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 43.435 0.070 43.505 ;
+    END
+  END rd_out[37]
+  PIN rd_out[38]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 43.645 0.070 43.715 ;
+    END
+  END rd_out[38]
+  PIN rd_out[39]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 43.855 0.070 43.925 ;
+    END
+  END rd_out[39]
+  PIN rd_out[40]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 44.065 0.070 44.135 ;
+    END
+  END rd_out[40]
+  PIN rd_out[41]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 44.275 0.070 44.345 ;
+    END
+  END rd_out[41]
+  PIN rd_out[42]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 44.485 0.070 44.555 ;
+    END
+  END rd_out[42]
+  PIN rd_out[43]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 44.695 0.070 44.765 ;
+    END
+  END rd_out[43]
+  PIN rd_out[44]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 44.905 0.070 44.975 ;
+    END
+  END rd_out[44]
+  PIN rd_out[45]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 45.115 0.070 45.185 ;
+    END
+  END rd_out[45]
+  PIN rd_out[46]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 45.325 0.070 45.395 ;
+    END
+  END rd_out[46]
+  PIN rd_out[47]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 45.535 0.070 45.605 ;
+    END
+  END rd_out[47]
+  PIN rd_out[48]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 45.745 0.070 45.815 ;
+    END
+  END rd_out[48]
+  PIN rd_out[49]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 45.955 0.070 46.025 ;
+    END
+  END rd_out[49]
+  PIN rd_out[50]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 46.165 0.070 46.235 ;
+    END
+  END rd_out[50]
+  PIN rd_out[51]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 46.375 0.070 46.445 ;
+    END
+  END rd_out[51]
+  PIN rd_out[52]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 46.585 0.070 46.655 ;
+    END
+  END rd_out[52]
+  PIN rd_out[53]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 46.795 0.070 46.865 ;
+    END
+  END rd_out[53]
+  PIN rd_out[54]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 47.005 0.070 47.075 ;
+    END
+  END rd_out[54]
+  PIN rd_out[55]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 47.215 0.070 47.285 ;
+    END
+  END rd_out[55]
+  PIN rd_out[56]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 47.425 0.070 47.495 ;
+    END
+  END rd_out[56]
+  PIN rd_out[57]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 47.635 0.070 47.705 ;
+    END
+  END rd_out[57]
+  PIN rd_out[58]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 47.845 0.070 47.915 ;
+    END
+  END rd_out[58]
+  PIN rd_out[59]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 48.055 0.070 48.125 ;
+    END
+  END rd_out[59]
+  PIN rd_out[60]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 48.265 0.070 48.335 ;
+    END
+  END rd_out[60]
+  PIN rd_out[61]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 48.475 0.070 48.545 ;
+    END
+  END rd_out[61]
+  PIN rd_out[62]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 48.685 0.070 48.755 ;
+    END
+  END rd_out[62]
+  PIN rd_out[63]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 48.895 0.070 48.965 ;
+    END
+  END rd_out[63]
+  PIN rd_out[64]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 49.105 0.070 49.175 ;
+    END
+  END rd_out[64]
+  PIN rd_out[65]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 49.315 0.070 49.385 ;
+    END
+  END rd_out[65]
+  PIN rd_out[66]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 49.525 0.070 49.595 ;
+    END
+  END rd_out[66]
+  PIN rd_out[67]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 49.735 0.070 49.805 ;
+    END
+  END rd_out[67]
+  PIN rd_out[68]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 49.945 0.070 50.015 ;
+    END
+  END rd_out[68]
+  PIN rd_out[69]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 50.155 0.070 50.225 ;
+    END
+  END rd_out[69]
+  PIN rd_out[70]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 50.365 0.070 50.435 ;
+    END
+  END rd_out[70]
+  PIN rd_out[71]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 50.575 0.070 50.645 ;
+    END
+  END rd_out[71]
+  PIN rd_out[72]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 50.785 0.070 50.855 ;
+    END
+  END rd_out[72]
+  PIN rd_out[73]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 50.995 0.070 51.065 ;
+    END
+  END rd_out[73]
+  PIN rd_out[74]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 51.205 0.070 51.275 ;
+    END
+  END rd_out[74]
+  PIN rd_out[75]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 51.415 0.070 51.485 ;
+    END
+  END rd_out[75]
+  PIN rd_out[76]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 51.625 0.070 51.695 ;
+    END
+  END rd_out[76]
+  PIN rd_out[77]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 51.835 0.070 51.905 ;
+    END
+  END rd_out[77]
+  PIN rd_out[78]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 52.045 0.070 52.115 ;
+    END
+  END rd_out[78]
+  PIN rd_out[79]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 52.255 0.070 52.325 ;
+    END
+  END rd_out[79]
+  PIN rd_out[80]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 52.465 0.070 52.535 ;
+    END
+  END rd_out[80]
+  PIN rd_out[81]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 52.675 0.070 52.745 ;
+    END
+  END rd_out[81]
+  PIN rd_out[82]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 52.885 0.070 52.955 ;
+    END
+  END rd_out[82]
+  PIN rd_out[83]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 53.095 0.070 53.165 ;
+    END
+  END rd_out[83]
+  PIN rd_out[84]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 53.305 0.070 53.375 ;
+    END
+  END rd_out[84]
+  PIN rd_out[85]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 53.515 0.070 53.585 ;
+    END
+  END rd_out[85]
+  PIN rd_out[86]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 53.725 0.070 53.795 ;
+    END
+  END rd_out[86]
+  PIN rd_out[87]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 53.935 0.070 54.005 ;
+    END
+  END rd_out[87]
+  PIN rd_out[88]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 54.145 0.070 54.215 ;
+    END
+  END rd_out[88]
+  PIN rd_out[89]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 54.355 0.070 54.425 ;
+    END
+  END rd_out[89]
+  PIN rd_out[90]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 54.565 0.070 54.635 ;
+    END
+  END rd_out[90]
+  PIN rd_out[91]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 54.775 0.070 54.845 ;
+    END
+  END rd_out[91]
+  PIN rd_out[92]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 54.985 0.070 55.055 ;
+    END
+  END rd_out[92]
+  PIN rd_out[93]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 55.195 0.070 55.265 ;
+    END
+  END rd_out[93]
+  PIN rd_out[94]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 55.405 0.070 55.475 ;
+    END
+  END rd_out[94]
+  PIN rd_out[95]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 55.615 0.070 55.685 ;
+    END
+  END rd_out[95]
+  PIN rd_out[96]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 55.825 0.070 55.895 ;
+    END
+  END rd_out[96]
+  PIN rd_out[97]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 56.035 0.070 56.105 ;
+    END
+  END rd_out[97]
+  PIN rd_out[98]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 56.245 0.070 56.315 ;
+    END
+  END rd_out[98]
+  PIN rd_out[99]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 56.455 0.070 56.525 ;
+    END
+  END rd_out[99]
+  PIN rd_out[100]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 56.665 0.070 56.735 ;
+    END
+  END rd_out[100]
+  PIN rd_out[101]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 56.875 0.070 56.945 ;
+    END
+  END rd_out[101]
+  PIN rd_out[102]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 57.085 0.070 57.155 ;
+    END
+  END rd_out[102]
+  PIN rd_out[103]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 57.295 0.070 57.365 ;
+    END
+  END rd_out[103]
+  PIN rd_out[104]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 57.505 0.070 57.575 ;
+    END
+  END rd_out[104]
+  PIN rd_out[105]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 57.715 0.070 57.785 ;
+    END
+  END rd_out[105]
+  PIN rd_out[106]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 57.925 0.070 57.995 ;
+    END
+  END rd_out[106]
+  PIN rd_out[107]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 58.135 0.070 58.205 ;
+    END
+  END rd_out[107]
+  PIN rd_out[108]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 58.345 0.070 58.415 ;
+    END
+  END rd_out[108]
+  PIN rd_out[109]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 58.555 0.070 58.625 ;
+    END
+  END rd_out[109]
+  PIN rd_out[110]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 58.765 0.070 58.835 ;
+    END
+  END rd_out[110]
+  PIN rd_out[111]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 58.975 0.070 59.045 ;
+    END
+  END rd_out[111]
+  PIN rd_out[112]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 59.185 0.070 59.255 ;
+    END
+  END rd_out[112]
+  PIN rd_out[113]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 59.395 0.070 59.465 ;
+    END
+  END rd_out[113]
+  PIN rd_out[114]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 59.605 0.070 59.675 ;
+    END
+  END rd_out[114]
+  PIN rd_out[115]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 59.815 0.070 59.885 ;
+    END
+  END rd_out[115]
+  PIN wd_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 69.265 0.070 69.335 ;
+    END
+  END wd_in[0]
+  PIN wd_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 69.475 0.070 69.545 ;
+    END
+  END wd_in[1]
+  PIN wd_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 69.685 0.070 69.755 ;
+    END
+  END wd_in[2]
+  PIN wd_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 69.895 0.070 69.965 ;
+    END
+  END wd_in[3]
+  PIN wd_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 70.105 0.070 70.175 ;
+    END
+  END wd_in[4]
+  PIN wd_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 70.315 0.070 70.385 ;
+    END
+  END wd_in[5]
+  PIN wd_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 70.525 0.070 70.595 ;
+    END
+  END wd_in[6]
+  PIN wd_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 70.735 0.070 70.805 ;
+    END
+  END wd_in[7]
+  PIN wd_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 70.945 0.070 71.015 ;
+    END
+  END wd_in[8]
+  PIN wd_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 71.155 0.070 71.225 ;
+    END
+  END wd_in[9]
+  PIN wd_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 71.365 0.070 71.435 ;
+    END
+  END wd_in[10]
+  PIN wd_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 71.575 0.070 71.645 ;
+    END
+  END wd_in[11]
+  PIN wd_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 71.785 0.070 71.855 ;
+    END
+  END wd_in[12]
+  PIN wd_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 71.995 0.070 72.065 ;
+    END
+  END wd_in[13]
+  PIN wd_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 72.205 0.070 72.275 ;
+    END
+  END wd_in[14]
+  PIN wd_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 72.415 0.070 72.485 ;
+    END
+  END wd_in[15]
+  PIN wd_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 72.625 0.070 72.695 ;
+    END
+  END wd_in[16]
+  PIN wd_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 72.835 0.070 72.905 ;
+    END
+  END wd_in[17]
+  PIN wd_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 73.045 0.070 73.115 ;
+    END
+  END wd_in[18]
+  PIN wd_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 73.255 0.070 73.325 ;
+    END
+  END wd_in[19]
+  PIN wd_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 73.465 0.070 73.535 ;
+    END
+  END wd_in[20]
+  PIN wd_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 73.675 0.070 73.745 ;
+    END
+  END wd_in[21]
+  PIN wd_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 73.885 0.070 73.955 ;
+    END
+  END wd_in[22]
+  PIN wd_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 74.095 0.070 74.165 ;
+    END
+  END wd_in[23]
+  PIN wd_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 74.305 0.070 74.375 ;
+    END
+  END wd_in[24]
+  PIN wd_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 74.515 0.070 74.585 ;
+    END
+  END wd_in[25]
+  PIN wd_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 74.725 0.070 74.795 ;
+    END
+  END wd_in[26]
+  PIN wd_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 74.935 0.070 75.005 ;
+    END
+  END wd_in[27]
+  PIN wd_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 75.145 0.070 75.215 ;
+    END
+  END wd_in[28]
+  PIN wd_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 75.355 0.070 75.425 ;
+    END
+  END wd_in[29]
+  PIN wd_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 75.565 0.070 75.635 ;
+    END
+  END wd_in[30]
+  PIN wd_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 75.775 0.070 75.845 ;
+    END
+  END wd_in[31]
+  PIN wd_in[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 75.985 0.070 76.055 ;
+    END
+  END wd_in[32]
+  PIN wd_in[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 76.195 0.070 76.265 ;
+    END
+  END wd_in[33]
+  PIN wd_in[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 76.405 0.070 76.475 ;
+    END
+  END wd_in[34]
+  PIN wd_in[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 76.615 0.070 76.685 ;
+    END
+  END wd_in[35]
+  PIN wd_in[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 76.825 0.070 76.895 ;
+    END
+  END wd_in[36]
+  PIN wd_in[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 77.035 0.070 77.105 ;
+    END
+  END wd_in[37]
+  PIN wd_in[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 77.245 0.070 77.315 ;
+    END
+  END wd_in[38]
+  PIN wd_in[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 77.455 0.070 77.525 ;
+    END
+  END wd_in[39]
+  PIN wd_in[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 77.665 0.070 77.735 ;
+    END
+  END wd_in[40]
+  PIN wd_in[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 77.875 0.070 77.945 ;
+    END
+  END wd_in[41]
+  PIN wd_in[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 78.085 0.070 78.155 ;
+    END
+  END wd_in[42]
+  PIN wd_in[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 78.295 0.070 78.365 ;
+    END
+  END wd_in[43]
+  PIN wd_in[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 78.505 0.070 78.575 ;
+    END
+  END wd_in[44]
+  PIN wd_in[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 78.715 0.070 78.785 ;
+    END
+  END wd_in[45]
+  PIN wd_in[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 78.925 0.070 78.995 ;
+    END
+  END wd_in[46]
+  PIN wd_in[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 79.135 0.070 79.205 ;
+    END
+  END wd_in[47]
+  PIN wd_in[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 79.345 0.070 79.415 ;
+    END
+  END wd_in[48]
+  PIN wd_in[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 79.555 0.070 79.625 ;
+    END
+  END wd_in[49]
+  PIN wd_in[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 79.765 0.070 79.835 ;
+    END
+  END wd_in[50]
+  PIN wd_in[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 79.975 0.070 80.045 ;
+    END
+  END wd_in[51]
+  PIN wd_in[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 80.185 0.070 80.255 ;
+    END
+  END wd_in[52]
+  PIN wd_in[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 80.395 0.070 80.465 ;
+    END
+  END wd_in[53]
+  PIN wd_in[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 80.605 0.070 80.675 ;
+    END
+  END wd_in[54]
+  PIN wd_in[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 80.815 0.070 80.885 ;
+    END
+  END wd_in[55]
+  PIN wd_in[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 81.025 0.070 81.095 ;
+    END
+  END wd_in[56]
+  PIN wd_in[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 81.235 0.070 81.305 ;
+    END
+  END wd_in[57]
+  PIN wd_in[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 81.445 0.070 81.515 ;
+    END
+  END wd_in[58]
+  PIN wd_in[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 81.655 0.070 81.725 ;
+    END
+  END wd_in[59]
+  PIN wd_in[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 81.865 0.070 81.935 ;
+    END
+  END wd_in[60]
+  PIN wd_in[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 82.075 0.070 82.145 ;
+    END
+  END wd_in[61]
+  PIN wd_in[62]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 82.285 0.070 82.355 ;
+    END
+  END wd_in[62]
+  PIN wd_in[63]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 82.495 0.070 82.565 ;
+    END
+  END wd_in[63]
+  PIN wd_in[64]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 82.705 0.070 82.775 ;
+    END
+  END wd_in[64]
+  PIN wd_in[65]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 82.915 0.070 82.985 ;
+    END
+  END wd_in[65]
+  PIN wd_in[66]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 83.125 0.070 83.195 ;
+    END
+  END wd_in[66]
+  PIN wd_in[67]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 83.335 0.070 83.405 ;
+    END
+  END wd_in[67]
+  PIN wd_in[68]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 83.545 0.070 83.615 ;
+    END
+  END wd_in[68]
+  PIN wd_in[69]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 83.755 0.070 83.825 ;
+    END
+  END wd_in[69]
+  PIN wd_in[70]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 83.965 0.070 84.035 ;
+    END
+  END wd_in[70]
+  PIN wd_in[71]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 84.175 0.070 84.245 ;
+    END
+  END wd_in[71]
+  PIN wd_in[72]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 84.385 0.070 84.455 ;
+    END
+  END wd_in[72]
+  PIN wd_in[73]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 84.595 0.070 84.665 ;
+    END
+  END wd_in[73]
+  PIN wd_in[74]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 84.805 0.070 84.875 ;
+    END
+  END wd_in[74]
+  PIN wd_in[75]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 85.015 0.070 85.085 ;
+    END
+  END wd_in[75]
+  PIN wd_in[76]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 85.225 0.070 85.295 ;
+    END
+  END wd_in[76]
+  PIN wd_in[77]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 85.435 0.070 85.505 ;
+    END
+  END wd_in[77]
+  PIN wd_in[78]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 85.645 0.070 85.715 ;
+    END
+  END wd_in[78]
+  PIN wd_in[79]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 85.855 0.070 85.925 ;
+    END
+  END wd_in[79]
+  PIN wd_in[80]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 86.065 0.070 86.135 ;
+    END
+  END wd_in[80]
+  PIN wd_in[81]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 86.275 0.070 86.345 ;
+    END
+  END wd_in[81]
+  PIN wd_in[82]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 86.485 0.070 86.555 ;
+    END
+  END wd_in[82]
+  PIN wd_in[83]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 86.695 0.070 86.765 ;
+    END
+  END wd_in[83]
+  PIN wd_in[84]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 86.905 0.070 86.975 ;
+    END
+  END wd_in[84]
+  PIN wd_in[85]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 87.115 0.070 87.185 ;
+    END
+  END wd_in[85]
+  PIN wd_in[86]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 87.325 0.070 87.395 ;
+    END
+  END wd_in[86]
+  PIN wd_in[87]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 87.535 0.070 87.605 ;
+    END
+  END wd_in[87]
+  PIN wd_in[88]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 87.745 0.070 87.815 ;
+    END
+  END wd_in[88]
+  PIN wd_in[89]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 87.955 0.070 88.025 ;
+    END
+  END wd_in[89]
+  PIN wd_in[90]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 88.165 0.070 88.235 ;
+    END
+  END wd_in[90]
+  PIN wd_in[91]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 88.375 0.070 88.445 ;
+    END
+  END wd_in[91]
+  PIN wd_in[92]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 88.585 0.070 88.655 ;
+    END
+  END wd_in[92]
+  PIN wd_in[93]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 88.795 0.070 88.865 ;
+    END
+  END wd_in[93]
+  PIN wd_in[94]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 89.005 0.070 89.075 ;
+    END
+  END wd_in[94]
+  PIN wd_in[95]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 89.215 0.070 89.285 ;
+    END
+  END wd_in[95]
+  PIN wd_in[96]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 89.425 0.070 89.495 ;
+    END
+  END wd_in[96]
+  PIN wd_in[97]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 89.635 0.070 89.705 ;
+    END
+  END wd_in[97]
+  PIN wd_in[98]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 89.845 0.070 89.915 ;
+    END
+  END wd_in[98]
+  PIN wd_in[99]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 90.055 0.070 90.125 ;
+    END
+  END wd_in[99]
+  PIN wd_in[100]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 90.265 0.070 90.335 ;
+    END
+  END wd_in[100]
+  PIN wd_in[101]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 90.475 0.070 90.545 ;
+    END
+  END wd_in[101]
+  PIN wd_in[102]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 90.685 0.070 90.755 ;
+    END
+  END wd_in[102]
+  PIN wd_in[103]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 90.895 0.070 90.965 ;
+    END
+  END wd_in[103]
+  PIN wd_in[104]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 91.105 0.070 91.175 ;
+    END
+  END wd_in[104]
+  PIN wd_in[105]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 91.315 0.070 91.385 ;
+    END
+  END wd_in[105]
+  PIN wd_in[106]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 91.525 0.070 91.595 ;
+    END
+  END wd_in[106]
+  PIN wd_in[107]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 91.735 0.070 91.805 ;
+    END
+  END wd_in[107]
+  PIN wd_in[108]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 91.945 0.070 92.015 ;
+    END
+  END wd_in[108]
+  PIN wd_in[109]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 92.155 0.070 92.225 ;
+    END
+  END wd_in[109]
+  PIN wd_in[110]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 92.365 0.070 92.435 ;
+    END
+  END wd_in[110]
+  PIN wd_in[111]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 92.575 0.070 92.645 ;
+    END
+  END wd_in[111]
+  PIN wd_in[112]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 92.785 0.070 92.855 ;
+    END
+  END wd_in[112]
+  PIN wd_in[113]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 92.995 0.070 93.065 ;
+    END
+  END wd_in[113]
+  PIN wd_in[114]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 93.205 0.070 93.275 ;
+    END
+  END wd_in[114]
+  PIN wd_in[115]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 93.415 0.070 93.485 ;
+    END
+  END wd_in[115]
+  PIN addr_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 102.865 0.070 102.935 ;
+    END
+  END addr_in[0]
+  PIN addr_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 103.075 0.070 103.145 ;
+    END
+  END addr_in[1]
+  PIN addr_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 103.285 0.070 103.355 ;
+    END
+  END addr_in[2]
+  PIN addr_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 103.495 0.070 103.565 ;
+    END
+  END addr_in[3]
+  PIN addr_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 103.705 0.070 103.775 ;
+    END
+  END addr_in[4]
+  PIN addr_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 103.915 0.070 103.985 ;
+    END
+  END addr_in[5]
+  PIN addr_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 104.125 0.070 104.195 ;
+    END
+  END addr_in[6]
+  PIN we_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 113.575 0.070 113.645 ;
+    END
+  END we_in
+  PIN ce_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 113.785 0.070 113.855 ;
+    END
+  END ce_in
+  PIN clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 113.995 0.070 114.065 ;
+    END
+  END clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER metal4 ;
+      RECT 1.960 2.100 2.240 115.500 ;
+      RECT 5.320 2.100 5.600 115.500 ;
+      RECT 8.680 2.100 8.960 115.500 ;
+      RECT 12.040 2.100 12.320 115.500 ;
+      RECT 15.400 2.100 15.680 115.500 ;
+      RECT 18.760 2.100 19.040 115.500 ;
+      RECT 22.120 2.100 22.400 115.500 ;
+      RECT 25.480 2.100 25.760 115.500 ;
+      RECT 28.840 2.100 29.120 115.500 ;
+      RECT 32.200 2.100 32.480 115.500 ;
+      RECT 35.560 2.100 35.840 115.500 ;
+      RECT 38.920 2.100 39.200 115.500 ;
+      RECT 42.280 2.100 42.560 115.500 ;
+      RECT 45.640 2.100 45.920 115.500 ;
+      RECT 49.000 2.100 49.280 115.500 ;
+      RECT 52.360 2.100 52.640 115.500 ;
+      RECT 55.720 2.100 56.000 115.500 ;
+      RECT 59.080 2.100 59.360 115.500 ;
+      RECT 62.440 2.100 62.720 115.500 ;
+      RECT 65.800 2.100 66.080 115.500 ;
+      RECT 69.160 2.100 69.440 115.500 ;
+      RECT 72.520 2.100 72.800 115.500 ;
+      RECT 75.880 2.100 76.160 115.500 ;
+      RECT 79.240 2.100 79.520 115.500 ;
+      RECT 82.600 2.100 82.880 115.500 ;
+      RECT 85.960 2.100 86.240 115.500 ;
+      RECT 89.320 2.100 89.600 115.500 ;
+      RECT 92.680 2.100 92.960 115.500 ;
+      RECT 96.040 2.100 96.320 115.500 ;
+      RECT 99.400 2.100 99.680 115.500 ;
+      RECT 102.760 2.100 103.040 115.500 ;
+      RECT 106.120 2.100 106.400 115.500 ;
+      RECT 109.480 2.100 109.760 115.500 ;
+      RECT 112.840 2.100 113.120 115.500 ;
+      RECT 116.200 2.100 116.480 115.500 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER metal4 ;
+      RECT 3.640 2.100 3.920 115.500 ;
+      RECT 7.000 2.100 7.280 115.500 ;
+      RECT 10.360 2.100 10.640 115.500 ;
+      RECT 13.720 2.100 14.000 115.500 ;
+      RECT 17.080 2.100 17.360 115.500 ;
+      RECT 20.440 2.100 20.720 115.500 ;
+      RECT 23.800 2.100 24.080 115.500 ;
+      RECT 27.160 2.100 27.440 115.500 ;
+      RECT 30.520 2.100 30.800 115.500 ;
+      RECT 33.880 2.100 34.160 115.500 ;
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+    END
+  END VDD
+  OBS
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+    LAYER metal4 ;
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+    RECT 87.920 2.100 89.320 115.500 ;
+    RECT 89.600 2.100 91.000 115.500 ;
+    RECT 91.280 2.100 92.680 115.500 ;
+    RECT 92.960 2.100 94.360 115.500 ;
+    RECT 94.640 2.100 96.040 115.500 ;
+    RECT 96.320 2.100 97.720 115.500 ;
+    RECT 98.000 2.100 99.400 115.500 ;
+    RECT 99.680 2.100 101.080 115.500 ;
+    RECT 101.360 2.100 102.760 115.500 ;
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+    RECT 104.720 2.100 106.120 115.500 ;
+    RECT 106.400 2.100 107.800 115.500 ;
+    RECT 108.080 2.100 109.480 115.500 ;
+    RECT 109.760 2.100 111.160 115.500 ;
+    RECT 111.440 2.100 112.840 115.500 ;
+    RECT 113.120 2.100 114.520 115.500 ;
+    RECT 114.800 2.100 116.200 115.500 ;
+    RECT 116.480 2.100 117.880 115.500 ;
+    RECT 118.160 2.100 121.030 115.500 ;
+    LAYER OVERLAP ;
+    RECT 0 0 121.030 117.600 ;
+  END
+END fakeram45_128x116
+
+END LIBRARY

Enablements/NanGate45/lef/fakeram45_256x48.lef

+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+MACRO fakeram45_256x48
+  FOREIGN fakeram45_256x48 0 0 ;
+  SYMMETRY X Y R90 ;
+  SIZE 64.030 BY 207.200 ;
+  CLASS BLOCK ;
+  PIN w_mask_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.065 0.070 2.135 ;
+    END
+  END w_mask_in[0]
+  PIN w_mask_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.325 0.070 3.395 ;
+    END
+  END w_mask_in[1]
+  PIN w_mask_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 4.585 0.070 4.655 ;
+    END
+  END w_mask_in[2]
+  PIN w_mask_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.845 0.070 5.915 ;
+    END
+  END w_mask_in[3]
+  PIN w_mask_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.105 0.070 7.175 ;
+    END
+  END w_mask_in[4]
+  PIN w_mask_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.365 0.070 8.435 ;
+    END
+  END w_mask_in[5]
+  PIN w_mask_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 9.625 0.070 9.695 ;
+    END
+  END w_mask_in[6]
+  PIN w_mask_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.885 0.070 10.955 ;
+    END
+  END w_mask_in[7]
+  PIN w_mask_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.145 0.070 12.215 ;
+    END
+  END w_mask_in[8]
+  PIN w_mask_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 13.405 0.070 13.475 ;
+    END
+  END w_mask_in[9]
+  PIN w_mask_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.665 0.070 14.735 ;
+    END
+  END w_mask_in[10]
+  PIN w_mask_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.925 0.070 15.995 ;
+    END
+  END w_mask_in[11]
+  PIN w_mask_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 17.185 0.070 17.255 ;
+    END
+  END w_mask_in[12]
+  PIN w_mask_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 18.445 0.070 18.515 ;
+    END
+  END w_mask_in[13]
+  PIN w_mask_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.705 0.070 19.775 ;
+    END
+  END w_mask_in[14]
+  PIN w_mask_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.965 0.070 21.035 ;
+    END
+  END w_mask_in[15]
+  PIN w_mask_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.225 0.070 22.295 ;
+    END
+  END w_mask_in[16]
+  PIN w_mask_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.485 0.070 23.555 ;
+    END
+  END w_mask_in[17]
+  PIN w_mask_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.745 0.070 24.815 ;
+    END
+  END w_mask_in[18]
+  PIN w_mask_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 26.005 0.070 26.075 ;
+    END
+  END w_mask_in[19]
+  PIN w_mask_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 27.265 0.070 27.335 ;
+    END
+  END w_mask_in[20]
+  PIN w_mask_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 28.525 0.070 28.595 ;
+    END
+  END w_mask_in[21]
+  PIN w_mask_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 29.785 0.070 29.855 ;
+    END
+  END w_mask_in[22]
+  PIN w_mask_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 31.045 0.070 31.115 ;
+    END
+  END w_mask_in[23]
+  PIN w_mask_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 32.305 0.070 32.375 ;
+    END
+  END w_mask_in[24]
+  PIN w_mask_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 33.565 0.070 33.635 ;
+    END
+  END w_mask_in[25]
+  PIN w_mask_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 34.825 0.070 34.895 ;
+    END
+  END w_mask_in[26]
+  PIN w_mask_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 36.085 0.070 36.155 ;
+    END
+  END w_mask_in[27]
+  PIN w_mask_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 37.345 0.070 37.415 ;
+    END
+  END w_mask_in[28]
+  PIN w_mask_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 38.605 0.070 38.675 ;
+    END
+  END w_mask_in[29]
+  PIN w_mask_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 39.865 0.070 39.935 ;
+    END
+  END w_mask_in[30]
+  PIN w_mask_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 41.125 0.070 41.195 ;
+    END
+  END w_mask_in[31]
+  PIN w_mask_in[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 42.385 0.070 42.455 ;
+    END
+  END w_mask_in[32]
+  PIN w_mask_in[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 43.645 0.070 43.715 ;
+    END
+  END w_mask_in[33]
+  PIN w_mask_in[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 44.905 0.070 44.975 ;
+    END
+  END w_mask_in[34]
+  PIN w_mask_in[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 46.165 0.070 46.235 ;
+    END
+  END w_mask_in[35]
+  PIN w_mask_in[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 47.425 0.070 47.495 ;
+    END
+  END w_mask_in[36]
+  PIN w_mask_in[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 48.685 0.070 48.755 ;
+    END
+  END w_mask_in[37]
+  PIN w_mask_in[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 49.945 0.070 50.015 ;
+    END
+  END w_mask_in[38]
+  PIN w_mask_in[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 51.205 0.070 51.275 ;
+    END
+  END w_mask_in[39]
+  PIN w_mask_in[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 52.465 0.070 52.535 ;
+    END
+  END w_mask_in[40]
+  PIN w_mask_in[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 53.725 0.070 53.795 ;
+    END
+  END w_mask_in[41]
+  PIN w_mask_in[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 54.985 0.070 55.055 ;
+    END
+  END w_mask_in[42]
+  PIN w_mask_in[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 56.245 0.070 56.315 ;
+    END
+  END w_mask_in[43]
+  PIN w_mask_in[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 57.505 0.070 57.575 ;
+    END
+  END w_mask_in[44]
+  PIN w_mask_in[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 58.765 0.070 58.835 ;
+    END
+  END w_mask_in[45]
+  PIN w_mask_in[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 60.025 0.070 60.095 ;
+    END
+  END w_mask_in[46]
+  PIN w_mask_in[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 61.285 0.070 61.355 ;
+    END
+  END w_mask_in[47]
+  PIN rd_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 63.175 0.070 63.245 ;
+    END
+  END rd_out[0]
+  PIN rd_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 64.435 0.070 64.505 ;
+    END
+  END rd_out[1]
+  PIN rd_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 65.695 0.070 65.765 ;
+    END
+  END rd_out[2]
+  PIN rd_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 66.955 0.070 67.025 ;
+    END
+  END rd_out[3]
+  PIN rd_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 68.215 0.070 68.285 ;
+    END
+  END rd_out[4]
+  PIN rd_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 69.475 0.070 69.545 ;
+    END
+  END rd_out[5]
+  PIN rd_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 70.735 0.070 70.805 ;
+    END
+  END rd_out[6]
+  PIN rd_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 71.995 0.070 72.065 ;
+    END
+  END rd_out[7]
+  PIN rd_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 73.255 0.070 73.325 ;
+    END
+  END rd_out[8]
+  PIN rd_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 74.515 0.070 74.585 ;
+    END
+  END rd_out[9]
+  PIN rd_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 75.775 0.070 75.845 ;
+    END
+  END rd_out[10]
+  PIN rd_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 77.035 0.070 77.105 ;
+    END
+  END rd_out[11]
+  PIN rd_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 78.295 0.070 78.365 ;
+    END
+  END rd_out[12]
+  PIN rd_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 79.555 0.070 79.625 ;
+    END
+  END rd_out[13]
+  PIN rd_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 80.815 0.070 80.885 ;
+    END
+  END rd_out[14]
+  PIN rd_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 82.075 0.070 82.145 ;
+    END
+  END rd_out[15]
+  PIN rd_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 83.335 0.070 83.405 ;
+    END
+  END rd_out[16]
+  PIN rd_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 84.595 0.070 84.665 ;
+    END
+  END rd_out[17]
+  PIN rd_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 85.855 0.070 85.925 ;
+    END
+  END rd_out[18]
+  PIN rd_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 87.115 0.070 87.185 ;
+    END
+  END rd_out[19]
+  PIN rd_out[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 88.375 0.070 88.445 ;
+    END
+  END rd_out[20]
+  PIN rd_out[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 89.635 0.070 89.705 ;
+    END
+  END rd_out[21]
+  PIN rd_out[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 90.895 0.070 90.965 ;
+    END
+  END rd_out[22]
+  PIN rd_out[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 92.155 0.070 92.225 ;
+    END
+  END rd_out[23]
+  PIN rd_out[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 93.415 0.070 93.485 ;
+    END
+  END rd_out[24]
+  PIN rd_out[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 94.675 0.070 94.745 ;
+    END
+  END rd_out[25]
+  PIN rd_out[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 95.935 0.070 96.005 ;
+    END
+  END rd_out[26]
+  PIN rd_out[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 97.195 0.070 97.265 ;
+    END
+  END rd_out[27]
+  PIN rd_out[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 98.455 0.070 98.525 ;
+    END
+  END rd_out[28]
+  PIN rd_out[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 99.715 0.070 99.785 ;
+    END
+  END rd_out[29]
+  PIN rd_out[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 100.975 0.070 101.045 ;
+    END
+  END rd_out[30]
+  PIN rd_out[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 102.235 0.070 102.305 ;
+    END
+  END rd_out[31]
+  PIN rd_out[32]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 103.495 0.070 103.565 ;
+    END
+  END rd_out[32]
+  PIN rd_out[33]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 104.755 0.070 104.825 ;
+    END
+  END rd_out[33]
+  PIN rd_out[34]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 106.015 0.070 106.085 ;
+    END
+  END rd_out[34]
+  PIN rd_out[35]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 107.275 0.070 107.345 ;
+    END
+  END rd_out[35]
+  PIN rd_out[36]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 108.535 0.070 108.605 ;
+    END
+  END rd_out[36]
+  PIN rd_out[37]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 109.795 0.070 109.865 ;
+    END
+  END rd_out[37]
+  PIN rd_out[38]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 111.055 0.070 111.125 ;
+    END
+  END rd_out[38]
+  PIN rd_out[39]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 112.315 0.070 112.385 ;
+    END
+  END rd_out[39]
+  PIN rd_out[40]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 113.575 0.070 113.645 ;
+    END
+  END rd_out[40]
+  PIN rd_out[41]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 114.835 0.070 114.905 ;
+    END
+  END rd_out[41]
+  PIN rd_out[42]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 116.095 0.070 116.165 ;
+    END
+  END rd_out[42]
+  PIN rd_out[43]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 117.355 0.070 117.425 ;
+    END
+  END rd_out[43]
+  PIN rd_out[44]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 118.615 0.070 118.685 ;
+    END
+  END rd_out[44]
+  PIN rd_out[45]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 119.875 0.070 119.945 ;
+    END
+  END rd_out[45]
+  PIN rd_out[46]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 121.135 0.070 121.205 ;
+    END
+  END rd_out[46]
+  PIN rd_out[47]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 122.395 0.070 122.465 ;
+    END
+  END rd_out[47]
+  PIN wd_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 124.285 0.070 124.355 ;
+    END
+  END wd_in[0]
+  PIN wd_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 125.545 0.070 125.615 ;
+    END
+  END wd_in[1]
+  PIN wd_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 126.805 0.070 126.875 ;
+    END
+  END wd_in[2]
+  PIN wd_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 128.065 0.070 128.135 ;
+    END
+  END wd_in[3]
+  PIN wd_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 129.325 0.070 129.395 ;
+    END
+  END wd_in[4]
+  PIN wd_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 130.585 0.070 130.655 ;
+    END
+  END wd_in[5]
+  PIN wd_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 131.845 0.070 131.915 ;
+    END
+  END wd_in[6]
+  PIN wd_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 133.105 0.070 133.175 ;
+    END
+  END wd_in[7]
+  PIN wd_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 134.365 0.070 134.435 ;
+    END
+  END wd_in[8]
+  PIN wd_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 135.625 0.070 135.695 ;
+    END
+  END wd_in[9]
+  PIN wd_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 136.885 0.070 136.955 ;
+    END
+  END wd_in[10]
+  PIN wd_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 138.145 0.070 138.215 ;
+    END
+  END wd_in[11]
+  PIN wd_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 139.405 0.070 139.475 ;
+    END
+  END wd_in[12]
+  PIN wd_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 140.665 0.070 140.735 ;
+    END
+  END wd_in[13]
+  PIN wd_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 141.925 0.070 141.995 ;
+    END
+  END wd_in[14]
+  PIN wd_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 143.185 0.070 143.255 ;
+    END
+  END wd_in[15]
+  PIN wd_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 144.445 0.070 144.515 ;
+    END
+  END wd_in[16]
+  PIN wd_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 145.705 0.070 145.775 ;
+    END
+  END wd_in[17]
+  PIN wd_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 146.965 0.070 147.035 ;
+    END
+  END wd_in[18]
+  PIN wd_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 148.225 0.070 148.295 ;
+    END
+  END wd_in[19]
+  PIN wd_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 149.485 0.070 149.555 ;
+    END
+  END wd_in[20]
+  PIN wd_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 150.745 0.070 150.815 ;
+    END
+  END wd_in[21]
+  PIN wd_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 152.005 0.070 152.075 ;
+    END
+  END wd_in[22]
+  PIN wd_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 153.265 0.070 153.335 ;
+    END
+  END wd_in[23]
+  PIN wd_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 154.525 0.070 154.595 ;
+    END
+  END wd_in[24]
+  PIN wd_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 155.785 0.070 155.855 ;
+    END
+  END wd_in[25]
+  PIN wd_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 157.045 0.070 157.115 ;
+    END
+  END wd_in[26]
+  PIN wd_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 158.305 0.070 158.375 ;
+    END
+  END wd_in[27]
+  PIN wd_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 159.565 0.070 159.635 ;
+    END
+  END wd_in[28]
+  PIN wd_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 160.825 0.070 160.895 ;
+    END
+  END wd_in[29]
+  PIN wd_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 162.085 0.070 162.155 ;
+    END
+  END wd_in[30]
+  PIN wd_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 163.345 0.070 163.415 ;
+    END
+  END wd_in[31]
+  PIN wd_in[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 164.605 0.070 164.675 ;
+    END
+  END wd_in[32]
+  PIN wd_in[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 165.865 0.070 165.935 ;
+    END
+  END wd_in[33]
+  PIN wd_in[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 167.125 0.070 167.195 ;
+    END
+  END wd_in[34]
+  PIN wd_in[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 168.385 0.070 168.455 ;
+    END
+  END wd_in[35]
+  PIN wd_in[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 169.645 0.070 169.715 ;
+    END
+  END wd_in[36]
+  PIN wd_in[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 170.905 0.070 170.975 ;
+    END
+  END wd_in[37]
+  PIN wd_in[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 172.165 0.070 172.235 ;
+    END
+  END wd_in[38]
+  PIN wd_in[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 173.425 0.070 173.495 ;
+    END
+  END wd_in[39]
+  PIN wd_in[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 174.685 0.070 174.755 ;
+    END
+  END wd_in[40]
+  PIN wd_in[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 175.945 0.070 176.015 ;
+    END
+  END wd_in[41]
+  PIN wd_in[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 177.205 0.070 177.275 ;
+    END
+  END wd_in[42]
+  PIN wd_in[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 178.465 0.070 178.535 ;
+    END
+  END wd_in[43]
+  PIN wd_in[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 179.725 0.070 179.795 ;
+    END
+  END wd_in[44]
+  PIN wd_in[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 180.985 0.070 181.055 ;
+    END
+  END wd_in[45]
+  PIN wd_in[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 182.245 0.070 182.315 ;
+    END
+  END wd_in[46]
+  PIN wd_in[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 183.505 0.070 183.575 ;
+    END
+  END wd_in[47]
+  PIN addr_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 185.395 0.070 185.465 ;
+    END
+  END addr_in[0]
+  PIN addr_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 186.655 0.070 186.725 ;
+    END
+  END addr_in[1]
+  PIN addr_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 187.915 0.070 187.985 ;
+    END
+  END addr_in[2]
+  PIN addr_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 189.175 0.070 189.245 ;
+    END
+  END addr_in[3]
+  PIN addr_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 190.435 0.070 190.505 ;
+    END
+  END addr_in[4]
+  PIN addr_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 191.695 0.070 191.765 ;
+    END
+  END addr_in[5]
+  PIN addr_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 192.955 0.070 193.025 ;
+    END
+  END addr_in[6]
+  PIN addr_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 194.215 0.070 194.285 ;
+    END
+  END addr_in[7]
+  PIN we_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 196.105 0.070 196.175 ;
+    END
+  END we_in
+  PIN ce_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 197.365 0.070 197.435 ;
+    END
+  END ce_in
+  PIN clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 198.625 0.070 198.695 ;
+    END
+  END clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER metal4 ;
+      RECT 1.960 2.100 2.240 205.100 ;
+      RECT 5.320 2.100 5.600 205.100 ;
+      RECT 8.680 2.100 8.960 205.100 ;
+      RECT 12.040 2.100 12.320 205.100 ;
+      RECT 15.400 2.100 15.680 205.100 ;
+      RECT 18.760 2.100 19.040 205.100 ;
+      RECT 22.120 2.100 22.400 205.100 ;
+      RECT 25.480 2.100 25.760 205.100 ;
+      RECT 28.840 2.100 29.120 205.100 ;
+      RECT 32.200 2.100 32.480 205.100 ;
+      RECT 35.560 2.100 35.840 205.100 ;
+      RECT 38.920 2.100 39.200 205.100 ;
+      RECT 42.280 2.100 42.560 205.100 ;
+      RECT 45.640 2.100 45.920 205.100 ;
+      RECT 49.000 2.100 49.280 205.100 ;
+      RECT 52.360 2.100 52.640 205.100 ;
+      RECT 55.720 2.100 56.000 205.100 ;
+      RECT 59.080 2.100 59.360 205.100 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER metal4 ;
+      RECT 3.640 2.100 3.920 205.100 ;
+      RECT 7.000 2.100 7.280 205.100 ;
+      RECT 10.360 2.100 10.640 205.100 ;
+      RECT 13.720 2.100 14.000 205.100 ;
+      RECT 17.080 2.100 17.360 205.100 ;
+      RECT 20.440 2.100 20.720 205.100 ;
+      RECT 23.800 2.100 24.080 205.100 ;
+      RECT 27.160 2.100 27.440 205.100 ;
+      RECT 30.520 2.100 30.800 205.100 ;
+      RECT 33.880 2.100 34.160 205.100 ;
+      RECT 37.240 2.100 37.520 205.100 ;
+      RECT 40.600 2.100 40.880 205.100 ;
+      RECT 43.960 2.100 44.240 205.100 ;
+      RECT 47.320 2.100 47.600 205.100 ;
+      RECT 50.680 2.100 50.960 205.100 ;
+      RECT 54.040 2.100 54.320 205.100 ;
+      RECT 57.400 2.100 57.680 205.100 ;
+      RECT 60.760 2.100 61.040 205.100 ;
+    END
+  END VDD
+  OBS
+    LAYER metal1 ;
+    RECT 0 0 64.030 207.200 ;
+    LAYER metal2 ;
+    RECT 0 0 64.030 207.200 ;
+    LAYER metal3 ;
+    RECT 0.070 0 64.030 207.200 ;
+    RECT 0 0.000 0.070 2.065 ;
+    RECT 0 2.135 0.070 3.325 ;
+    RECT 0 3.395 0.070 4.585 ;
+    RECT 0 4.655 0.070 5.845 ;
+    RECT 0 5.915 0.070 7.105 ;
+    RECT 0 7.175 0.070 8.365 ;
+    RECT 0 8.435 0.070 9.625 ;
+    RECT 0 9.695 0.070 10.885 ;
+    RECT 0 10.955 0.070 12.145 ;
+    RECT 0 12.215 0.070 13.405 ;
+    RECT 0 13.475 0.070 14.665 ;
+    RECT 0 14.735 0.070 15.925 ;
+    RECT 0 15.995 0.070 17.185 ;
+    RECT 0 17.255 0.070 18.445 ;
+    RECT 0 18.515 0.070 19.705 ;
+    RECT 0 19.775 0.070 20.965 ;
+    RECT 0 21.035 0.070 22.225 ;
+    RECT 0 22.295 0.070 23.485 ;
+    RECT 0 23.555 0.070 24.745 ;
+    RECT 0 24.815 0.070 26.005 ;
+    RECT 0 26.075 0.070 27.265 ;
+    RECT 0 27.335 0.070 28.525 ;
+    RECT 0 28.595 0.070 29.785 ;
+    RECT 0 29.855 0.070 31.045 ;
+    RECT 0 31.115 0.070 32.305 ;
+    RECT 0 32.375 0.070 33.565 ;
+    RECT 0 33.635 0.070 34.825 ;
+    RECT 0 34.895 0.070 36.085 ;
+    RECT 0 36.155 0.070 37.345 ;
+    RECT 0 37.415 0.070 38.605 ;
+    RECT 0 38.675 0.070 39.865 ;
+    RECT 0 39.935 0.070 41.125 ;
+    RECT 0 41.195 0.070 42.385 ;
+    RECT 0 42.455 0.070 43.645 ;
+    RECT 0 43.715 0.070 44.905 ;
+    RECT 0 44.975 0.070 46.165 ;
+    RECT 0 46.235 0.070 47.425 ;
+    RECT 0 47.495 0.070 48.685 ;
+    RECT 0 48.755 0.070 49.945 ;
+    RECT 0 50.015 0.070 51.205 ;
+    RECT 0 51.275 0.070 52.465 ;
+    RECT 0 52.535 0.070 53.725 ;
+    RECT 0 53.795 0.070 54.985 ;
+    RECT 0 55.055 0.070 56.245 ;
+    RECT 0 56.315 0.070 57.505 ;
+    RECT 0 57.575 0.070 58.765 ;
+    RECT 0 58.835 0.070 60.025 ;
+    RECT 0 60.095 0.070 61.285 ;
+    RECT 0 61.355 0.070 63.175 ;
+    RECT 0 63.245 0.070 64.435 ;
+    RECT 0 64.505 0.070 65.695 ;
+    RECT 0 65.765 0.070 66.955 ;
+    RECT 0 67.025 0.070 68.215 ;
+    RECT 0 68.285 0.070 69.475 ;
+    RECT 0 69.545 0.070 70.735 ;
+    RECT 0 70.805 0.070 71.995 ;
+    RECT 0 72.065 0.070 73.255 ;
+    RECT 0 73.325 0.070 74.515 ;
+    RECT 0 74.585 0.070 75.775 ;
+    RECT 0 75.845 0.070 77.035 ;
+    RECT 0 77.105 0.070 78.295 ;
+    RECT 0 78.365 0.070 79.555 ;
+    RECT 0 79.625 0.070 80.815 ;
+    RECT 0 80.885 0.070 82.075 ;
+    RECT 0 82.145 0.070 83.335 ;
+    RECT 0 83.405 0.070 84.595 ;
+    RECT 0 84.665 0.070 85.855 ;
+    RECT 0 85.925 0.070 87.115 ;
+    RECT 0 87.185 0.070 88.375 ;
+    RECT 0 88.445 0.070 89.635 ;
+    RECT 0 89.705 0.070 90.895 ;
+    RECT 0 90.965 0.070 92.155 ;
+    RECT 0 92.225 0.070 93.415 ;
+    RECT 0 93.485 0.070 94.675 ;
+    RECT 0 94.745 0.070 95.935 ;
+    RECT 0 96.005 0.070 97.195 ;
+    RECT 0 97.265 0.070 98.455 ;
+    RECT 0 98.525 0.070 99.715 ;
+    RECT 0 99.785 0.070 100.975 ;
+    RECT 0 101.045 0.070 102.235 ;
+    RECT 0 102.305 0.070 103.495 ;
+    RECT 0 103.565 0.070 104.755 ;
+    RECT 0 104.825 0.070 106.015 ;
+    RECT 0 106.085 0.070 107.275 ;
+    RECT 0 107.345 0.070 108.535 ;
+    RECT 0 108.605 0.070 109.795 ;
+    RECT 0 109.865 0.070 111.055 ;
+    RECT 0 111.125 0.070 112.315 ;
+    RECT 0 112.385 0.070 113.575 ;
+    RECT 0 113.645 0.070 114.835 ;
+    RECT 0 114.905 0.070 116.095 ;
+    RECT 0 116.165 0.070 117.355 ;
+    RECT 0 117.425 0.070 118.615 ;
+    RECT 0 118.685 0.070 119.875 ;
+    RECT 0 119.945 0.070 121.135 ;
+    RECT 0 121.205 0.070 122.395 ;
+    RECT 0 122.465 0.070 124.285 ;
+    RECT 0 124.355 0.070 125.545 ;
+    RECT 0 125.615 0.070 126.805 ;
+    RECT 0 126.875 0.070 128.065 ;
+    RECT 0 128.135 0.070 129.325 ;
+    RECT 0 129.395 0.070 130.585 ;
+    RECT 0 130.655 0.070 131.845 ;
+    RECT 0 131.915 0.070 133.105 ;
+    RECT 0 133.175 0.070 134.365 ;
+    RECT 0 134.435 0.070 135.625 ;
+    RECT 0 135.695 0.070 136.885 ;
+    RECT 0 136.955 0.070 138.145 ;
+    RECT 0 138.215 0.070 139.405 ;
+    RECT 0 139.475 0.070 140.665 ;
+    RECT 0 140.735 0.070 141.925 ;
+    RECT 0 141.995 0.070 143.185 ;
+    RECT 0 143.255 0.070 144.445 ;
+    RECT 0 144.515 0.070 145.705 ;
+    RECT 0 145.775 0.070 146.965 ;
+    RECT 0 147.035 0.070 148.225 ;
+    RECT 0 148.295 0.070 149.485 ;
+    RECT 0 149.555 0.070 150.745 ;
+    RECT 0 150.815 0.070 152.005 ;
+    RECT 0 152.075 0.070 153.265 ;
+    RECT 0 153.335 0.070 154.525 ;
+    RECT 0 154.595 0.070 155.785 ;
+    RECT 0 155.855 0.070 157.045 ;
+    RECT 0 157.115 0.070 158.305 ;
+    RECT 0 158.375 0.070 159.565 ;
+    RECT 0 159.635 0.070 160.825 ;
+    RECT 0 160.895 0.070 162.085 ;
+    RECT 0 162.155 0.070 163.345 ;
+    RECT 0 163.415 0.070 164.605 ;
+    RECT 0 164.675 0.070 165.865 ;
+    RECT 0 165.935 0.070 167.125 ;
+    RECT 0 167.195 0.070 168.385 ;
+    RECT 0 168.455 0.070 169.645 ;
+    RECT 0 169.715 0.070 170.905 ;
+    RECT 0 170.975 0.070 172.165 ;
+    RECT 0 172.235 0.070 173.425 ;
+    RECT 0 173.495 0.070 174.685 ;
+    RECT 0 174.755 0.070 175.945 ;
+    RECT 0 176.015 0.070 177.205 ;
+    RECT 0 177.275 0.070 178.465 ;
+    RECT 0 178.535 0.070 179.725 ;
+    RECT 0 179.795 0.070 180.985 ;
+    RECT 0 181.055 0.070 182.245 ;
+    RECT 0 182.315 0.070 183.505 ;
+    RECT 0 183.575 0.070 185.395 ;
+    RECT 0 185.465 0.070 186.655 ;
+    RECT 0 186.725 0.070 187.915 ;
+    RECT 0 187.985 0.070 189.175 ;
+    RECT 0 189.245 0.070 190.435 ;
+    RECT 0 190.505 0.070 191.695 ;
+    RECT 0 191.765 0.070 192.955 ;
+    RECT 0 193.025 0.070 194.215 ;
+    RECT 0 194.285 0.070 196.105 ;
+    RECT 0 196.175 0.070 197.365 ;
+    RECT 0 197.435 0.070 198.625 ;
+    RECT 0 198.695 0.070 207.200 ;
+    LAYER metal4 ;
+    RECT 0 0 64.030 2.100 ;
+    RECT 0 205.100 64.030 207.200 ;
+    RECT 0.000 2.100 1.960 205.100 ;
+    RECT 2.240 2.100 3.640 205.100 ;
+    RECT 3.920 2.100 5.320 205.100 ;
+    RECT 5.600 2.100 7.000 205.100 ;
+    RECT 7.280 2.100 8.680 205.100 ;
+    RECT 8.960 2.100 10.360 205.100 ;
+    RECT 10.640 2.100 12.040 205.100 ;
+    RECT 12.320 2.100 13.720 205.100 ;
+    RECT 14.000 2.100 15.400 205.100 ;
+    RECT 15.680 2.100 17.080 205.100 ;
+    RECT 17.360 2.100 18.760 205.100 ;
+    RECT 19.040 2.100 20.440 205.100 ;
+    RECT 20.720 2.100 22.120 205.100 ;
+    RECT 22.400 2.100 23.800 205.100 ;
+    RECT 24.080 2.100 25.480 205.100 ;
+    RECT 25.760 2.100 27.160 205.100 ;
+    RECT 27.440 2.100 28.840 205.100 ;
+    RECT 29.120 2.100 30.520 205.100 ;
+    RECT 30.800 2.100 32.200 205.100 ;
+    RECT 32.480 2.100 33.880 205.100 ;
+    RECT 34.160 2.100 35.560 205.100 ;
+    RECT 35.840 2.100 37.240 205.100 ;
+    RECT 37.520 2.100 38.920 205.100 ;
+    RECT 39.200 2.100 40.600 205.100 ;
+    RECT 40.880 2.100 42.280 205.100 ;
+    RECT 42.560 2.100 43.960 205.100 ;
+    RECT 44.240 2.100 45.640 205.100 ;
+    RECT 45.920 2.100 47.320 205.100 ;
+    RECT 47.600 2.100 49.000 205.100 ;
+    RECT 49.280 2.100 50.680 205.100 ;
+    RECT 50.960 2.100 52.360 205.100 ;
+    RECT 52.640 2.100 54.040 205.100 ;
+    RECT 54.320 2.100 55.720 205.100 ;
+    RECT 56.000 2.100 57.400 205.100 ;
+    RECT 57.680 2.100 59.080 205.100 ;
+    RECT 59.360 2.100 60.760 205.100 ;
+    RECT 61.040 2.100 64.030 205.100 ;
+    LAYER OVERLAP ;
+    RECT 0 0 64.030 207.200 ;
+  END
+END fakeram45_256x48
+
+END LIBRARY

Enablements/NanGate45/lef/fakeram45_32x32.lef

+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+MACRO fakeram45_32x32
+  FOREIGN fakeram45_32x32 0 0 ;
+  SYMMETRY X Y R90 ;
+  SIZE 55.100 BY 33.600 ;
+  CLASS BLOCK ;
+  PIN w_mask_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.065 0.070 2.135 ;
+    END
+  END w_mask_in[0]
+  PIN w_mask_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.275 0.070 2.345 ;
+    END
+  END w_mask_in[1]
+  PIN w_mask_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.485 0.070 2.555 ;
+    END
+  END w_mask_in[2]
+  PIN w_mask_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.695 0.070 2.765 ;
+    END
+  END w_mask_in[3]
+  PIN w_mask_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.905 0.070 2.975 ;
+    END
+  END w_mask_in[4]
+  PIN w_mask_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.115 0.070 3.185 ;
+    END
+  END w_mask_in[5]
+  PIN w_mask_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.325 0.070 3.395 ;
+    END
+  END w_mask_in[6]
+  PIN w_mask_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.535 0.070 3.605 ;
+    END
+  END w_mask_in[7]
+  PIN w_mask_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.745 0.070 3.815 ;
+    END
+  END w_mask_in[8]
+  PIN w_mask_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.955 0.070 4.025 ;
+    END
+  END w_mask_in[9]
+  PIN w_mask_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 4.165 0.070 4.235 ;
+    END
+  END w_mask_in[10]
+  PIN w_mask_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 4.375 0.070 4.445 ;
+    END
+  END w_mask_in[11]
+  PIN w_mask_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 4.585 0.070 4.655 ;
+    END
+  END w_mask_in[12]
+  PIN w_mask_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 4.795 0.070 4.865 ;
+    END
+  END w_mask_in[13]
+  PIN w_mask_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.005 0.070 5.075 ;
+    END
+  END w_mask_in[14]
+  PIN w_mask_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.215 0.070 5.285 ;
+    END
+  END w_mask_in[15]
+  PIN w_mask_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.425 0.070 5.495 ;
+    END
+  END w_mask_in[16]
+  PIN w_mask_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.635 0.070 5.705 ;
+    END
+  END w_mask_in[17]
+  PIN w_mask_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.845 0.070 5.915 ;
+    END
+  END w_mask_in[18]
+  PIN w_mask_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.055 0.070 6.125 ;
+    END
+  END w_mask_in[19]
+  PIN w_mask_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.265 0.070 6.335 ;
+    END
+  END w_mask_in[20]
+  PIN w_mask_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.475 0.070 6.545 ;
+    END
+  END w_mask_in[21]
+  PIN w_mask_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.685 0.070 6.755 ;
+    END
+  END w_mask_in[22]
+  PIN w_mask_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.895 0.070 6.965 ;
+    END
+  END w_mask_in[23]
+  PIN w_mask_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.105 0.070 7.175 ;
+    END
+  END w_mask_in[24]
+  PIN w_mask_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.315 0.070 7.385 ;
+    END
+  END w_mask_in[25]
+  PIN w_mask_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.525 0.070 7.595 ;
+    END
+  END w_mask_in[26]
+  PIN w_mask_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.735 0.070 7.805 ;
+    END
+  END w_mask_in[27]
+  PIN w_mask_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.945 0.070 8.015 ;
+    END
+  END w_mask_in[28]
+  PIN w_mask_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.155 0.070 8.225 ;
+    END
+  END w_mask_in[29]
+  PIN w_mask_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.365 0.070 8.435 ;
+    END
+  END w_mask_in[30]
+  PIN w_mask_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.575 0.070 8.645 ;
+    END
+  END w_mask_in[31]
+  PIN rd_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.465 0.070 10.535 ;
+    END
+  END rd_out[0]
+  PIN rd_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.675 0.070 10.745 ;
+    END
+  END rd_out[1]
+  PIN rd_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.885 0.070 10.955 ;
+    END
+  END rd_out[2]
+  PIN rd_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.095 0.070 11.165 ;
+    END
+  END rd_out[3]
+  PIN rd_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.305 0.070 11.375 ;
+    END
+  END rd_out[4]
+  PIN rd_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.515 0.070 11.585 ;
+    END
+  END rd_out[5]
+  PIN rd_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.725 0.070 11.795 ;
+    END
+  END rd_out[6]
+  PIN rd_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.935 0.070 12.005 ;
+    END
+  END rd_out[7]
+  PIN rd_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.145 0.070 12.215 ;
+    END
+  END rd_out[8]
+  PIN rd_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.355 0.070 12.425 ;
+    END
+  END rd_out[9]
+  PIN rd_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.565 0.070 12.635 ;
+    END
+  END rd_out[10]
+  PIN rd_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.775 0.070 12.845 ;
+    END
+  END rd_out[11]
+  PIN rd_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.985 0.070 13.055 ;
+    END
+  END rd_out[12]
+  PIN rd_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 13.195 0.070 13.265 ;
+    END
+  END rd_out[13]
+  PIN rd_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 13.405 0.070 13.475 ;
+    END
+  END rd_out[14]
+  PIN rd_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 13.615 0.070 13.685 ;
+    END
+  END rd_out[15]
+  PIN rd_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 13.825 0.070 13.895 ;
+    END
+  END rd_out[16]
+  PIN rd_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.035 0.070 14.105 ;
+    END
+  END rd_out[17]
+  PIN rd_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.245 0.070 14.315 ;
+    END
+  END rd_out[18]
+  PIN rd_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.455 0.070 14.525 ;
+    END
+  END rd_out[19]
+  PIN rd_out[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.665 0.070 14.735 ;
+    END
+  END rd_out[20]
+  PIN rd_out[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.875 0.070 14.945 ;
+    END
+  END rd_out[21]
+  PIN rd_out[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.085 0.070 15.155 ;
+    END
+  END rd_out[22]
+  PIN rd_out[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.295 0.070 15.365 ;
+    END
+  END rd_out[23]
+  PIN rd_out[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.505 0.070 15.575 ;
+    END
+  END rd_out[24]
+  PIN rd_out[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.715 0.070 15.785 ;
+    END
+  END rd_out[25]
+  PIN rd_out[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.925 0.070 15.995 ;
+    END
+  END rd_out[26]
+  PIN rd_out[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.135 0.070 16.205 ;
+    END
+  END rd_out[27]
+  PIN rd_out[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.345 0.070 16.415 ;
+    END
+  END rd_out[28]
+  PIN rd_out[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.555 0.070 16.625 ;
+    END
+  END rd_out[29]
+  PIN rd_out[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.765 0.070 16.835 ;
+    END
+  END rd_out[30]
+  PIN rd_out[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.975 0.070 17.045 ;
+    END
+  END rd_out[31]
+  PIN wd_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 18.865 0.070 18.935 ;
+    END
+  END wd_in[0]
+  PIN wd_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.075 0.070 19.145 ;
+    END
+  END wd_in[1]
+  PIN wd_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.285 0.070 19.355 ;
+    END
+  END wd_in[2]
+  PIN wd_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.495 0.070 19.565 ;
+    END
+  END wd_in[3]
+  PIN wd_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.705 0.070 19.775 ;
+    END
+  END wd_in[4]
+  PIN wd_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.915 0.070 19.985 ;
+    END
+  END wd_in[5]
+  PIN wd_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.125 0.070 20.195 ;
+    END
+  END wd_in[6]
+  PIN wd_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.335 0.070 20.405 ;
+    END
+  END wd_in[7]
+  PIN wd_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.545 0.070 20.615 ;
+    END
+  END wd_in[8]
+  PIN wd_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.755 0.070 20.825 ;
+    END
+  END wd_in[9]
+  PIN wd_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.965 0.070 21.035 ;
+    END
+  END wd_in[10]
+  PIN wd_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 21.175 0.070 21.245 ;
+    END
+  END wd_in[11]
+  PIN wd_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 21.385 0.070 21.455 ;
+    END
+  END wd_in[12]
+  PIN wd_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 21.595 0.070 21.665 ;
+    END
+  END wd_in[13]
+  PIN wd_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 21.805 0.070 21.875 ;
+    END
+  END wd_in[14]
+  PIN wd_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.015 0.070 22.085 ;
+    END
+  END wd_in[15]
+  PIN wd_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.225 0.070 22.295 ;
+    END
+  END wd_in[16]
+  PIN wd_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.435 0.070 22.505 ;
+    END
+  END wd_in[17]
+  PIN wd_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.645 0.070 22.715 ;
+    END
+  END wd_in[18]
+  PIN wd_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.855 0.070 22.925 ;
+    END
+  END wd_in[19]
+  PIN wd_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.065 0.070 23.135 ;
+    END
+  END wd_in[20]
+  PIN wd_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.275 0.070 23.345 ;
+    END
+  END wd_in[21]
+  PIN wd_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.485 0.070 23.555 ;
+    END
+  END wd_in[22]
+  PIN wd_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.695 0.070 23.765 ;
+    END
+  END wd_in[23]
+  PIN wd_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.905 0.070 23.975 ;
+    END
+  END wd_in[24]
+  PIN wd_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.115 0.070 24.185 ;
+    END
+  END wd_in[25]
+  PIN wd_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.325 0.070 24.395 ;
+    END
+  END wd_in[26]
+  PIN wd_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.535 0.070 24.605 ;
+    END
+  END wd_in[27]
+  PIN wd_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.745 0.070 24.815 ;
+    END
+  END wd_in[28]
+  PIN wd_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.955 0.070 25.025 ;
+    END
+  END wd_in[29]
+  PIN wd_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 25.165 0.070 25.235 ;
+    END
+  END wd_in[30]
+  PIN wd_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 25.375 0.070 25.445 ;
+    END
+  END wd_in[31]
+  PIN addr_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 27.265 0.070 27.335 ;
+    END
+  END addr_in[0]
+  PIN addr_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 27.475 0.070 27.545 ;
+    END
+  END addr_in[1]
+  PIN addr_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 27.685 0.070 27.755 ;
+    END
+  END addr_in[2]
+  PIN addr_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 27.895 0.070 27.965 ;
+    END
+  END addr_in[3]
+  PIN addr_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 28.105 0.070 28.175 ;
+    END
+  END addr_in[4]
+  PIN we_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 29.995 0.070 30.065 ;
+    END
+  END we_in
+  PIN ce_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 30.205 0.070 30.275 ;
+    END
+  END ce_in
+  PIN clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 30.415 0.070 30.485 ;
+    END
+  END clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER metal4 ;
+      RECT 1.960 2.100 2.240 31.500 ;
+      RECT 5.320 2.100 5.600 31.500 ;
+      RECT 8.680 2.100 8.960 31.500 ;
+      RECT 12.040 2.100 12.320 31.500 ;
+      RECT 15.400 2.100 15.680 31.500 ;
+      RECT 18.760 2.100 19.040 31.500 ;
+      RECT 22.120 2.100 22.400 31.500 ;
+      RECT 25.480 2.100 25.760 31.500 ;
+      RECT 28.840 2.100 29.120 31.500 ;
+      RECT 32.200 2.100 32.480 31.500 ;
+      RECT 35.560 2.100 35.840 31.500 ;
+      RECT 38.920 2.100 39.200 31.500 ;
+      RECT 42.280 2.100 42.560 31.500 ;
+      RECT 45.640 2.100 45.920 31.500 ;
+      RECT 49.000 2.100 49.280 31.500 ;
+      RECT 52.360 2.100 52.640 31.500 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER metal4 ;
+      RECT 3.640 2.100 3.920 31.500 ;
+      RECT 7.000 2.100 7.280 31.500 ;
+      RECT 10.360 2.100 10.640 31.500 ;
+      RECT 13.720 2.100 14.000 31.500 ;
+      RECT 17.080 2.100 17.360 31.500 ;
+      RECT 20.440 2.100 20.720 31.500 ;
+      RECT 23.800 2.100 24.080 31.500 ;
+      RECT 27.160 2.100 27.440 31.500 ;
+      RECT 30.520 2.100 30.800 31.500 ;
+      RECT 33.880 2.100 34.160 31.500 ;
+      RECT 37.240 2.100 37.520 31.500 ;
+      RECT 40.600 2.100 40.880 31.500 ;
+      RECT 43.960 2.100 44.240 31.500 ;
+      RECT 47.320 2.100 47.600 31.500 ;
+      RECT 50.680 2.100 50.960 31.500 ;
+    END
+  END VDD
+  OBS
+    LAYER metal1 ;
+    RECT 0 0 55.100 33.600 ;
+    LAYER metal2 ;
+    RECT 0 0 55.100 33.600 ;
+    LAYER metal3 ;
+    RECT 0.070 0 55.100 33.600 ;
+    RECT 0 0.000 0.070 2.065 ;
+    RECT 0 2.135 0.070 2.275 ;
+    RECT 0 2.345 0.070 2.485 ;
+    RECT 0 2.555 0.070 2.695 ;
+    RECT 0 2.765 0.070 2.905 ;
+    RECT 0 2.975 0.070 3.115 ;
+    RECT 0 3.185 0.070 3.325 ;
+    RECT 0 3.395 0.070 3.535 ;
+    RECT 0 3.605 0.070 3.745 ;
+    RECT 0 3.815 0.070 3.955 ;
+    RECT 0 4.025 0.070 4.165 ;
+    RECT 0 4.235 0.070 4.375 ;
+    RECT 0 4.445 0.070 4.585 ;
+    RECT 0 4.655 0.070 4.795 ;
+    RECT 0 4.865 0.070 5.005 ;
+    RECT 0 5.075 0.070 5.215 ;
+    RECT 0 5.285 0.070 5.425 ;
+    RECT 0 5.495 0.070 5.635 ;
+    RECT 0 5.705 0.070 5.845 ;
+    RECT 0 5.915 0.070 6.055 ;
+    RECT 0 6.125 0.070 6.265 ;
+    RECT 0 6.335 0.070 6.475 ;
+    RECT 0 6.545 0.070 6.685 ;
+    RECT 0 6.755 0.070 6.895 ;
+    RECT 0 6.965 0.070 7.105 ;
+    RECT 0 7.175 0.070 7.315 ;
+    RECT 0 7.385 0.070 7.525 ;
+    RECT 0 7.595 0.070 7.735 ;
+    RECT 0 7.805 0.070 7.945 ;
+    RECT 0 8.015 0.070 8.155 ;
+    RECT 0 8.225 0.070 8.365 ;
+    RECT 0 8.435 0.070 8.575 ;
+    RECT 0 8.645 0.070 10.465 ;
+    RECT 0 10.535 0.070 10.675 ;
+    RECT 0 10.745 0.070 10.885 ;
+    RECT 0 10.955 0.070 11.095 ;
+    RECT 0 11.165 0.070 11.305 ;
+    RECT 0 11.375 0.070 11.515 ;
+    RECT 0 11.585 0.070 11.725 ;
+    RECT 0 11.795 0.070 11.935 ;
+    RECT 0 12.005 0.070 12.145 ;
+    RECT 0 12.215 0.070 12.355 ;
+    RECT 0 12.425 0.070 12.565 ;
+    RECT 0 12.635 0.070 12.775 ;
+    RECT 0 12.845 0.070 12.985 ;
+    RECT 0 13.055 0.070 13.195 ;
+    RECT 0 13.265 0.070 13.405 ;
+    RECT 0 13.475 0.070 13.615 ;
+    RECT 0 13.685 0.070 13.825 ;
+    RECT 0 13.895 0.070 14.035 ;
+    RECT 0 14.105 0.070 14.245 ;
+    RECT 0 14.315 0.070 14.455 ;
+    RECT 0 14.525 0.070 14.665 ;
+    RECT 0 14.735 0.070 14.875 ;
+    RECT 0 14.945 0.070 15.085 ;
+    RECT 0 15.155 0.070 15.295 ;
+    RECT 0 15.365 0.070 15.505 ;
+    RECT 0 15.575 0.070 15.715 ;
+    RECT 0 15.785 0.070 15.925 ;
+    RECT 0 15.995 0.070 16.135 ;
+    RECT 0 16.205 0.070 16.345 ;
+    RECT 0 16.415 0.070 16.555 ;
+    RECT 0 16.625 0.070 16.765 ;
+    RECT 0 16.835 0.070 16.975 ;
+    RECT 0 17.045 0.070 18.865 ;
+    RECT 0 18.935 0.070 19.075 ;
+    RECT 0 19.145 0.070 19.285 ;
+    RECT 0 19.355 0.070 19.495 ;
+    RECT 0 19.565 0.070 19.705 ;
+    RECT 0 19.775 0.070 19.915 ;
+    RECT 0 19.985 0.070 20.125 ;
+    RECT 0 20.195 0.070 20.335 ;
+    RECT 0 20.405 0.070 20.545 ;
+    RECT 0 20.615 0.070 20.755 ;
+    RECT 0 20.825 0.070 20.965 ;
+    RECT 0 21.035 0.070 21.175 ;
+    RECT 0 21.245 0.070 21.385 ;
+    RECT 0 21.455 0.070 21.595 ;
+    RECT 0 21.665 0.070 21.805 ;
+    RECT 0 21.875 0.070 22.015 ;
+    RECT 0 22.085 0.070 22.225 ;
+    RECT 0 22.295 0.070 22.435 ;
+    RECT 0 22.505 0.070 22.645 ;
+    RECT 0 22.715 0.070 22.855 ;
+    RECT 0 22.925 0.070 23.065 ;
+    RECT 0 23.135 0.070 23.275 ;
+    RECT 0 23.345 0.070 23.485 ;
+    RECT 0 23.555 0.070 23.695 ;
+    RECT 0 23.765 0.070 23.905 ;
+    RECT 0 23.975 0.070 24.115 ;
+    RECT 0 24.185 0.070 24.325 ;
+    RECT 0 24.395 0.070 24.535 ;
+    RECT 0 24.605 0.070 24.745 ;
+    RECT 0 24.815 0.070 24.955 ;
+    RECT 0 25.025 0.070 25.165 ;
+    RECT 0 25.235 0.070 25.375 ;
+    RECT 0 25.445 0.070 27.265 ;
+    RECT 0 27.335 0.070 27.475 ;
+    RECT 0 27.545 0.070 27.685 ;
+    RECT 0 27.755 0.070 27.895 ;
+    RECT 0 27.965 0.070 28.105 ;
+    RECT 0 28.175 0.070 29.995 ;
+    RECT 0 30.065 0.070 30.205 ;
+    RECT 0 30.275 0.070 30.415 ;
+    RECT 0 30.485 0.070 33.600 ;
+    LAYER metal4 ;
+    RECT 0 0 55.100 2.100 ;
+    RECT 0 31.500 55.100 33.600 ;
+    RECT 0.000 2.100 1.960 31.500 ;
+    RECT 2.240 2.100 3.640 31.500 ;
+    RECT 3.920 2.100 5.320 31.500 ;
+    RECT 5.600 2.100 7.000 31.500 ;
+    RECT 7.280 2.100 8.680 31.500 ;
+    RECT 8.960 2.100 10.360 31.500 ;
+    RECT 10.640 2.100 12.040 31.500 ;
+    RECT 12.320 2.100 13.720 31.500 ;
+    RECT 14.000 2.100 15.400 31.500 ;
+    RECT 15.680 2.100 17.080 31.500 ;
+    RECT 17.360 2.100 18.760 31.500 ;
+    RECT 19.040 2.100 20.440 31.500 ;
+    RECT 20.720 2.100 22.120 31.500 ;
+    RECT 22.400 2.100 23.800 31.500 ;
+    RECT 24.080 2.100 25.480 31.500 ;
+    RECT 25.760 2.100 27.160 31.500 ;
+    RECT 27.440 2.100 28.840 31.500 ;
+    RECT 29.120 2.100 30.520 31.500 ;
+    RECT 30.800 2.100 32.200 31.500 ;
+    RECT 32.480 2.100 33.880 31.500 ;
+    RECT 34.160 2.100 35.560 31.500 ;
+    RECT 35.840 2.100 37.240 31.500 ;
+    RECT 37.520 2.100 38.920 31.500 ;
+    RECT 39.200 2.100 40.600 31.500 ;
+    RECT 40.880 2.100 42.280 31.500 ;
+    RECT 42.560 2.100 43.960 31.500 ;
+    RECT 44.240 2.100 45.640 31.500 ;
+    RECT 45.920 2.100 47.320 31.500 ;
+    RECT 47.600 2.100 49.000 31.500 ;
+    RECT 49.280 2.100 50.680 31.500 ;
+    RECT 50.960 2.100 52.360 31.500 ;
+    RECT 52.640 2.100 55.100 31.500 ;
+    LAYER OVERLAP ;
+    RECT 0 0 55.100 33.600 ;
+  END
+END fakeram45_32x32
+
+END LIBRARY

Enablements/NanGate45/lef/fakeram45_512x64.lef

+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+MACRO fakeram45_512x64
+  FOREIGN fakeram45_512x64 0 0 ;
+  SYMMETRY X Y R90 ;
+  SIZE 110.010 BY 238.000 ;
+  CLASS BLOCK ;
+  PIN w_mask_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.065 0.070 2.135 ;
+    END
+  END w_mask_in[0]
+  PIN w_mask_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.115 0.070 3.185 ;
+    END
+  END w_mask_in[1]
+  PIN w_mask_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 4.165 0.070 4.235 ;
+    END
+  END w_mask_in[2]
+  PIN w_mask_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.215 0.070 5.285 ;
+    END
+  END w_mask_in[3]
+  PIN w_mask_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.265 0.070 6.335 ;
+    END
+  END w_mask_in[4]
+  PIN w_mask_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.315 0.070 7.385 ;
+    END
+  END w_mask_in[5]
+  PIN w_mask_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.365 0.070 8.435 ;
+    END
+  END w_mask_in[6]
+  PIN w_mask_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 9.415 0.070 9.485 ;
+    END
+  END w_mask_in[7]
+  PIN w_mask_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.465 0.070 10.535 ;
+    END
+  END w_mask_in[8]
+  PIN w_mask_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.515 0.070 11.585 ;
+    END
+  END w_mask_in[9]
+  PIN w_mask_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.565 0.070 12.635 ;
+    END
+  END w_mask_in[10]
+  PIN w_mask_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 13.615 0.070 13.685 ;
+    END
+  END w_mask_in[11]
+  PIN w_mask_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.665 0.070 14.735 ;
+    END
+  END w_mask_in[12]
+  PIN w_mask_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.715 0.070 15.785 ;
+    END
+  END w_mask_in[13]
+  PIN w_mask_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.765 0.070 16.835 ;
+    END
+  END w_mask_in[14]
+  PIN w_mask_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 17.815 0.070 17.885 ;
+    END
+  END w_mask_in[15]
+  PIN w_mask_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 18.865 0.070 18.935 ;
+    END
+  END w_mask_in[16]
+  PIN w_mask_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.915 0.070 19.985 ;
+    END
+  END w_mask_in[17]
+  PIN w_mask_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.965 0.070 21.035 ;
+    END
+  END w_mask_in[18]
+  PIN w_mask_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.015 0.070 22.085 ;
+    END
+  END w_mask_in[19]
+  PIN w_mask_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.065 0.070 23.135 ;
+    END
+  END w_mask_in[20]
+  PIN w_mask_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.115 0.070 24.185 ;
+    END
+  END w_mask_in[21]
+  PIN w_mask_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 25.165 0.070 25.235 ;
+    END
+  END w_mask_in[22]
+  PIN w_mask_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 26.215 0.070 26.285 ;
+    END
+  END w_mask_in[23]
+  PIN w_mask_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 27.265 0.070 27.335 ;
+    END
+  END w_mask_in[24]
+  PIN w_mask_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 28.315 0.070 28.385 ;
+    END
+  END w_mask_in[25]
+  PIN w_mask_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 29.365 0.070 29.435 ;
+    END
+  END w_mask_in[26]
+  PIN w_mask_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 30.415 0.070 30.485 ;
+    END
+  END w_mask_in[27]
+  PIN w_mask_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 31.465 0.070 31.535 ;
+    END
+  END w_mask_in[28]
+  PIN w_mask_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 32.515 0.070 32.585 ;
+    END
+  END w_mask_in[29]
+  PIN w_mask_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 33.565 0.070 33.635 ;
+    END
+  END w_mask_in[30]
+  PIN w_mask_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 34.615 0.070 34.685 ;
+    END
+  END w_mask_in[31]
+  PIN w_mask_in[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 35.665 0.070 35.735 ;
+    END
+  END w_mask_in[32]
+  PIN w_mask_in[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 36.715 0.070 36.785 ;
+    END
+  END w_mask_in[33]
+  PIN w_mask_in[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 37.765 0.070 37.835 ;
+    END
+  END w_mask_in[34]
+  PIN w_mask_in[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 38.815 0.070 38.885 ;
+    END
+  END w_mask_in[35]
+  PIN w_mask_in[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 39.865 0.070 39.935 ;
+    END
+  END w_mask_in[36]
+  PIN w_mask_in[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 40.915 0.070 40.985 ;
+    END
+  END w_mask_in[37]
+  PIN w_mask_in[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 41.965 0.070 42.035 ;
+    END
+  END w_mask_in[38]
+  PIN w_mask_in[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 43.015 0.070 43.085 ;
+    END
+  END w_mask_in[39]
+  PIN w_mask_in[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 44.065 0.070 44.135 ;
+    END
+  END w_mask_in[40]
+  PIN w_mask_in[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 45.115 0.070 45.185 ;
+    END
+  END w_mask_in[41]
+  PIN w_mask_in[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 46.165 0.070 46.235 ;
+    END
+  END w_mask_in[42]
+  PIN w_mask_in[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 47.215 0.070 47.285 ;
+    END
+  END w_mask_in[43]
+  PIN w_mask_in[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 48.265 0.070 48.335 ;
+    END
+  END w_mask_in[44]
+  PIN w_mask_in[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 49.315 0.070 49.385 ;
+    END
+  END w_mask_in[45]
+  PIN w_mask_in[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 50.365 0.070 50.435 ;
+    END
+  END w_mask_in[46]
+  PIN w_mask_in[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 51.415 0.070 51.485 ;
+    END
+  END w_mask_in[47]
+  PIN w_mask_in[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 52.465 0.070 52.535 ;
+    END
+  END w_mask_in[48]
+  PIN w_mask_in[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 53.515 0.070 53.585 ;
+    END
+  END w_mask_in[49]
+  PIN w_mask_in[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 54.565 0.070 54.635 ;
+    END
+  END w_mask_in[50]
+  PIN w_mask_in[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 55.615 0.070 55.685 ;
+    END
+  END w_mask_in[51]
+  PIN w_mask_in[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 56.665 0.070 56.735 ;
+    END
+  END w_mask_in[52]
+  PIN w_mask_in[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 57.715 0.070 57.785 ;
+    END
+  END w_mask_in[53]
+  PIN w_mask_in[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 58.765 0.070 58.835 ;
+    END
+  END w_mask_in[54]
+  PIN w_mask_in[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 59.815 0.070 59.885 ;
+    END
+  END w_mask_in[55]
+  PIN w_mask_in[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 60.865 0.070 60.935 ;
+    END
+  END w_mask_in[56]
+  PIN w_mask_in[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 61.915 0.070 61.985 ;
+    END
+  END w_mask_in[57]
+  PIN w_mask_in[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 62.965 0.070 63.035 ;
+    END
+  END w_mask_in[58]
+  PIN w_mask_in[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 64.015 0.070 64.085 ;
+    END
+  END w_mask_in[59]
+  PIN w_mask_in[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 65.065 0.070 65.135 ;
+    END
+  END w_mask_in[60]
+  PIN w_mask_in[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 66.115 0.070 66.185 ;
+    END
+  END w_mask_in[61]
+  PIN w_mask_in[62]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 67.165 0.070 67.235 ;
+    END
+  END w_mask_in[62]
+  PIN w_mask_in[63]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 68.215 0.070 68.285 ;
+    END
+  END w_mask_in[63]
+  PIN rd_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 73.045 0.070 73.115 ;
+    END
+  END rd_out[0]
+  PIN rd_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 74.095 0.070 74.165 ;
+    END
+  END rd_out[1]
+  PIN rd_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 75.145 0.070 75.215 ;
+    END
+  END rd_out[2]
+  PIN rd_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 76.195 0.070 76.265 ;
+    END
+  END rd_out[3]
+  PIN rd_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 77.245 0.070 77.315 ;
+    END
+  END rd_out[4]
+  PIN rd_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 78.295 0.070 78.365 ;
+    END
+  END rd_out[5]
+  PIN rd_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 79.345 0.070 79.415 ;
+    END
+  END rd_out[6]
+  PIN rd_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 80.395 0.070 80.465 ;
+    END
+  END rd_out[7]
+  PIN rd_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 81.445 0.070 81.515 ;
+    END
+  END rd_out[8]
+  PIN rd_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 82.495 0.070 82.565 ;
+    END
+  END rd_out[9]
+  PIN rd_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 83.545 0.070 83.615 ;
+    END
+  END rd_out[10]
+  PIN rd_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 84.595 0.070 84.665 ;
+    END
+  END rd_out[11]
+  PIN rd_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 85.645 0.070 85.715 ;
+    END
+  END rd_out[12]
+  PIN rd_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 86.695 0.070 86.765 ;
+    END
+  END rd_out[13]
+  PIN rd_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 87.745 0.070 87.815 ;
+    END
+  END rd_out[14]
+  PIN rd_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 88.795 0.070 88.865 ;
+    END
+  END rd_out[15]
+  PIN rd_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 89.845 0.070 89.915 ;
+    END
+  END rd_out[16]
+  PIN rd_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 90.895 0.070 90.965 ;
+    END
+  END rd_out[17]
+  PIN rd_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 91.945 0.070 92.015 ;
+    END
+  END rd_out[18]
+  PIN rd_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 92.995 0.070 93.065 ;
+    END
+  END rd_out[19]
+  PIN rd_out[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 94.045 0.070 94.115 ;
+    END
+  END rd_out[20]
+  PIN rd_out[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 95.095 0.070 95.165 ;
+    END
+  END rd_out[21]
+  PIN rd_out[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 96.145 0.070 96.215 ;
+    END
+  END rd_out[22]
+  PIN rd_out[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 97.195 0.070 97.265 ;
+    END
+  END rd_out[23]
+  PIN rd_out[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 98.245 0.070 98.315 ;
+    END
+  END rd_out[24]
+  PIN rd_out[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 99.295 0.070 99.365 ;
+    END
+  END rd_out[25]
+  PIN rd_out[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 100.345 0.070 100.415 ;
+    END
+  END rd_out[26]
+  PIN rd_out[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 101.395 0.070 101.465 ;
+    END
+  END rd_out[27]
+  PIN rd_out[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 102.445 0.070 102.515 ;
+    END
+  END rd_out[28]
+  PIN rd_out[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 103.495 0.070 103.565 ;
+    END
+  END rd_out[29]
+  PIN rd_out[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 104.545 0.070 104.615 ;
+    END
+  END rd_out[30]
+  PIN rd_out[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 105.595 0.070 105.665 ;
+    END
+  END rd_out[31]
+  PIN rd_out[32]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 106.645 0.070 106.715 ;
+    END
+  END rd_out[32]
+  PIN rd_out[33]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 107.695 0.070 107.765 ;
+    END
+  END rd_out[33]
+  PIN rd_out[34]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 108.745 0.070 108.815 ;
+    END
+  END rd_out[34]
+  PIN rd_out[35]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 109.795 0.070 109.865 ;
+    END
+  END rd_out[35]
+  PIN rd_out[36]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 110.845 0.070 110.915 ;
+    END
+  END rd_out[36]
+  PIN rd_out[37]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 111.895 0.070 111.965 ;
+    END
+  END rd_out[37]
+  PIN rd_out[38]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 112.945 0.070 113.015 ;
+    END
+  END rd_out[38]
+  PIN rd_out[39]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 113.995 0.070 114.065 ;
+    END
+  END rd_out[39]
+  PIN rd_out[40]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 115.045 0.070 115.115 ;
+    END
+  END rd_out[40]
+  PIN rd_out[41]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 116.095 0.070 116.165 ;
+    END
+  END rd_out[41]
+  PIN rd_out[42]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 117.145 0.070 117.215 ;
+    END
+  END rd_out[42]
+  PIN rd_out[43]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 118.195 0.070 118.265 ;
+    END
+  END rd_out[43]
+  PIN rd_out[44]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 119.245 0.070 119.315 ;
+    END
+  END rd_out[44]
+  PIN rd_out[45]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 120.295 0.070 120.365 ;
+    END
+  END rd_out[45]
+  PIN rd_out[46]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 121.345 0.070 121.415 ;
+    END
+  END rd_out[46]
+  PIN rd_out[47]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 122.395 0.070 122.465 ;
+    END
+  END rd_out[47]
+  PIN rd_out[48]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 123.445 0.070 123.515 ;
+    END
+  END rd_out[48]
+  PIN rd_out[49]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 124.495 0.070 124.565 ;
+    END
+  END rd_out[49]
+  PIN rd_out[50]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 125.545 0.070 125.615 ;
+    END
+  END rd_out[50]
+  PIN rd_out[51]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 126.595 0.070 126.665 ;
+    END
+  END rd_out[51]
+  PIN rd_out[52]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 127.645 0.070 127.715 ;
+    END
+  END rd_out[52]
+  PIN rd_out[53]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 128.695 0.070 128.765 ;
+    END
+  END rd_out[53]
+  PIN rd_out[54]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 129.745 0.070 129.815 ;
+    END
+  END rd_out[54]
+  PIN rd_out[55]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 130.795 0.070 130.865 ;
+    END
+  END rd_out[55]
+  PIN rd_out[56]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 131.845 0.070 131.915 ;
+    END
+  END rd_out[56]
+  PIN rd_out[57]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 132.895 0.070 132.965 ;
+    END
+  END rd_out[57]
+  PIN rd_out[58]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 133.945 0.070 134.015 ;
+    END
+  END rd_out[58]
+  PIN rd_out[59]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 134.995 0.070 135.065 ;
+    END
+  END rd_out[59]
+  PIN rd_out[60]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 136.045 0.070 136.115 ;
+    END
+  END rd_out[60]
+  PIN rd_out[61]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 137.095 0.070 137.165 ;
+    END
+  END rd_out[61]
+  PIN rd_out[62]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 138.145 0.070 138.215 ;
+    END
+  END rd_out[62]
+  PIN rd_out[63]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 139.195 0.070 139.265 ;
+    END
+  END rd_out[63]
+  PIN wd_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 144.025 0.070 144.095 ;
+    END
+  END wd_in[0]
+  PIN wd_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 145.075 0.070 145.145 ;
+    END
+  END wd_in[1]
+  PIN wd_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 146.125 0.070 146.195 ;
+    END
+  END wd_in[2]
+  PIN wd_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 147.175 0.070 147.245 ;
+    END
+  END wd_in[3]
+  PIN wd_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 148.225 0.070 148.295 ;
+    END
+  END wd_in[4]
+  PIN wd_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 149.275 0.070 149.345 ;
+    END
+  END wd_in[5]
+  PIN wd_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 150.325 0.070 150.395 ;
+    END
+  END wd_in[6]
+  PIN wd_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 151.375 0.070 151.445 ;
+    END
+  END wd_in[7]
+  PIN wd_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 152.425 0.070 152.495 ;
+    END
+  END wd_in[8]
+  PIN wd_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 153.475 0.070 153.545 ;
+    END
+  END wd_in[9]
+  PIN wd_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 154.525 0.070 154.595 ;
+    END
+  END wd_in[10]
+  PIN wd_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 155.575 0.070 155.645 ;
+    END
+  END wd_in[11]
+  PIN wd_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 156.625 0.070 156.695 ;
+    END
+  END wd_in[12]
+  PIN wd_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 157.675 0.070 157.745 ;
+    END
+  END wd_in[13]
+  PIN wd_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 158.725 0.070 158.795 ;
+    END
+  END wd_in[14]
+  PIN wd_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 159.775 0.070 159.845 ;
+    END
+  END wd_in[15]
+  PIN wd_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 160.825 0.070 160.895 ;
+    END
+  END wd_in[16]
+  PIN wd_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 161.875 0.070 161.945 ;
+    END
+  END wd_in[17]
+  PIN wd_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 162.925 0.070 162.995 ;
+    END
+  END wd_in[18]
+  PIN wd_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 163.975 0.070 164.045 ;
+    END
+  END wd_in[19]
+  PIN wd_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 165.025 0.070 165.095 ;
+    END
+  END wd_in[20]
+  PIN wd_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 166.075 0.070 166.145 ;
+    END
+  END wd_in[21]
+  PIN wd_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 167.125 0.070 167.195 ;
+    END
+  END wd_in[22]
+  PIN wd_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 168.175 0.070 168.245 ;
+    END
+  END wd_in[23]
+  PIN wd_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 169.225 0.070 169.295 ;
+    END
+  END wd_in[24]
+  PIN wd_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 170.275 0.070 170.345 ;
+    END
+  END wd_in[25]
+  PIN wd_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 171.325 0.070 171.395 ;
+    END
+  END wd_in[26]
+  PIN wd_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 172.375 0.070 172.445 ;
+    END
+  END wd_in[27]
+  PIN wd_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 173.425 0.070 173.495 ;
+    END
+  END wd_in[28]
+  PIN wd_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 174.475 0.070 174.545 ;
+    END
+  END wd_in[29]
+  PIN wd_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 175.525 0.070 175.595 ;
+    END
+  END wd_in[30]
+  PIN wd_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 176.575 0.070 176.645 ;
+    END
+  END wd_in[31]
+  PIN wd_in[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 177.625 0.070 177.695 ;
+    END
+  END wd_in[32]
+  PIN wd_in[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 178.675 0.070 178.745 ;
+    END
+  END wd_in[33]
+  PIN wd_in[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 179.725 0.070 179.795 ;
+    END
+  END wd_in[34]
+  PIN wd_in[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 180.775 0.070 180.845 ;
+    END
+  END wd_in[35]
+  PIN wd_in[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 181.825 0.070 181.895 ;
+    END
+  END wd_in[36]
+  PIN wd_in[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 182.875 0.070 182.945 ;
+    END
+  END wd_in[37]
+  PIN wd_in[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 183.925 0.070 183.995 ;
+    END
+  END wd_in[38]
+  PIN wd_in[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 184.975 0.070 185.045 ;
+    END
+  END wd_in[39]
+  PIN wd_in[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 186.025 0.070 186.095 ;
+    END
+  END wd_in[40]
+  PIN wd_in[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 187.075 0.070 187.145 ;
+    END
+  END wd_in[41]
+  PIN wd_in[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 188.125 0.070 188.195 ;
+    END
+  END wd_in[42]
+  PIN wd_in[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 189.175 0.070 189.245 ;
+    END
+  END wd_in[43]
+  PIN wd_in[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 190.225 0.070 190.295 ;
+    END
+  END wd_in[44]
+  PIN wd_in[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 191.275 0.070 191.345 ;
+    END
+  END wd_in[45]
+  PIN wd_in[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 192.325 0.070 192.395 ;
+    END
+  END wd_in[46]
+  PIN wd_in[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 193.375 0.070 193.445 ;
+    END
+  END wd_in[47]
+  PIN wd_in[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 194.425 0.070 194.495 ;
+    END
+  END wd_in[48]
+  PIN wd_in[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 195.475 0.070 195.545 ;
+    END
+  END wd_in[49]
+  PIN wd_in[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 196.525 0.070 196.595 ;
+    END
+  END wd_in[50]
+  PIN wd_in[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 197.575 0.070 197.645 ;
+    END
+  END wd_in[51]
+  PIN wd_in[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 198.625 0.070 198.695 ;
+    END
+  END wd_in[52]
+  PIN wd_in[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 199.675 0.070 199.745 ;
+    END
+  END wd_in[53]
+  PIN wd_in[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 200.725 0.070 200.795 ;
+    END
+  END wd_in[54]
+  PIN wd_in[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 201.775 0.070 201.845 ;
+    END
+  END wd_in[55]
+  PIN wd_in[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 202.825 0.070 202.895 ;
+    END
+  END wd_in[56]
+  PIN wd_in[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 203.875 0.070 203.945 ;
+    END
+  END wd_in[57]
+  PIN wd_in[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 204.925 0.070 204.995 ;
+    END
+  END wd_in[58]
+  PIN wd_in[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 205.975 0.070 206.045 ;
+    END
+  END wd_in[59]
+  PIN wd_in[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 207.025 0.070 207.095 ;
+    END
+  END wd_in[60]
+  PIN wd_in[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 208.075 0.070 208.145 ;
+    END
+  END wd_in[61]
+  PIN wd_in[62]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 209.125 0.070 209.195 ;
+    END
+  END wd_in[62]
+  PIN wd_in[63]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 210.175 0.070 210.245 ;
+    END
+  END wd_in[63]
+  PIN addr_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 215.005 0.070 215.075 ;
+    END
+  END addr_in[0]
+  PIN addr_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 216.055 0.070 216.125 ;
+    END
+  END addr_in[1]
+  PIN addr_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 217.105 0.070 217.175 ;
+    END
+  END addr_in[2]
+  PIN addr_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 218.155 0.070 218.225 ;
+    END
+  END addr_in[3]
+  PIN addr_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 219.205 0.070 219.275 ;
+    END
+  END addr_in[4]
+  PIN addr_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 220.255 0.070 220.325 ;
+    END
+  END addr_in[5]
+  PIN addr_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 221.305 0.070 221.375 ;
+    END
+  END addr_in[6]
+  PIN addr_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 222.355 0.070 222.425 ;
+    END
+  END addr_in[7]
+  PIN addr_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 223.405 0.070 223.475 ;
+    END
+  END addr_in[8]
+  PIN we_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 228.235 0.070 228.305 ;
+    END
+  END we_in
+  PIN ce_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 229.285 0.070 229.355 ;
+    END
+  END ce_in
+  PIN clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 230.335 0.070 230.405 ;
+    END
+  END clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER metal4 ;
+      RECT 1.960 2.100 2.240 235.900 ;
+      RECT 5.320 2.100 5.600 235.900 ;
+      RECT 8.680 2.100 8.960 235.900 ;
+      RECT 12.040 2.100 12.320 235.900 ;
+      RECT 15.400 2.100 15.680 235.900 ;
+      RECT 18.760 2.100 19.040 235.900 ;
+      RECT 22.120 2.100 22.400 235.900 ;
+      RECT 25.480 2.100 25.760 235.900 ;
+      RECT 28.840 2.100 29.120 235.900 ;
+      RECT 32.200 2.100 32.480 235.900 ;
+      RECT 35.560 2.100 35.840 235.900 ;
+      RECT 38.920 2.100 39.200 235.900 ;
+      RECT 42.280 2.100 42.560 235.900 ;
+      RECT 45.640 2.100 45.920 235.900 ;
+      RECT 49.000 2.100 49.280 235.900 ;
+      RECT 52.360 2.100 52.640 235.900 ;
+      RECT 55.720 2.100 56.000 235.900 ;
+      RECT 59.080 2.100 59.360 235.900 ;
+      RECT 62.440 2.100 62.720 235.900 ;
+      RECT 65.800 2.100 66.080 235.900 ;
+      RECT 69.160 2.100 69.440 235.900 ;
+      RECT 72.520 2.100 72.800 235.900 ;
+      RECT 75.880 2.100 76.160 235.900 ;
+      RECT 79.240 2.100 79.520 235.900 ;
+      RECT 82.600 2.100 82.880 235.900 ;
+      RECT 85.960 2.100 86.240 235.900 ;
+      RECT 89.320 2.100 89.600 235.900 ;
+      RECT 92.680 2.100 92.960 235.900 ;
+      RECT 96.040 2.100 96.320 235.900 ;
+      RECT 99.400 2.100 99.680 235.900 ;
+      RECT 102.760 2.100 103.040 235.900 ;
+      RECT 106.120 2.100 106.400 235.900 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER metal4 ;
+      RECT 3.640 2.100 3.920 235.900 ;
+      RECT 7.000 2.100 7.280 235.900 ;
+      RECT 10.360 2.100 10.640 235.900 ;
+      RECT 13.720 2.100 14.000 235.900 ;
+      RECT 17.080 2.100 17.360 235.900 ;
+      RECT 20.440 2.100 20.720 235.900 ;
+      RECT 23.800 2.100 24.080 235.900 ;
+      RECT 27.160 2.100 27.440 235.900 ;
+      RECT 30.520 2.100 30.800 235.900 ;
+      RECT 33.880 2.100 34.160 235.900 ;
+      RECT 37.240 2.100 37.520 235.900 ;
+      RECT 40.600 2.100 40.880 235.900 ;
+      RECT 43.960 2.100 44.240 235.900 ;
+      RECT 47.320 2.100 47.600 235.900 ;
+      RECT 50.680 2.100 50.960 235.900 ;
+      RECT 54.040 2.100 54.320 235.900 ;
+      RECT 57.400 2.100 57.680 235.900 ;
+      RECT 60.760 2.100 61.040 235.900 ;
+      RECT 64.120 2.100 64.400 235.900 ;
+      RECT 67.480 2.100 67.760 235.900 ;
+      RECT 70.840 2.100 71.120 235.900 ;
+      RECT 74.200 2.100 74.480 235.900 ;
+      RECT 77.560 2.100 77.840 235.900 ;
+      RECT 80.920 2.100 81.200 235.900 ;
+      RECT 84.280 2.100 84.560 235.900 ;
+      RECT 87.640 2.100 87.920 235.900 ;
+      RECT 91.000 2.100 91.280 235.900 ;
+      RECT 94.360 2.100 94.640 235.900 ;
+      RECT 97.720 2.100 98.000 235.900 ;
+      RECT 101.080 2.100 101.360 235.900 ;
+      RECT 104.440 2.100 104.720 235.900 ;
+    END
+  END VDD
+  OBS
+    LAYER metal1 ;
+    RECT 0 0 110.010 238.000 ;
+    LAYER metal2 ;
+    RECT 0 0 110.010 238.000 ;
+    LAYER metal3 ;
+    RECT 0.070 0 110.010 238.000 ;
+    RECT 0 0.000 0.070 2.065 ;
+    RECT 0 2.135 0.070 3.115 ;
+    RECT 0 3.185 0.070 4.165 ;
+    RECT 0 4.235 0.070 5.215 ;
+    RECT 0 5.285 0.070 6.265 ;
+    RECT 0 6.335 0.070 7.315 ;
+    RECT 0 7.385 0.070 8.365 ;
+    RECT 0 8.435 0.070 9.415 ;
+    RECT 0 9.485 0.070 10.465 ;
+    RECT 0 10.535 0.070 11.515 ;
+    RECT 0 11.585 0.070 12.565 ;
+    RECT 0 12.635 0.070 13.615 ;
+    RECT 0 13.685 0.070 14.665 ;
+    RECT 0 14.735 0.070 15.715 ;
+    RECT 0 15.785 0.070 16.765 ;
+    RECT 0 16.835 0.070 17.815 ;
+    RECT 0 17.885 0.070 18.865 ;
+    RECT 0 18.935 0.070 19.915 ;
+    RECT 0 19.985 0.070 20.965 ;
+    RECT 0 21.035 0.070 22.015 ;
+    RECT 0 22.085 0.070 23.065 ;
+    RECT 0 23.135 0.070 24.115 ;
+    RECT 0 24.185 0.070 25.165 ;
+    RECT 0 25.235 0.070 26.215 ;
+    RECT 0 26.285 0.070 27.265 ;
+    RECT 0 27.335 0.070 28.315 ;
+    RECT 0 28.385 0.070 29.365 ;
+    RECT 0 29.435 0.070 30.415 ;
+    RECT 0 30.485 0.070 31.465 ;
+    RECT 0 31.535 0.070 32.515 ;
+    RECT 0 32.585 0.070 33.565 ;
+    RECT 0 33.635 0.070 34.615 ;
+    RECT 0 34.685 0.070 35.665 ;
+    RECT 0 35.735 0.070 36.715 ;
+    RECT 0 36.785 0.070 37.765 ;
+    RECT 0 37.835 0.070 38.815 ;
+    RECT 0 38.885 0.070 39.865 ;
+    RECT 0 39.935 0.070 40.915 ;
+    RECT 0 40.985 0.070 41.965 ;
+    RECT 0 42.035 0.070 43.015 ;
+    RECT 0 43.085 0.070 44.065 ;
+    RECT 0 44.135 0.070 45.115 ;
+    RECT 0 45.185 0.070 46.165 ;
+    RECT 0 46.235 0.070 47.215 ;
+    RECT 0 47.285 0.070 48.265 ;
+    RECT 0 48.335 0.070 49.315 ;
+    RECT 0 49.385 0.070 50.365 ;
+    RECT 0 50.435 0.070 51.415 ;
+    RECT 0 51.485 0.070 52.465 ;
+    RECT 0 52.535 0.070 53.515 ;
+    RECT 0 53.585 0.070 54.565 ;
+    RECT 0 54.635 0.070 55.615 ;
+    RECT 0 55.685 0.070 56.665 ;
+    RECT 0 56.735 0.070 57.715 ;
+    RECT 0 57.785 0.070 58.765 ;
+    RECT 0 58.835 0.070 59.815 ;
+    RECT 0 59.885 0.070 60.865 ;
+    RECT 0 60.935 0.070 61.915 ;
+    RECT 0 61.985 0.070 62.965 ;
+    RECT 0 63.035 0.070 64.015 ;
+    RECT 0 64.085 0.070 65.065 ;
+    RECT 0 65.135 0.070 66.115 ;
+    RECT 0 66.185 0.070 67.165 ;
+    RECT 0 67.235 0.070 68.215 ;
+    RECT 0 68.285 0.070 73.045 ;
+    RECT 0 73.115 0.070 74.095 ;
+    RECT 0 74.165 0.070 75.145 ;
+    RECT 0 75.215 0.070 76.195 ;
+    RECT 0 76.265 0.070 77.245 ;
+    RECT 0 77.315 0.070 78.295 ;
+    RECT 0 78.365 0.070 79.345 ;
+    RECT 0 79.415 0.070 80.395 ;
+    RECT 0 80.465 0.070 81.445 ;
+    RECT 0 81.515 0.070 82.495 ;
+    RECT 0 82.565 0.070 83.545 ;
+    RECT 0 83.615 0.070 84.595 ;
+    RECT 0 84.665 0.070 85.645 ;
+    RECT 0 85.715 0.070 86.695 ;
+    RECT 0 86.765 0.070 87.745 ;
+    RECT 0 87.815 0.070 88.795 ;
+    RECT 0 88.865 0.070 89.845 ;
+    RECT 0 89.915 0.070 90.895 ;
+    RECT 0 90.965 0.070 91.945 ;
+    RECT 0 92.015 0.070 92.995 ;
+    RECT 0 93.065 0.070 94.045 ;
+    RECT 0 94.115 0.070 95.095 ;
+    RECT 0 95.165 0.070 96.145 ;
+    RECT 0 96.215 0.070 97.195 ;
+    RECT 0 97.265 0.070 98.245 ;
+    RECT 0 98.315 0.070 99.295 ;
+    RECT 0 99.365 0.070 100.345 ;
+    RECT 0 100.415 0.070 101.395 ;
+    RECT 0 101.465 0.070 102.445 ;
+    RECT 0 102.515 0.070 103.495 ;
+    RECT 0 103.565 0.070 104.545 ;
+    RECT 0 104.615 0.070 105.595 ;
+    RECT 0 105.665 0.070 106.645 ;
+    RECT 0 106.715 0.070 107.695 ;
+    RECT 0 107.765 0.070 108.745 ;
+    RECT 0 108.815 0.070 109.795 ;
+    RECT 0 109.865 0.070 110.845 ;
+    RECT 0 110.915 0.070 111.895 ;
+    RECT 0 111.965 0.070 112.945 ;
+    RECT 0 113.015 0.070 113.995 ;
+    RECT 0 114.065 0.070 115.045 ;
+    RECT 0 115.115 0.070 116.095 ;
+    RECT 0 116.165 0.070 117.145 ;
+    RECT 0 117.215 0.070 118.195 ;
+    RECT 0 118.265 0.070 119.245 ;
+    RECT 0 119.315 0.070 120.295 ;
+    RECT 0 120.365 0.070 121.345 ;
+    RECT 0 121.415 0.070 122.395 ;
+    RECT 0 122.465 0.070 123.445 ;
+    RECT 0 123.515 0.070 124.495 ;
+    RECT 0 124.565 0.070 125.545 ;
+    RECT 0 125.615 0.070 126.595 ;
+    RECT 0 126.665 0.070 127.645 ;
+    RECT 0 127.715 0.070 128.695 ;
+    RECT 0 128.765 0.070 129.745 ;
+    RECT 0 129.815 0.070 130.795 ;
+    RECT 0 130.865 0.070 131.845 ;
+    RECT 0 131.915 0.070 132.895 ;
+    RECT 0 132.965 0.070 133.945 ;
+    RECT 0 134.015 0.070 134.995 ;
+    RECT 0 135.065 0.070 136.045 ;
+    RECT 0 136.115 0.070 137.095 ;
+    RECT 0 137.165 0.070 138.145 ;
+    RECT 0 138.215 0.070 139.195 ;
+    RECT 0 139.265 0.070 144.025 ;
+    RECT 0 144.095 0.070 145.075 ;
+    RECT 0 145.145 0.070 146.125 ;
+    RECT 0 146.195 0.070 147.175 ;
+    RECT 0 147.245 0.070 148.225 ;
+    RECT 0 148.295 0.070 149.275 ;
+    RECT 0 149.345 0.070 150.325 ;
+    RECT 0 150.395 0.070 151.375 ;
+    RECT 0 151.445 0.070 152.425 ;
+    RECT 0 152.495 0.070 153.475 ;
+    RECT 0 153.545 0.070 154.525 ;
+    RECT 0 154.595 0.070 155.575 ;
+    RECT 0 155.645 0.070 156.625 ;
+    RECT 0 156.695 0.070 157.675 ;
+    RECT 0 157.745 0.070 158.725 ;
+    RECT 0 158.795 0.070 159.775 ;
+    RECT 0 159.845 0.070 160.825 ;
+    RECT 0 160.895 0.070 161.875 ;
+    RECT 0 161.945 0.070 162.925 ;
+    RECT 0 162.995 0.070 163.975 ;
+    RECT 0 164.045 0.070 165.025 ;
+    RECT 0 165.095 0.070 166.075 ;
+    RECT 0 166.145 0.070 167.125 ;
+    RECT 0 167.195 0.070 168.175 ;
+    RECT 0 168.245 0.070 169.225 ;
+    RECT 0 169.295 0.070 170.275 ;
+    RECT 0 170.345 0.070 171.325 ;
+    RECT 0 171.395 0.070 172.375 ;
+    RECT 0 172.445 0.070 173.425 ;
+    RECT 0 173.495 0.070 174.475 ;
+    RECT 0 174.545 0.070 175.525 ;
+    RECT 0 175.595 0.070 176.575 ;
+    RECT 0 176.645 0.070 177.625 ;
+    RECT 0 177.695 0.070 178.675 ;
+    RECT 0 178.745 0.070 179.725 ;
+    RECT 0 179.795 0.070 180.775 ;
+    RECT 0 180.845 0.070 181.825 ;
+    RECT 0 181.895 0.070 182.875 ;
+    RECT 0 182.945 0.070 183.925 ;
+    RECT 0 183.995 0.070 184.975 ;
+    RECT 0 185.045 0.070 186.025 ;
+    RECT 0 186.095 0.070 187.075 ;
+    RECT 0 187.145 0.070 188.125 ;
+    RECT 0 188.195 0.070 189.175 ;
+    RECT 0 189.245 0.070 190.225 ;
+    RECT 0 190.295 0.070 191.275 ;
+    RECT 0 191.345 0.070 192.325 ;
+    RECT 0 192.395 0.070 193.375 ;
+    RECT 0 193.445 0.070 194.425 ;
+    RECT 0 194.495 0.070 195.475 ;
+    RECT 0 195.545 0.070 196.525 ;
+    RECT 0 196.595 0.070 197.575 ;
+    RECT 0 197.645 0.070 198.625 ;
+    RECT 0 198.695 0.070 199.675 ;
+    RECT 0 199.745 0.070 200.725 ;
+    RECT 0 200.795 0.070 201.775 ;
+    RECT 0 201.845 0.070 202.825 ;
+    RECT 0 202.895 0.070 203.875 ;
+    RECT 0 203.945 0.070 204.925 ;
+    RECT 0 204.995 0.070 205.975 ;
+    RECT 0 206.045 0.070 207.025 ;
+    RECT 0 207.095 0.070 208.075 ;
+    RECT 0 208.145 0.070 209.125 ;
+    RECT 0 209.195 0.070 210.175 ;
+    RECT 0 210.245 0.070 215.005 ;
+    RECT 0 215.075 0.070 216.055 ;
+    RECT 0 216.125 0.070 217.105 ;
+    RECT 0 217.175 0.070 218.155 ;
+    RECT 0 218.225 0.070 219.205 ;
+    RECT 0 219.275 0.070 220.255 ;
+    RECT 0 220.325 0.070 221.305 ;
+    RECT 0 221.375 0.070 222.355 ;
+    RECT 0 222.425 0.070 223.405 ;
+    RECT 0 223.475 0.070 228.235 ;
+    RECT 0 228.305 0.070 229.285 ;
+    RECT 0 229.355 0.070 230.335 ;
+    RECT 0 230.405 0.070 238.000 ;
+    LAYER metal4 ;
+    RECT 0 0 110.010 2.100 ;
+    RECT 0 235.900 110.010 238.000 ;
+    RECT 0.000 2.100 1.960 235.900 ;
+    RECT 2.240 2.100 3.640 235.900 ;
+    RECT 3.920 2.100 5.320 235.900 ;
+    RECT 5.600 2.100 7.000 235.900 ;
+    RECT 7.280 2.100 8.680 235.900 ;
+    RECT 8.960 2.100 10.360 235.900 ;
+    RECT 10.640 2.100 12.040 235.900 ;
+    RECT 12.320 2.100 13.720 235.900 ;
+    RECT 14.000 2.100 15.400 235.900 ;
+    RECT 15.680 2.100 17.080 235.900 ;
+    RECT 17.360 2.100 18.760 235.900 ;
+    RECT 19.040 2.100 20.440 235.900 ;
+    RECT 20.720 2.100 22.120 235.900 ;
+    RECT 22.400 2.100 23.800 235.900 ;
+    RECT 24.080 2.100 25.480 235.900 ;
+    RECT 25.760 2.100 27.160 235.900 ;
+    RECT 27.440 2.100 28.840 235.900 ;
+    RECT 29.120 2.100 30.520 235.900 ;
+    RECT 30.800 2.100 32.200 235.900 ;
+    RECT 32.480 2.100 33.880 235.900 ;
+    RECT 34.160 2.100 35.560 235.900 ;
+    RECT 35.840 2.100 37.240 235.900 ;
+    RECT 37.520 2.100 38.920 235.900 ;
+    RECT 39.200 2.100 40.600 235.900 ;
+    RECT 40.880 2.100 42.280 235.900 ;
+    RECT 42.560 2.100 43.960 235.900 ;
+    RECT 44.240 2.100 45.640 235.900 ;
+    RECT 45.920 2.100 47.320 235.900 ;
+    RECT 47.600 2.100 49.000 235.900 ;
+    RECT 49.280 2.100 50.680 235.900 ;
+    RECT 50.960 2.100 52.360 235.900 ;
+    RECT 52.640 2.100 54.040 235.900 ;
+    RECT 54.320 2.100 55.720 235.900 ;
+    RECT 56.000 2.100 57.400 235.900 ;
+    RECT 57.680 2.100 59.080 235.900 ;
+    RECT 59.360 2.100 60.760 235.900 ;
+    RECT 61.040 2.100 62.440 235.900 ;
+    RECT 62.720 2.100 64.120 235.900 ;
+    RECT 64.400 2.100 65.800 235.900 ;
+    RECT 66.080 2.100 67.480 235.900 ;
+    RECT 67.760 2.100 69.160 235.900 ;
+    RECT 69.440 2.100 70.840 235.900 ;
+    RECT 71.120 2.100 72.520 235.900 ;
+    RECT 72.800 2.100 74.200 235.900 ;
+    RECT 74.480 2.100 75.880 235.900 ;
+    RECT 76.160 2.100 77.560 235.900 ;
+    RECT 77.840 2.100 79.240 235.900 ;
+    RECT 79.520 2.100 80.920 235.900 ;
+    RECT 81.200 2.100 82.600 235.900 ;
+    RECT 82.880 2.100 84.280 235.900 ;
+    RECT 84.560 2.100 85.960 235.900 ;
+    RECT 86.240 2.100 87.640 235.900 ;
+    RECT 87.920 2.100 89.320 235.900 ;
+    RECT 89.600 2.100 91.000 235.900 ;
+    RECT 91.280 2.100 92.680 235.900 ;
+    RECT 92.960 2.100 94.360 235.900 ;
+    RECT 94.640 2.100 96.040 235.900 ;
+    RECT 96.320 2.100 97.720 235.900 ;
+    RECT 98.000 2.100 99.400 235.900 ;
+    RECT 99.680 2.100 101.080 235.900 ;
+    RECT 101.360 2.100 102.760 235.900 ;
+    RECT 103.040 2.100 104.440 235.900 ;
+    RECT 104.720 2.100 106.120 235.900 ;
+    RECT 106.400 2.100 110.010 235.900 ;
+    LAYER OVERLAP ;
+    RECT 0 0 110.010 238.000 ;
+  END
+END fakeram45_512x64
+
+END LIBRARY

Enablements/NanGate45/lef/fakeram45_64x124.lef

+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+MACRO fakeram45_64x124
+  FOREIGN fakeram45_64x124 0 0 ;
+  SYMMETRY X Y R90 ;
+  SIZE 80.560 BY 121.800 ;
+  CLASS BLOCK ;
+  PIN w_mask_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.065 0.070 2.135 ;
+    END
+  END w_mask_in[0]
+  PIN w_mask_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.275 0.070 2.345 ;
+    END
+  END w_mask_in[1]
+  PIN w_mask_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.485 0.070 2.555 ;
+    END
+  END w_mask_in[2]
+  PIN w_mask_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.695 0.070 2.765 ;
+    END
+  END w_mask_in[3]
+  PIN w_mask_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.905 0.070 2.975 ;
+    END
+  END w_mask_in[4]
+  PIN w_mask_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.115 0.070 3.185 ;
+    END
+  END w_mask_in[5]
+  PIN w_mask_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.325 0.070 3.395 ;
+    END
+  END w_mask_in[6]
+  PIN w_mask_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.535 0.070 3.605 ;
+    END
+  END w_mask_in[7]
+  PIN w_mask_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.745 0.070 3.815 ;
+    END
+  END w_mask_in[8]
+  PIN w_mask_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.955 0.070 4.025 ;
+    END
+  END w_mask_in[9]
+  PIN w_mask_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 4.165 0.070 4.235 ;
+    END
+  END w_mask_in[10]
+  PIN w_mask_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 4.375 0.070 4.445 ;
+    END
+  END w_mask_in[11]
+  PIN w_mask_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 4.585 0.070 4.655 ;
+    END
+  END w_mask_in[12]
+  PIN w_mask_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 4.795 0.070 4.865 ;
+    END
+  END w_mask_in[13]
+  PIN w_mask_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.005 0.070 5.075 ;
+    END
+  END w_mask_in[14]
+  PIN w_mask_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.215 0.070 5.285 ;
+    END
+  END w_mask_in[15]
+  PIN w_mask_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.425 0.070 5.495 ;
+    END
+  END w_mask_in[16]
+  PIN w_mask_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.635 0.070 5.705 ;
+    END
+  END w_mask_in[17]
+  PIN w_mask_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.845 0.070 5.915 ;
+    END
+  END w_mask_in[18]
+  PIN w_mask_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.055 0.070 6.125 ;
+    END
+  END w_mask_in[19]
+  PIN w_mask_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.265 0.070 6.335 ;
+    END
+  END w_mask_in[20]
+  PIN w_mask_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.475 0.070 6.545 ;
+    END
+  END w_mask_in[21]
+  PIN w_mask_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.685 0.070 6.755 ;
+    END
+  END w_mask_in[22]
+  PIN w_mask_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.895 0.070 6.965 ;
+    END
+  END w_mask_in[23]
+  PIN w_mask_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.105 0.070 7.175 ;
+    END
+  END w_mask_in[24]
+  PIN w_mask_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.315 0.070 7.385 ;
+    END
+  END w_mask_in[25]
+  PIN w_mask_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.525 0.070 7.595 ;
+    END
+  END w_mask_in[26]
+  PIN w_mask_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.735 0.070 7.805 ;
+    END
+  END w_mask_in[27]
+  PIN w_mask_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.945 0.070 8.015 ;
+    END
+  END w_mask_in[28]
+  PIN w_mask_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.155 0.070 8.225 ;
+    END
+  END w_mask_in[29]
+  PIN w_mask_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.365 0.070 8.435 ;
+    END
+  END w_mask_in[30]
+  PIN w_mask_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.575 0.070 8.645 ;
+    END
+  END w_mask_in[31]
+  PIN w_mask_in[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.785 0.070 8.855 ;
+    END
+  END w_mask_in[32]
+  PIN w_mask_in[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.995 0.070 9.065 ;
+    END
+  END w_mask_in[33]
+  PIN w_mask_in[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 9.205 0.070 9.275 ;
+    END
+  END w_mask_in[34]
+  PIN w_mask_in[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 9.415 0.070 9.485 ;
+    END
+  END w_mask_in[35]
+  PIN w_mask_in[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 9.625 0.070 9.695 ;
+    END
+  END w_mask_in[36]
+  PIN w_mask_in[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 9.835 0.070 9.905 ;
+    END
+  END w_mask_in[37]
+  PIN w_mask_in[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.045 0.070 10.115 ;
+    END
+  END w_mask_in[38]
+  PIN w_mask_in[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.255 0.070 10.325 ;
+    END
+  END w_mask_in[39]
+  PIN w_mask_in[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.465 0.070 10.535 ;
+    END
+  END w_mask_in[40]
+  PIN w_mask_in[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.675 0.070 10.745 ;
+    END
+  END w_mask_in[41]
+  PIN w_mask_in[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.885 0.070 10.955 ;
+    END
+  END w_mask_in[42]
+  PIN w_mask_in[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.095 0.070 11.165 ;
+    END
+  END w_mask_in[43]
+  PIN w_mask_in[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.305 0.070 11.375 ;
+    END
+  END w_mask_in[44]
+  PIN w_mask_in[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.515 0.070 11.585 ;
+    END
+  END w_mask_in[45]
+  PIN w_mask_in[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.725 0.070 11.795 ;
+    END
+  END w_mask_in[46]
+  PIN w_mask_in[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.935 0.070 12.005 ;
+    END
+  END w_mask_in[47]
+  PIN w_mask_in[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.145 0.070 12.215 ;
+    END
+  END w_mask_in[48]
+  PIN w_mask_in[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.355 0.070 12.425 ;
+    END
+  END w_mask_in[49]
+  PIN w_mask_in[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.565 0.070 12.635 ;
+    END
+  END w_mask_in[50]
+  PIN w_mask_in[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.775 0.070 12.845 ;
+    END
+  END w_mask_in[51]
+  PIN w_mask_in[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.985 0.070 13.055 ;
+    END
+  END w_mask_in[52]
+  PIN w_mask_in[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 13.195 0.070 13.265 ;
+    END
+  END w_mask_in[53]
+  PIN w_mask_in[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 13.405 0.070 13.475 ;
+    END
+  END w_mask_in[54]
+  PIN w_mask_in[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 13.615 0.070 13.685 ;
+    END
+  END w_mask_in[55]
+  PIN w_mask_in[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 13.825 0.070 13.895 ;
+    END
+  END w_mask_in[56]
+  PIN w_mask_in[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.035 0.070 14.105 ;
+    END
+  END w_mask_in[57]
+  PIN w_mask_in[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.245 0.070 14.315 ;
+    END
+  END w_mask_in[58]
+  PIN w_mask_in[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.455 0.070 14.525 ;
+    END
+  END w_mask_in[59]
+  PIN w_mask_in[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.665 0.070 14.735 ;
+    END
+  END w_mask_in[60]
+  PIN w_mask_in[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.875 0.070 14.945 ;
+    END
+  END w_mask_in[61]
+  PIN w_mask_in[62]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.085 0.070 15.155 ;
+    END
+  END w_mask_in[62]
+  PIN w_mask_in[63]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.295 0.070 15.365 ;
+    END
+  END w_mask_in[63]
+  PIN w_mask_in[64]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.505 0.070 15.575 ;
+    END
+  END w_mask_in[64]
+  PIN w_mask_in[65]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.715 0.070 15.785 ;
+    END
+  END w_mask_in[65]
+  PIN w_mask_in[66]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.925 0.070 15.995 ;
+    END
+  END w_mask_in[66]
+  PIN w_mask_in[67]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.135 0.070 16.205 ;
+    END
+  END w_mask_in[67]
+  PIN w_mask_in[68]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.345 0.070 16.415 ;
+    END
+  END w_mask_in[68]
+  PIN w_mask_in[69]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.555 0.070 16.625 ;
+    END
+  END w_mask_in[69]
+  PIN w_mask_in[70]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.765 0.070 16.835 ;
+    END
+  END w_mask_in[70]
+  PIN w_mask_in[71]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.975 0.070 17.045 ;
+    END
+  END w_mask_in[71]
+  PIN w_mask_in[72]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 17.185 0.070 17.255 ;
+    END
+  END w_mask_in[72]
+  PIN w_mask_in[73]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 17.395 0.070 17.465 ;
+    END
+  END w_mask_in[73]
+  PIN w_mask_in[74]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 17.605 0.070 17.675 ;
+    END
+  END w_mask_in[74]
+  PIN w_mask_in[75]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 17.815 0.070 17.885 ;
+    END
+  END w_mask_in[75]
+  PIN w_mask_in[76]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 18.025 0.070 18.095 ;
+    END
+  END w_mask_in[76]
+  PIN w_mask_in[77]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 18.235 0.070 18.305 ;
+    END
+  END w_mask_in[77]
+  PIN w_mask_in[78]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 18.445 0.070 18.515 ;
+    END
+  END w_mask_in[78]
+  PIN w_mask_in[79]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 18.655 0.070 18.725 ;
+    END
+  END w_mask_in[79]
+  PIN w_mask_in[80]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 18.865 0.070 18.935 ;
+    END
+  END w_mask_in[80]
+  PIN w_mask_in[81]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.075 0.070 19.145 ;
+    END
+  END w_mask_in[81]
+  PIN w_mask_in[82]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.285 0.070 19.355 ;
+    END
+  END w_mask_in[82]
+  PIN w_mask_in[83]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.495 0.070 19.565 ;
+    END
+  END w_mask_in[83]
+  PIN w_mask_in[84]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.705 0.070 19.775 ;
+    END
+  END w_mask_in[84]
+  PIN w_mask_in[85]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.915 0.070 19.985 ;
+    END
+  END w_mask_in[85]
+  PIN w_mask_in[86]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.125 0.070 20.195 ;
+    END
+  END w_mask_in[86]
+  PIN w_mask_in[87]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.335 0.070 20.405 ;
+    END
+  END w_mask_in[87]
+  PIN w_mask_in[88]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.545 0.070 20.615 ;
+    END
+  END w_mask_in[88]
+  PIN w_mask_in[89]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.755 0.070 20.825 ;
+    END
+  END w_mask_in[89]
+  PIN w_mask_in[90]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.965 0.070 21.035 ;
+    END
+  END w_mask_in[90]
+  PIN w_mask_in[91]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 21.175 0.070 21.245 ;
+    END
+  END w_mask_in[91]
+  PIN w_mask_in[92]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 21.385 0.070 21.455 ;
+    END
+  END w_mask_in[92]
+  PIN w_mask_in[93]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 21.595 0.070 21.665 ;
+    END
+  END w_mask_in[93]
+  PIN w_mask_in[94]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 21.805 0.070 21.875 ;
+    END
+  END w_mask_in[94]
+  PIN w_mask_in[95]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.015 0.070 22.085 ;
+    END
+  END w_mask_in[95]
+  PIN w_mask_in[96]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.225 0.070 22.295 ;
+    END
+  END w_mask_in[96]
+  PIN w_mask_in[97]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.435 0.070 22.505 ;
+    END
+  END w_mask_in[97]
+  PIN w_mask_in[98]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.645 0.070 22.715 ;
+    END
+  END w_mask_in[98]
+  PIN w_mask_in[99]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.855 0.070 22.925 ;
+    END
+  END w_mask_in[99]
+  PIN w_mask_in[100]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.065 0.070 23.135 ;
+    END
+  END w_mask_in[100]
+  PIN w_mask_in[101]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.275 0.070 23.345 ;
+    END
+  END w_mask_in[101]
+  PIN w_mask_in[102]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.485 0.070 23.555 ;
+    END
+  END w_mask_in[102]
+  PIN w_mask_in[103]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.695 0.070 23.765 ;
+    END
+  END w_mask_in[103]
+  PIN w_mask_in[104]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.905 0.070 23.975 ;
+    END
+  END w_mask_in[104]
+  PIN w_mask_in[105]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.115 0.070 24.185 ;
+    END
+  END w_mask_in[105]
+  PIN w_mask_in[106]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.325 0.070 24.395 ;
+    END
+  END w_mask_in[106]
+  PIN w_mask_in[107]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.535 0.070 24.605 ;
+    END
+  END w_mask_in[107]
+  PIN w_mask_in[108]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.745 0.070 24.815 ;
+    END
+  END w_mask_in[108]
+  PIN w_mask_in[109]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.955 0.070 25.025 ;
+    END
+  END w_mask_in[109]
+  PIN w_mask_in[110]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 25.165 0.070 25.235 ;
+    END
+  END w_mask_in[110]
+  PIN w_mask_in[111]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 25.375 0.070 25.445 ;
+    END
+  END w_mask_in[111]
+  PIN w_mask_in[112]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 25.585 0.070 25.655 ;
+    END
+  END w_mask_in[112]
+  PIN w_mask_in[113]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 25.795 0.070 25.865 ;
+    END
+  END w_mask_in[113]
+  PIN w_mask_in[114]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 26.005 0.070 26.075 ;
+    END
+  END w_mask_in[114]
+  PIN w_mask_in[115]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 26.215 0.070 26.285 ;
+    END
+  END w_mask_in[115]
+  PIN w_mask_in[116]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 26.425 0.070 26.495 ;
+    END
+  END w_mask_in[116]
+  PIN w_mask_in[117]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 26.635 0.070 26.705 ;
+    END
+  END w_mask_in[117]
+  PIN w_mask_in[118]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 26.845 0.070 26.915 ;
+    END
+  END w_mask_in[118]
+  PIN w_mask_in[119]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 27.055 0.070 27.125 ;
+    END
+  END w_mask_in[119]
+  PIN w_mask_in[120]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 27.265 0.070 27.335 ;
+    END
+  END w_mask_in[120]
+  PIN w_mask_in[121]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 27.475 0.070 27.545 ;
+    END
+  END w_mask_in[121]
+  PIN w_mask_in[122]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 27.685 0.070 27.755 ;
+    END
+  END w_mask_in[122]
+  PIN w_mask_in[123]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 27.895 0.070 27.965 ;
+    END
+  END w_mask_in[123]
+  PIN rd_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 37.135 0.070 37.205 ;
+    END
+  END rd_out[0]
+  PIN rd_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 37.345 0.070 37.415 ;
+    END
+  END rd_out[1]
+  PIN rd_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 37.555 0.070 37.625 ;
+    END
+  END rd_out[2]
+  PIN rd_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 37.765 0.070 37.835 ;
+    END
+  END rd_out[3]
+  PIN rd_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 37.975 0.070 38.045 ;
+    END
+  END rd_out[4]
+  PIN rd_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 38.185 0.070 38.255 ;
+    END
+  END rd_out[5]
+  PIN rd_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 38.395 0.070 38.465 ;
+    END
+  END rd_out[6]
+  PIN rd_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 38.605 0.070 38.675 ;
+    END
+  END rd_out[7]
+  PIN rd_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 38.815 0.070 38.885 ;
+    END
+  END rd_out[8]
+  PIN rd_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 39.025 0.070 39.095 ;
+    END
+  END rd_out[9]
+  PIN rd_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 39.235 0.070 39.305 ;
+    END
+  END rd_out[10]
+  PIN rd_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 39.445 0.070 39.515 ;
+    END
+  END rd_out[11]
+  PIN rd_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 39.655 0.070 39.725 ;
+    END
+  END rd_out[12]
+  PIN rd_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 39.865 0.070 39.935 ;
+    END
+  END rd_out[13]
+  PIN rd_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 40.075 0.070 40.145 ;
+    END
+  END rd_out[14]
+  PIN rd_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 40.285 0.070 40.355 ;
+    END
+  END rd_out[15]
+  PIN rd_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 40.495 0.070 40.565 ;
+    END
+  END rd_out[16]
+  PIN rd_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 40.705 0.070 40.775 ;
+    END
+  END rd_out[17]
+  PIN rd_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 40.915 0.070 40.985 ;
+    END
+  END rd_out[18]
+  PIN rd_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 41.125 0.070 41.195 ;
+    END
+  END rd_out[19]
+  PIN rd_out[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 41.335 0.070 41.405 ;
+    END
+  END rd_out[20]
+  PIN rd_out[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 41.545 0.070 41.615 ;
+    END
+  END rd_out[21]
+  PIN rd_out[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 41.755 0.070 41.825 ;
+    END
+  END rd_out[22]
+  PIN rd_out[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 41.965 0.070 42.035 ;
+    END
+  END rd_out[23]
+  PIN rd_out[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 42.175 0.070 42.245 ;
+    END
+  END rd_out[24]
+  PIN rd_out[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 42.385 0.070 42.455 ;
+    END
+  END rd_out[25]
+  PIN rd_out[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 42.595 0.070 42.665 ;
+    END
+  END rd_out[26]
+  PIN rd_out[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 42.805 0.070 42.875 ;
+    END
+  END rd_out[27]
+  PIN rd_out[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 43.015 0.070 43.085 ;
+    END
+  END rd_out[28]
+  PIN rd_out[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 43.225 0.070 43.295 ;
+    END
+  END rd_out[29]
+  PIN rd_out[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 43.435 0.070 43.505 ;
+    END
+  END rd_out[30]
+  PIN rd_out[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 43.645 0.070 43.715 ;
+    END
+  END rd_out[31]
+  PIN rd_out[32]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 43.855 0.070 43.925 ;
+    END
+  END rd_out[32]
+  PIN rd_out[33]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 44.065 0.070 44.135 ;
+    END
+  END rd_out[33]
+  PIN rd_out[34]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 44.275 0.070 44.345 ;
+    END
+  END rd_out[34]
+  PIN rd_out[35]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 44.485 0.070 44.555 ;
+    END
+  END rd_out[35]
+  PIN rd_out[36]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 44.695 0.070 44.765 ;
+    END
+  END rd_out[36]
+  PIN rd_out[37]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 44.905 0.070 44.975 ;
+    END
+  END rd_out[37]
+  PIN rd_out[38]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 45.115 0.070 45.185 ;
+    END
+  END rd_out[38]
+  PIN rd_out[39]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 45.325 0.070 45.395 ;
+    END
+  END rd_out[39]
+  PIN rd_out[40]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 45.535 0.070 45.605 ;
+    END
+  END rd_out[40]
+  PIN rd_out[41]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 45.745 0.070 45.815 ;
+    END
+  END rd_out[41]
+  PIN rd_out[42]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 45.955 0.070 46.025 ;
+    END
+  END rd_out[42]
+  PIN rd_out[43]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 46.165 0.070 46.235 ;
+    END
+  END rd_out[43]
+  PIN rd_out[44]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 46.375 0.070 46.445 ;
+    END
+  END rd_out[44]
+  PIN rd_out[45]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 46.585 0.070 46.655 ;
+    END
+  END rd_out[45]
+  PIN rd_out[46]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 46.795 0.070 46.865 ;
+    END
+  END rd_out[46]
+  PIN rd_out[47]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 47.005 0.070 47.075 ;
+    END
+  END rd_out[47]
+  PIN rd_out[48]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 47.215 0.070 47.285 ;
+    END
+  END rd_out[48]
+  PIN rd_out[49]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 47.425 0.070 47.495 ;
+    END
+  END rd_out[49]
+  PIN rd_out[50]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 47.635 0.070 47.705 ;
+    END
+  END rd_out[50]
+  PIN rd_out[51]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 47.845 0.070 47.915 ;
+    END
+  END rd_out[51]
+  PIN rd_out[52]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 48.055 0.070 48.125 ;
+    END
+  END rd_out[52]
+  PIN rd_out[53]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 48.265 0.070 48.335 ;
+    END
+  END rd_out[53]
+  PIN rd_out[54]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 48.475 0.070 48.545 ;
+    END
+  END rd_out[54]
+  PIN rd_out[55]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 48.685 0.070 48.755 ;
+    END
+  END rd_out[55]
+  PIN rd_out[56]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 48.895 0.070 48.965 ;
+    END
+  END rd_out[56]
+  PIN rd_out[57]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 49.105 0.070 49.175 ;
+    END
+  END rd_out[57]
+  PIN rd_out[58]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 49.315 0.070 49.385 ;
+    END
+  END rd_out[58]
+  PIN rd_out[59]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 49.525 0.070 49.595 ;
+    END
+  END rd_out[59]
+  PIN rd_out[60]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 49.735 0.070 49.805 ;
+    END
+  END rd_out[60]
+  PIN rd_out[61]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 49.945 0.070 50.015 ;
+    END
+  END rd_out[61]
+  PIN rd_out[62]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 50.155 0.070 50.225 ;
+    END
+  END rd_out[62]
+  PIN rd_out[63]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 50.365 0.070 50.435 ;
+    END
+  END rd_out[63]
+  PIN rd_out[64]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 50.575 0.070 50.645 ;
+    END
+  END rd_out[64]
+  PIN rd_out[65]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 50.785 0.070 50.855 ;
+    END
+  END rd_out[65]
+  PIN rd_out[66]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 50.995 0.070 51.065 ;
+    END
+  END rd_out[66]
+  PIN rd_out[67]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 51.205 0.070 51.275 ;
+    END
+  END rd_out[67]
+  PIN rd_out[68]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 51.415 0.070 51.485 ;
+    END
+  END rd_out[68]
+  PIN rd_out[69]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 51.625 0.070 51.695 ;
+    END
+  END rd_out[69]
+  PIN rd_out[70]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 51.835 0.070 51.905 ;
+    END
+  END rd_out[70]
+  PIN rd_out[71]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 52.045 0.070 52.115 ;
+    END
+  END rd_out[71]
+  PIN rd_out[72]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 52.255 0.070 52.325 ;
+    END
+  END rd_out[72]
+  PIN rd_out[73]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 52.465 0.070 52.535 ;
+    END
+  END rd_out[73]
+  PIN rd_out[74]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 52.675 0.070 52.745 ;
+    END
+  END rd_out[74]
+  PIN rd_out[75]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 52.885 0.070 52.955 ;
+    END
+  END rd_out[75]
+  PIN rd_out[76]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 53.095 0.070 53.165 ;
+    END
+  END rd_out[76]
+  PIN rd_out[77]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 53.305 0.070 53.375 ;
+    END
+  END rd_out[77]
+  PIN rd_out[78]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 53.515 0.070 53.585 ;
+    END
+  END rd_out[78]
+  PIN rd_out[79]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 53.725 0.070 53.795 ;
+    END
+  END rd_out[79]
+  PIN rd_out[80]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 53.935 0.070 54.005 ;
+    END
+  END rd_out[80]
+  PIN rd_out[81]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 54.145 0.070 54.215 ;
+    END
+  END rd_out[81]
+  PIN rd_out[82]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 54.355 0.070 54.425 ;
+    END
+  END rd_out[82]
+  PIN rd_out[83]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 54.565 0.070 54.635 ;
+    END
+  END rd_out[83]
+  PIN rd_out[84]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 54.775 0.070 54.845 ;
+    END
+  END rd_out[84]
+  PIN rd_out[85]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 54.985 0.070 55.055 ;
+    END
+  END rd_out[85]
+  PIN rd_out[86]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 55.195 0.070 55.265 ;
+    END
+  END rd_out[86]
+  PIN rd_out[87]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 55.405 0.070 55.475 ;
+    END
+  END rd_out[87]
+  PIN rd_out[88]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 55.615 0.070 55.685 ;
+    END
+  END rd_out[88]
+  PIN rd_out[89]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 55.825 0.070 55.895 ;
+    END
+  END rd_out[89]
+  PIN rd_out[90]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 56.035 0.070 56.105 ;
+    END
+  END rd_out[90]
+  PIN rd_out[91]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 56.245 0.070 56.315 ;
+    END
+  END rd_out[91]
+  PIN rd_out[92]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 56.455 0.070 56.525 ;
+    END
+  END rd_out[92]
+  PIN rd_out[93]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 56.665 0.070 56.735 ;
+    END
+  END rd_out[93]
+  PIN rd_out[94]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 56.875 0.070 56.945 ;
+    END
+  END rd_out[94]
+  PIN rd_out[95]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 57.085 0.070 57.155 ;
+    END
+  END rd_out[95]
+  PIN rd_out[96]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 57.295 0.070 57.365 ;
+    END
+  END rd_out[96]
+  PIN rd_out[97]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 57.505 0.070 57.575 ;
+    END
+  END rd_out[97]
+  PIN rd_out[98]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 57.715 0.070 57.785 ;
+    END
+  END rd_out[98]
+  PIN rd_out[99]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 57.925 0.070 57.995 ;
+    END
+  END rd_out[99]
+  PIN rd_out[100]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 58.135 0.070 58.205 ;
+    END
+  END rd_out[100]
+  PIN rd_out[101]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 58.345 0.070 58.415 ;
+    END
+  END rd_out[101]
+  PIN rd_out[102]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 58.555 0.070 58.625 ;
+    END
+  END rd_out[102]
+  PIN rd_out[103]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 58.765 0.070 58.835 ;
+    END
+  END rd_out[103]
+  PIN rd_out[104]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 58.975 0.070 59.045 ;
+    END
+  END rd_out[104]
+  PIN rd_out[105]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 59.185 0.070 59.255 ;
+    END
+  END rd_out[105]
+  PIN rd_out[106]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 59.395 0.070 59.465 ;
+    END
+  END rd_out[106]
+  PIN rd_out[107]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 59.605 0.070 59.675 ;
+    END
+  END rd_out[107]
+  PIN rd_out[108]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 59.815 0.070 59.885 ;
+    END
+  END rd_out[108]
+  PIN rd_out[109]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 60.025 0.070 60.095 ;
+    END
+  END rd_out[109]
+  PIN rd_out[110]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 60.235 0.070 60.305 ;
+    END
+  END rd_out[110]
+  PIN rd_out[111]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 60.445 0.070 60.515 ;
+    END
+  END rd_out[111]
+  PIN rd_out[112]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 60.655 0.070 60.725 ;
+    END
+  END rd_out[112]
+  PIN rd_out[113]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 60.865 0.070 60.935 ;
+    END
+  END rd_out[113]
+  PIN rd_out[114]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 61.075 0.070 61.145 ;
+    END
+  END rd_out[114]
+  PIN rd_out[115]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 61.285 0.070 61.355 ;
+    END
+  END rd_out[115]
+  PIN rd_out[116]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 61.495 0.070 61.565 ;
+    END
+  END rd_out[116]
+  PIN rd_out[117]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 61.705 0.070 61.775 ;
+    END
+  END rd_out[117]
+  PIN rd_out[118]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 61.915 0.070 61.985 ;
+    END
+  END rd_out[118]
+  PIN rd_out[119]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 62.125 0.070 62.195 ;
+    END
+  END rd_out[119]
+  PIN rd_out[120]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 62.335 0.070 62.405 ;
+    END
+  END rd_out[120]
+  PIN rd_out[121]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 62.545 0.070 62.615 ;
+    END
+  END rd_out[121]
+  PIN rd_out[122]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 62.755 0.070 62.825 ;
+    END
+  END rd_out[122]
+  PIN rd_out[123]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 62.965 0.070 63.035 ;
+    END
+  END rd_out[123]
+  PIN wd_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 72.205 0.070 72.275 ;
+    END
+  END wd_in[0]
+  PIN wd_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 72.415 0.070 72.485 ;
+    END
+  END wd_in[1]
+  PIN wd_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 72.625 0.070 72.695 ;
+    END
+  END wd_in[2]
+  PIN wd_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 72.835 0.070 72.905 ;
+    END
+  END wd_in[3]
+  PIN wd_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 73.045 0.070 73.115 ;
+    END
+  END wd_in[4]
+  PIN wd_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 73.255 0.070 73.325 ;
+    END
+  END wd_in[5]
+  PIN wd_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 73.465 0.070 73.535 ;
+    END
+  END wd_in[6]
+  PIN wd_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 73.675 0.070 73.745 ;
+    END
+  END wd_in[7]
+  PIN wd_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 73.885 0.070 73.955 ;
+    END
+  END wd_in[8]
+  PIN wd_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 74.095 0.070 74.165 ;
+    END
+  END wd_in[9]
+  PIN wd_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 74.305 0.070 74.375 ;
+    END
+  END wd_in[10]
+  PIN wd_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 74.515 0.070 74.585 ;
+    END
+  END wd_in[11]
+  PIN wd_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 74.725 0.070 74.795 ;
+    END
+  END wd_in[12]
+  PIN wd_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 74.935 0.070 75.005 ;
+    END
+  END wd_in[13]
+  PIN wd_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 75.145 0.070 75.215 ;
+    END
+  END wd_in[14]
+  PIN wd_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 75.355 0.070 75.425 ;
+    END
+  END wd_in[15]
+  PIN wd_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 75.565 0.070 75.635 ;
+    END
+  END wd_in[16]
+  PIN wd_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 75.775 0.070 75.845 ;
+    END
+  END wd_in[17]
+  PIN wd_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 75.985 0.070 76.055 ;
+    END
+  END wd_in[18]
+  PIN wd_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 76.195 0.070 76.265 ;
+    END
+  END wd_in[19]
+  PIN wd_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 76.405 0.070 76.475 ;
+    END
+  END wd_in[20]
+  PIN wd_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 76.615 0.070 76.685 ;
+    END
+  END wd_in[21]
+  PIN wd_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 76.825 0.070 76.895 ;
+    END
+  END wd_in[22]
+  PIN wd_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 77.035 0.070 77.105 ;
+    END
+  END wd_in[23]
+  PIN wd_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 77.245 0.070 77.315 ;
+    END
+  END wd_in[24]
+  PIN wd_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 77.455 0.070 77.525 ;
+    END
+  END wd_in[25]
+  PIN wd_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 77.665 0.070 77.735 ;
+    END
+  END wd_in[26]
+  PIN wd_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 77.875 0.070 77.945 ;
+    END
+  END wd_in[27]
+  PIN wd_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 78.085 0.070 78.155 ;
+    END
+  END wd_in[28]
+  PIN wd_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 78.295 0.070 78.365 ;
+    END
+  END wd_in[29]
+  PIN wd_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 78.505 0.070 78.575 ;
+    END
+  END wd_in[30]
+  PIN wd_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 78.715 0.070 78.785 ;
+    END
+  END wd_in[31]
+  PIN wd_in[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 78.925 0.070 78.995 ;
+    END
+  END wd_in[32]
+  PIN wd_in[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 79.135 0.070 79.205 ;
+    END
+  END wd_in[33]
+  PIN wd_in[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 79.345 0.070 79.415 ;
+    END
+  END wd_in[34]
+  PIN wd_in[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 79.555 0.070 79.625 ;
+    END
+  END wd_in[35]
+  PIN wd_in[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 79.765 0.070 79.835 ;
+    END
+  END wd_in[36]
+  PIN wd_in[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 79.975 0.070 80.045 ;
+    END
+  END wd_in[37]
+  PIN wd_in[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 80.185 0.070 80.255 ;
+    END
+  END wd_in[38]
+  PIN wd_in[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 80.395 0.070 80.465 ;
+    END
+  END wd_in[39]
+  PIN wd_in[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 80.605 0.070 80.675 ;
+    END
+  END wd_in[40]
+  PIN wd_in[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 80.815 0.070 80.885 ;
+    END
+  END wd_in[41]
+  PIN wd_in[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 81.025 0.070 81.095 ;
+    END
+  END wd_in[42]
+  PIN wd_in[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 81.235 0.070 81.305 ;
+    END
+  END wd_in[43]
+  PIN wd_in[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 81.445 0.070 81.515 ;
+    END
+  END wd_in[44]
+  PIN wd_in[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 81.655 0.070 81.725 ;
+    END
+  END wd_in[45]
+  PIN wd_in[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 81.865 0.070 81.935 ;
+    END
+  END wd_in[46]
+  PIN wd_in[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 82.075 0.070 82.145 ;
+    END
+  END wd_in[47]
+  PIN wd_in[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 82.285 0.070 82.355 ;
+    END
+  END wd_in[48]
+  PIN wd_in[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 82.495 0.070 82.565 ;
+    END
+  END wd_in[49]
+  PIN wd_in[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 82.705 0.070 82.775 ;
+    END
+  END wd_in[50]
+  PIN wd_in[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 82.915 0.070 82.985 ;
+    END
+  END wd_in[51]
+  PIN wd_in[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 83.125 0.070 83.195 ;
+    END
+  END wd_in[52]
+  PIN wd_in[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 83.335 0.070 83.405 ;
+    END
+  END wd_in[53]
+  PIN wd_in[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 83.545 0.070 83.615 ;
+    END
+  END wd_in[54]
+  PIN wd_in[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 83.755 0.070 83.825 ;
+    END
+  END wd_in[55]
+  PIN wd_in[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 83.965 0.070 84.035 ;
+    END
+  END wd_in[56]
+  PIN wd_in[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 84.175 0.070 84.245 ;
+    END
+  END wd_in[57]
+  PIN wd_in[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 84.385 0.070 84.455 ;
+    END
+  END wd_in[58]
+  PIN wd_in[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 84.595 0.070 84.665 ;
+    END
+  END wd_in[59]
+  PIN wd_in[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 84.805 0.070 84.875 ;
+    END
+  END wd_in[60]
+  PIN wd_in[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 85.015 0.070 85.085 ;
+    END
+  END wd_in[61]
+  PIN wd_in[62]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 85.225 0.070 85.295 ;
+    END
+  END wd_in[62]
+  PIN wd_in[63]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 85.435 0.070 85.505 ;
+    END
+  END wd_in[63]
+  PIN wd_in[64]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 85.645 0.070 85.715 ;
+    END
+  END wd_in[64]
+  PIN wd_in[65]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 85.855 0.070 85.925 ;
+    END
+  END wd_in[65]
+  PIN wd_in[66]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 86.065 0.070 86.135 ;
+    END
+  END wd_in[66]
+  PIN wd_in[67]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 86.275 0.070 86.345 ;
+    END
+  END wd_in[67]
+  PIN wd_in[68]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 86.485 0.070 86.555 ;
+    END
+  END wd_in[68]
+  PIN wd_in[69]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 86.695 0.070 86.765 ;
+    END
+  END wd_in[69]
+  PIN wd_in[70]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 86.905 0.070 86.975 ;
+    END
+  END wd_in[70]
+  PIN wd_in[71]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 87.115 0.070 87.185 ;
+    END
+  END wd_in[71]
+  PIN wd_in[72]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 87.325 0.070 87.395 ;
+    END
+  END wd_in[72]
+  PIN wd_in[73]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 87.535 0.070 87.605 ;
+    END
+  END wd_in[73]
+  PIN wd_in[74]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 87.745 0.070 87.815 ;
+    END
+  END wd_in[74]
+  PIN wd_in[75]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 87.955 0.070 88.025 ;
+    END
+  END wd_in[75]
+  PIN wd_in[76]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 88.165 0.070 88.235 ;
+    END
+  END wd_in[76]
+  PIN wd_in[77]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 88.375 0.070 88.445 ;
+    END
+  END wd_in[77]
+  PIN wd_in[78]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 88.585 0.070 88.655 ;
+    END
+  END wd_in[78]
+  PIN wd_in[79]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 88.795 0.070 88.865 ;
+    END
+  END wd_in[79]
+  PIN wd_in[80]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 89.005 0.070 89.075 ;
+    END
+  END wd_in[80]
+  PIN wd_in[81]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 89.215 0.070 89.285 ;
+    END
+  END wd_in[81]
+  PIN wd_in[82]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 89.425 0.070 89.495 ;
+    END
+  END wd_in[82]
+  PIN wd_in[83]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 89.635 0.070 89.705 ;
+    END
+  END wd_in[83]
+  PIN wd_in[84]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 89.845 0.070 89.915 ;
+    END
+  END wd_in[84]
+  PIN wd_in[85]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 90.055 0.070 90.125 ;
+    END
+  END wd_in[85]
+  PIN wd_in[86]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 90.265 0.070 90.335 ;
+    END
+  END wd_in[86]
+  PIN wd_in[87]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 90.475 0.070 90.545 ;
+    END
+  END wd_in[87]
+  PIN wd_in[88]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 90.685 0.070 90.755 ;
+    END
+  END wd_in[88]
+  PIN wd_in[89]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 90.895 0.070 90.965 ;
+    END
+  END wd_in[89]
+  PIN wd_in[90]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 91.105 0.070 91.175 ;
+    END
+  END wd_in[90]
+  PIN wd_in[91]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 91.315 0.070 91.385 ;
+    END
+  END wd_in[91]
+  PIN wd_in[92]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 91.525 0.070 91.595 ;
+    END
+  END wd_in[92]
+  PIN wd_in[93]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 91.735 0.070 91.805 ;
+    END
+  END wd_in[93]
+  PIN wd_in[94]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 91.945 0.070 92.015 ;
+    END
+  END wd_in[94]
+  PIN wd_in[95]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 92.155 0.070 92.225 ;
+    END
+  END wd_in[95]
+  PIN wd_in[96]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 92.365 0.070 92.435 ;
+    END
+  END wd_in[96]
+  PIN wd_in[97]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 92.575 0.070 92.645 ;
+    END
+  END wd_in[97]
+  PIN wd_in[98]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 92.785 0.070 92.855 ;
+    END
+  END wd_in[98]
+  PIN wd_in[99]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 92.995 0.070 93.065 ;
+    END
+  END wd_in[99]
+  PIN wd_in[100]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 93.205 0.070 93.275 ;
+    END
+  END wd_in[100]
+  PIN wd_in[101]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 93.415 0.070 93.485 ;
+    END
+  END wd_in[101]
+  PIN wd_in[102]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 93.625 0.070 93.695 ;
+    END
+  END wd_in[102]
+  PIN wd_in[103]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 93.835 0.070 93.905 ;
+    END
+  END wd_in[103]
+  PIN wd_in[104]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 94.045 0.070 94.115 ;
+    END
+  END wd_in[104]
+  PIN wd_in[105]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 94.255 0.070 94.325 ;
+    END
+  END wd_in[105]
+  PIN wd_in[106]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 94.465 0.070 94.535 ;
+    END
+  END wd_in[106]
+  PIN wd_in[107]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 94.675 0.070 94.745 ;
+    END
+  END wd_in[107]
+  PIN wd_in[108]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 94.885 0.070 94.955 ;
+    END
+  END wd_in[108]
+  PIN wd_in[109]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 95.095 0.070 95.165 ;
+    END
+  END wd_in[109]
+  PIN wd_in[110]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 95.305 0.070 95.375 ;
+    END
+  END wd_in[110]
+  PIN wd_in[111]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 95.515 0.070 95.585 ;
+    END
+  END wd_in[111]
+  PIN wd_in[112]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 95.725 0.070 95.795 ;
+    END
+  END wd_in[112]
+  PIN wd_in[113]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 95.935 0.070 96.005 ;
+    END
+  END wd_in[113]
+  PIN wd_in[114]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 96.145 0.070 96.215 ;
+    END
+  END wd_in[114]
+  PIN wd_in[115]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 96.355 0.070 96.425 ;
+    END
+  END wd_in[115]
+  PIN wd_in[116]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 96.565 0.070 96.635 ;
+    END
+  END wd_in[116]
+  PIN wd_in[117]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 96.775 0.070 96.845 ;
+    END
+  END wd_in[117]
+  PIN wd_in[118]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 96.985 0.070 97.055 ;
+    END
+  END wd_in[118]
+  PIN wd_in[119]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 97.195 0.070 97.265 ;
+    END
+  END wd_in[119]
+  PIN wd_in[120]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 97.405 0.070 97.475 ;
+    END
+  END wd_in[120]
+  PIN wd_in[121]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 97.615 0.070 97.685 ;
+    END
+  END wd_in[121]
+  PIN wd_in[122]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 97.825 0.070 97.895 ;
+    END
+  END wd_in[122]
+  PIN wd_in[123]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 98.035 0.070 98.105 ;
+    END
+  END wd_in[123]
+  PIN addr_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 107.275 0.070 107.345 ;
+    END
+  END addr_in[0]
+  PIN addr_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 107.485 0.070 107.555 ;
+    END
+  END addr_in[1]
+  PIN addr_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 107.695 0.070 107.765 ;
+    END
+  END addr_in[2]
+  PIN addr_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 107.905 0.070 107.975 ;
+    END
+  END addr_in[3]
+  PIN addr_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 108.115 0.070 108.185 ;
+    END
+  END addr_in[4]
+  PIN addr_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 108.325 0.070 108.395 ;
+    END
+  END addr_in[5]
+  PIN we_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 117.565 0.070 117.635 ;
+    END
+  END we_in
+  PIN ce_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 117.775 0.070 117.845 ;
+    END
+  END ce_in
+  PIN clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 117.985 0.070 118.055 ;
+    END
+  END clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER metal4 ;
+      RECT 1.960 2.100 2.240 119.700 ;
+      RECT 5.320 2.100 5.600 119.700 ;
+      RECT 8.680 2.100 8.960 119.700 ;
+      RECT 12.040 2.100 12.320 119.700 ;
+      RECT 15.400 2.100 15.680 119.700 ;
+      RECT 18.760 2.100 19.040 119.700 ;
+      RECT 22.120 2.100 22.400 119.700 ;
+      RECT 25.480 2.100 25.760 119.700 ;
+      RECT 28.840 2.100 29.120 119.700 ;
+      RECT 32.200 2.100 32.480 119.700 ;
+      RECT 35.560 2.100 35.840 119.700 ;
+      RECT 38.920 2.100 39.200 119.700 ;
+      RECT 42.280 2.100 42.560 119.700 ;
+      RECT 45.640 2.100 45.920 119.700 ;
+      RECT 49.000 2.100 49.280 119.700 ;
+      RECT 52.360 2.100 52.640 119.700 ;
+      RECT 55.720 2.100 56.000 119.700 ;
+      RECT 59.080 2.100 59.360 119.700 ;
+      RECT 62.440 2.100 62.720 119.700 ;
+      RECT 65.800 2.100 66.080 119.700 ;
+      RECT 69.160 2.100 69.440 119.700 ;
+      RECT 72.520 2.100 72.800 119.700 ;
+      RECT 75.880 2.100 76.160 119.700 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER metal4 ;
+      RECT 3.640 2.100 3.920 119.700 ;
+      RECT 7.000 2.100 7.280 119.700 ;
+      RECT 10.360 2.100 10.640 119.700 ;
+      RECT 13.720 2.100 14.000 119.700 ;
+      RECT 17.080 2.100 17.360 119.700 ;
+      RECT 20.440 2.100 20.720 119.700 ;
+      RECT 23.800 2.100 24.080 119.700 ;
+      RECT 27.160 2.100 27.440 119.700 ;
+      RECT 30.520 2.100 30.800 119.700 ;
+      RECT 33.880 2.100 34.160 119.700 ;
+      RECT 37.240 2.100 37.520 119.700 ;
+      RECT 40.600 2.100 40.880 119.700 ;
+      RECT 43.960 2.100 44.240 119.700 ;
+      RECT 47.320 2.100 47.600 119.700 ;
+      RECT 50.680 2.100 50.960 119.700 ;
+      RECT 54.040 2.100 54.320 119.700 ;
+      RECT 57.400 2.100 57.680 119.700 ;
+      RECT 60.760 2.100 61.040 119.700 ;
+      RECT 64.120 2.100 64.400 119.700 ;
+      RECT 67.480 2.100 67.760 119.700 ;
+      RECT 70.840 2.100 71.120 119.700 ;
+      RECT 74.200 2.100 74.480 119.700 ;
+      RECT 77.560 2.100 77.840 119.700 ;
+    END
+  END VDD
+  OBS
+    LAYER metal1 ;
+    RECT 0 0 80.560 121.800 ;
+    LAYER metal2 ;
+    RECT 0 0 80.560 121.800 ;
+    LAYER metal3 ;
+    RECT 0.070 0 80.560 121.800 ;
+    RECT 0 0.000 0.070 2.065 ;
+    RECT 0 2.135 0.070 2.275 ;
+    RECT 0 2.345 0.070 2.485 ;
+    RECT 0 2.555 0.070 2.695 ;
+    RECT 0 2.765 0.070 2.905 ;
+    RECT 0 2.975 0.070 3.115 ;
+    RECT 0 3.185 0.070 3.325 ;
+    RECT 0 3.395 0.070 3.535 ;
+    RECT 0 3.605 0.070 3.745 ;
+    RECT 0 3.815 0.070 3.955 ;
+    RECT 0 4.025 0.070 4.165 ;
+    RECT 0 4.235 0.070 4.375 ;
+    RECT 0 4.445 0.070 4.585 ;
+    RECT 0 4.655 0.070 4.795 ;
+    RECT 0 4.865 0.070 5.005 ;
+    RECT 0 5.075 0.070 5.215 ;
+    RECT 0 5.285 0.070 5.425 ;
+    RECT 0 5.495 0.070 5.635 ;
+    RECT 0 5.705 0.070 5.845 ;
+    RECT 0 5.915 0.070 6.055 ;
+    RECT 0 6.125 0.070 6.265 ;
+    RECT 0 6.335 0.070 6.475 ;
+    RECT 0 6.545 0.070 6.685 ;
+    RECT 0 6.755 0.070 6.895 ;
+    RECT 0 6.965 0.070 7.105 ;
+    RECT 0 7.175 0.070 7.315 ;
+    RECT 0 7.385 0.070 7.525 ;
+    RECT 0 7.595 0.070 7.735 ;
+    RECT 0 7.805 0.070 7.945 ;
+    RECT 0 8.015 0.070 8.155 ;
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+    RECT 0 94.115 0.070 94.255 ;
+    RECT 0 94.325 0.070 94.465 ;
+    RECT 0 94.535 0.070 94.675 ;
+    RECT 0 94.745 0.070 94.885 ;
+    RECT 0 94.955 0.070 95.095 ;
+    RECT 0 95.165 0.070 95.305 ;
+    RECT 0 95.375 0.070 95.515 ;
+    RECT 0 95.585 0.070 95.725 ;
+    RECT 0 95.795 0.070 95.935 ;
+    RECT 0 96.005 0.070 96.145 ;
+    RECT 0 96.215 0.070 96.355 ;
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+    RECT 0 96.635 0.070 96.775 ;
+    RECT 0 96.845 0.070 96.985 ;
+    RECT 0 97.055 0.070 97.195 ;
+    RECT 0 97.265 0.070 97.405 ;
+    RECT 0 97.475 0.070 97.615 ;
+    RECT 0 97.685 0.070 97.825 ;
+    RECT 0 97.895 0.070 98.035 ;
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+    RECT 0 117.635 0.070 117.775 ;
+    RECT 0 117.845 0.070 117.985 ;
+    RECT 0 118.055 0.070 121.800 ;
+    LAYER metal4 ;
+    RECT 0 0 80.560 2.100 ;
+    RECT 0 119.700 80.560 121.800 ;
+    RECT 0.000 2.100 1.960 119.700 ;
+    RECT 2.240 2.100 3.640 119.700 ;
+    RECT 3.920 2.100 5.320 119.700 ;
+    RECT 5.600 2.100 7.000 119.700 ;
+    RECT 7.280 2.100 8.680 119.700 ;
+    RECT 8.960 2.100 10.360 119.700 ;
+    RECT 10.640 2.100 12.040 119.700 ;
+    RECT 12.320 2.100 13.720 119.700 ;
+    RECT 14.000 2.100 15.400 119.700 ;
+    RECT 15.680 2.100 17.080 119.700 ;
+    RECT 17.360 2.100 18.760 119.700 ;
+    RECT 19.040 2.100 20.440 119.700 ;
+    RECT 20.720 2.100 22.120 119.700 ;
+    RECT 22.400 2.100 23.800 119.700 ;
+    RECT 24.080 2.100 25.480 119.700 ;
+    RECT 25.760 2.100 27.160 119.700 ;
+    RECT 27.440 2.100 28.840 119.700 ;
+    RECT 29.120 2.100 30.520 119.700 ;
+    RECT 30.800 2.100 32.200 119.700 ;
+    RECT 32.480 2.100 33.880 119.700 ;
+    RECT 34.160 2.100 35.560 119.700 ;
+    RECT 35.840 2.100 37.240 119.700 ;
+    RECT 37.520 2.100 38.920 119.700 ;
+    RECT 39.200 2.100 40.600 119.700 ;
+    RECT 40.880 2.100 42.280 119.700 ;
+    RECT 42.560 2.100 43.960 119.700 ;
+    RECT 44.240 2.100 45.640 119.700 ;
+    RECT 45.920 2.100 47.320 119.700 ;
+    RECT 47.600 2.100 49.000 119.700 ;
+    RECT 49.280 2.100 50.680 119.700 ;
+    RECT 50.960 2.100 52.360 119.700 ;
+    RECT 52.640 2.100 54.040 119.700 ;
+    RECT 54.320 2.100 55.720 119.700 ;
+    RECT 56.000 2.100 57.400 119.700 ;
+    RECT 57.680 2.100 59.080 119.700 ;
+    RECT 59.360 2.100 60.760 119.700 ;
+    RECT 61.040 2.100 62.440 119.700 ;
+    RECT 62.720 2.100 64.120 119.700 ;
+    RECT 64.400 2.100 65.800 119.700 ;
+    RECT 66.080 2.100 67.480 119.700 ;
+    RECT 67.760 2.100 69.160 119.700 ;
+    RECT 69.440 2.100 70.840 119.700 ;
+    RECT 71.120 2.100 72.520 119.700 ;
+    RECT 72.800 2.100 74.200 119.700 ;
+    RECT 74.480 2.100 75.880 119.700 ;
+    RECT 76.160 2.100 77.560 119.700 ;
+    RECT 77.840 2.100 80.560 119.700 ;
+    LAYER OVERLAP ;
+    RECT 0 0 80.560 121.800 ;
+  END
+END fakeram45_64x124
+
+END LIBRARY

Enablements/NanGate45/lef/fakeram45_64x62.lef

+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+MACRO fakeram45_64x62
+  FOREIGN fakeram45_64x62 0 0 ;
+  SYMMETRY X Y R90 ;
+  SIZE 56.050 BY 102.200 ;
+  CLASS BLOCK ;
+  PIN w_mask_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.065 0.070 2.135 ;
+    END
+  END w_mask_in[0]
+  PIN w_mask_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.485 0.070 2.555 ;
+    END
+  END w_mask_in[1]
+  PIN w_mask_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 2.905 0.070 2.975 ;
+    END
+  END w_mask_in[2]
+  PIN w_mask_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.325 0.070 3.395 ;
+    END
+  END w_mask_in[3]
+  PIN w_mask_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 3.745 0.070 3.815 ;
+    END
+  END w_mask_in[4]
+  PIN w_mask_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 4.165 0.070 4.235 ;
+    END
+  END w_mask_in[5]
+  PIN w_mask_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 4.585 0.070 4.655 ;
+    END
+  END w_mask_in[6]
+  PIN w_mask_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.005 0.070 5.075 ;
+    END
+  END w_mask_in[7]
+  PIN w_mask_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.425 0.070 5.495 ;
+    END
+  END w_mask_in[8]
+  PIN w_mask_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 5.845 0.070 5.915 ;
+    END
+  END w_mask_in[9]
+  PIN w_mask_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.265 0.070 6.335 ;
+    END
+  END w_mask_in[10]
+  PIN w_mask_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 6.685 0.070 6.755 ;
+    END
+  END w_mask_in[11]
+  PIN w_mask_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.105 0.070 7.175 ;
+    END
+  END w_mask_in[12]
+  PIN w_mask_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.525 0.070 7.595 ;
+    END
+  END w_mask_in[13]
+  PIN w_mask_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 7.945 0.070 8.015 ;
+    END
+  END w_mask_in[14]
+  PIN w_mask_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.365 0.070 8.435 ;
+    END
+  END w_mask_in[15]
+  PIN w_mask_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 8.785 0.070 8.855 ;
+    END
+  END w_mask_in[16]
+  PIN w_mask_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 9.205 0.070 9.275 ;
+    END
+  END w_mask_in[17]
+  PIN w_mask_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 9.625 0.070 9.695 ;
+    END
+  END w_mask_in[18]
+  PIN w_mask_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.045 0.070 10.115 ;
+    END
+  END w_mask_in[19]
+  PIN w_mask_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.465 0.070 10.535 ;
+    END
+  END w_mask_in[20]
+  PIN w_mask_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 10.885 0.070 10.955 ;
+    END
+  END w_mask_in[21]
+  PIN w_mask_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.305 0.070 11.375 ;
+    END
+  END w_mask_in[22]
+  PIN w_mask_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 11.725 0.070 11.795 ;
+    END
+  END w_mask_in[23]
+  PIN w_mask_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.145 0.070 12.215 ;
+    END
+  END w_mask_in[24]
+  PIN w_mask_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.565 0.070 12.635 ;
+    END
+  END w_mask_in[25]
+  PIN w_mask_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 12.985 0.070 13.055 ;
+    END
+  END w_mask_in[26]
+  PIN w_mask_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 13.405 0.070 13.475 ;
+    END
+  END w_mask_in[27]
+  PIN w_mask_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 13.825 0.070 13.895 ;
+    END
+  END w_mask_in[28]
+  PIN w_mask_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.245 0.070 14.315 ;
+    END
+  END w_mask_in[29]
+  PIN w_mask_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 14.665 0.070 14.735 ;
+    END
+  END w_mask_in[30]
+  PIN w_mask_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.085 0.070 15.155 ;
+    END
+  END w_mask_in[31]
+  PIN w_mask_in[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.505 0.070 15.575 ;
+    END
+  END w_mask_in[32]
+  PIN w_mask_in[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 15.925 0.070 15.995 ;
+    END
+  END w_mask_in[33]
+  PIN w_mask_in[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.345 0.070 16.415 ;
+    END
+  END w_mask_in[34]
+  PIN w_mask_in[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 16.765 0.070 16.835 ;
+    END
+  END w_mask_in[35]
+  PIN w_mask_in[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 17.185 0.070 17.255 ;
+    END
+  END w_mask_in[36]
+  PIN w_mask_in[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 17.605 0.070 17.675 ;
+    END
+  END w_mask_in[37]
+  PIN w_mask_in[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 18.025 0.070 18.095 ;
+    END
+  END w_mask_in[38]
+  PIN w_mask_in[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 18.445 0.070 18.515 ;
+    END
+  END w_mask_in[39]
+  PIN w_mask_in[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 18.865 0.070 18.935 ;
+    END
+  END w_mask_in[40]
+  PIN w_mask_in[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.285 0.070 19.355 ;
+    END
+  END w_mask_in[41]
+  PIN w_mask_in[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 19.705 0.070 19.775 ;
+    END
+  END w_mask_in[42]
+  PIN w_mask_in[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.125 0.070 20.195 ;
+    END
+  END w_mask_in[43]
+  PIN w_mask_in[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.545 0.070 20.615 ;
+    END
+  END w_mask_in[44]
+  PIN w_mask_in[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 20.965 0.070 21.035 ;
+    END
+  END w_mask_in[45]
+  PIN w_mask_in[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 21.385 0.070 21.455 ;
+    END
+  END w_mask_in[46]
+  PIN w_mask_in[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 21.805 0.070 21.875 ;
+    END
+  END w_mask_in[47]
+  PIN w_mask_in[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.225 0.070 22.295 ;
+    END
+  END w_mask_in[48]
+  PIN w_mask_in[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 22.645 0.070 22.715 ;
+    END
+  END w_mask_in[49]
+  PIN w_mask_in[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.065 0.070 23.135 ;
+    END
+  END w_mask_in[50]
+  PIN w_mask_in[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.485 0.070 23.555 ;
+    END
+  END w_mask_in[51]
+  PIN w_mask_in[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 23.905 0.070 23.975 ;
+    END
+  END w_mask_in[52]
+  PIN w_mask_in[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.325 0.070 24.395 ;
+    END
+  END w_mask_in[53]
+  PIN w_mask_in[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 24.745 0.070 24.815 ;
+    END
+  END w_mask_in[54]
+  PIN w_mask_in[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 25.165 0.070 25.235 ;
+    END
+  END w_mask_in[55]
+  PIN w_mask_in[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 25.585 0.070 25.655 ;
+    END
+  END w_mask_in[56]
+  PIN w_mask_in[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 26.005 0.070 26.075 ;
+    END
+  END w_mask_in[57]
+  PIN w_mask_in[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 26.425 0.070 26.495 ;
+    END
+  END w_mask_in[58]
+  PIN w_mask_in[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 26.845 0.070 26.915 ;
+    END
+  END w_mask_in[59]
+  PIN w_mask_in[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 27.265 0.070 27.335 ;
+    END
+  END w_mask_in[60]
+  PIN w_mask_in[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 27.685 0.070 27.755 ;
+    END
+  END w_mask_in[61]
+  PIN rd_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 31.675 0.070 31.745 ;
+    END
+  END rd_out[0]
+  PIN rd_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 32.095 0.070 32.165 ;
+    END
+  END rd_out[1]
+  PIN rd_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 32.515 0.070 32.585 ;
+    END
+  END rd_out[2]
+  PIN rd_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 32.935 0.070 33.005 ;
+    END
+  END rd_out[3]
+  PIN rd_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 33.355 0.070 33.425 ;
+    END
+  END rd_out[4]
+  PIN rd_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 33.775 0.070 33.845 ;
+    END
+  END rd_out[5]
+  PIN rd_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 34.195 0.070 34.265 ;
+    END
+  END rd_out[6]
+  PIN rd_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 34.615 0.070 34.685 ;
+    END
+  END rd_out[7]
+  PIN rd_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 35.035 0.070 35.105 ;
+    END
+  END rd_out[8]
+  PIN rd_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 35.455 0.070 35.525 ;
+    END
+  END rd_out[9]
+  PIN rd_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 35.875 0.070 35.945 ;
+    END
+  END rd_out[10]
+  PIN rd_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 36.295 0.070 36.365 ;
+    END
+  END rd_out[11]
+  PIN rd_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 36.715 0.070 36.785 ;
+    END
+  END rd_out[12]
+  PIN rd_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 37.135 0.070 37.205 ;
+    END
+  END rd_out[13]
+  PIN rd_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 37.555 0.070 37.625 ;
+    END
+  END rd_out[14]
+  PIN rd_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 37.975 0.070 38.045 ;
+    END
+  END rd_out[15]
+  PIN rd_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 38.395 0.070 38.465 ;
+    END
+  END rd_out[16]
+  PIN rd_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 38.815 0.070 38.885 ;
+    END
+  END rd_out[17]
+  PIN rd_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 39.235 0.070 39.305 ;
+    END
+  END rd_out[18]
+  PIN rd_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 39.655 0.070 39.725 ;
+    END
+  END rd_out[19]
+  PIN rd_out[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 40.075 0.070 40.145 ;
+    END
+  END rd_out[20]
+  PIN rd_out[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 40.495 0.070 40.565 ;
+    END
+  END rd_out[21]
+  PIN rd_out[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 40.915 0.070 40.985 ;
+    END
+  END rd_out[22]
+  PIN rd_out[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 41.335 0.070 41.405 ;
+    END
+  END rd_out[23]
+  PIN rd_out[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 41.755 0.070 41.825 ;
+    END
+  END rd_out[24]
+  PIN rd_out[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 42.175 0.070 42.245 ;
+    END
+  END rd_out[25]
+  PIN rd_out[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 42.595 0.070 42.665 ;
+    END
+  END rd_out[26]
+  PIN rd_out[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 43.015 0.070 43.085 ;
+    END
+  END rd_out[27]
+  PIN rd_out[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 43.435 0.070 43.505 ;
+    END
+  END rd_out[28]
+  PIN rd_out[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 43.855 0.070 43.925 ;
+    END
+  END rd_out[29]
+  PIN rd_out[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 44.275 0.070 44.345 ;
+    END
+  END rd_out[30]
+  PIN rd_out[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 44.695 0.070 44.765 ;
+    END
+  END rd_out[31]
+  PIN rd_out[32]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 45.115 0.070 45.185 ;
+    END
+  END rd_out[32]
+  PIN rd_out[33]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 45.535 0.070 45.605 ;
+    END
+  END rd_out[33]
+  PIN rd_out[34]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 45.955 0.070 46.025 ;
+    END
+  END rd_out[34]
+  PIN rd_out[35]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 46.375 0.070 46.445 ;
+    END
+  END rd_out[35]
+  PIN rd_out[36]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 46.795 0.070 46.865 ;
+    END
+  END rd_out[36]
+  PIN rd_out[37]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 47.215 0.070 47.285 ;
+    END
+  END rd_out[37]
+  PIN rd_out[38]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 47.635 0.070 47.705 ;
+    END
+  END rd_out[38]
+  PIN rd_out[39]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 48.055 0.070 48.125 ;
+    END
+  END rd_out[39]
+  PIN rd_out[40]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 48.475 0.070 48.545 ;
+    END
+  END rd_out[40]
+  PIN rd_out[41]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 48.895 0.070 48.965 ;
+    END
+  END rd_out[41]
+  PIN rd_out[42]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 49.315 0.070 49.385 ;
+    END
+  END rd_out[42]
+  PIN rd_out[43]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 49.735 0.070 49.805 ;
+    END
+  END rd_out[43]
+  PIN rd_out[44]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 50.155 0.070 50.225 ;
+    END
+  END rd_out[44]
+  PIN rd_out[45]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 50.575 0.070 50.645 ;
+    END
+  END rd_out[45]
+  PIN rd_out[46]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 50.995 0.070 51.065 ;
+    END
+  END rd_out[46]
+  PIN rd_out[47]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 51.415 0.070 51.485 ;
+    END
+  END rd_out[47]
+  PIN rd_out[48]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 51.835 0.070 51.905 ;
+    END
+  END rd_out[48]
+  PIN rd_out[49]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 52.255 0.070 52.325 ;
+    END
+  END rd_out[49]
+  PIN rd_out[50]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 52.675 0.070 52.745 ;
+    END
+  END rd_out[50]
+  PIN rd_out[51]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 53.095 0.070 53.165 ;
+    END
+  END rd_out[51]
+  PIN rd_out[52]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 53.515 0.070 53.585 ;
+    END
+  END rd_out[52]
+  PIN rd_out[53]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 53.935 0.070 54.005 ;
+    END
+  END rd_out[53]
+  PIN rd_out[54]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 54.355 0.070 54.425 ;
+    END
+  END rd_out[54]
+  PIN rd_out[55]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 54.775 0.070 54.845 ;
+    END
+  END rd_out[55]
+  PIN rd_out[56]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 55.195 0.070 55.265 ;
+    END
+  END rd_out[56]
+  PIN rd_out[57]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 55.615 0.070 55.685 ;
+    END
+  END rd_out[57]
+  PIN rd_out[58]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 56.035 0.070 56.105 ;
+    END
+  END rd_out[58]
+  PIN rd_out[59]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 56.455 0.070 56.525 ;
+    END
+  END rd_out[59]
+  PIN rd_out[60]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 56.875 0.070 56.945 ;
+    END
+  END rd_out[60]
+  PIN rd_out[61]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 57.295 0.070 57.365 ;
+    END
+  END rd_out[61]
+  PIN wd_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 61.285 0.070 61.355 ;
+    END
+  END wd_in[0]
+  PIN wd_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 61.705 0.070 61.775 ;
+    END
+  END wd_in[1]
+  PIN wd_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 62.125 0.070 62.195 ;
+    END
+  END wd_in[2]
+  PIN wd_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 62.545 0.070 62.615 ;
+    END
+  END wd_in[3]
+  PIN wd_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 62.965 0.070 63.035 ;
+    END
+  END wd_in[4]
+  PIN wd_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 63.385 0.070 63.455 ;
+    END
+  END wd_in[5]
+  PIN wd_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 63.805 0.070 63.875 ;
+    END
+  END wd_in[6]
+  PIN wd_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 64.225 0.070 64.295 ;
+    END
+  END wd_in[7]
+  PIN wd_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 64.645 0.070 64.715 ;
+    END
+  END wd_in[8]
+  PIN wd_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 65.065 0.070 65.135 ;
+    END
+  END wd_in[9]
+  PIN wd_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 65.485 0.070 65.555 ;
+    END
+  END wd_in[10]
+  PIN wd_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 65.905 0.070 65.975 ;
+    END
+  END wd_in[11]
+  PIN wd_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 66.325 0.070 66.395 ;
+    END
+  END wd_in[12]
+  PIN wd_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 66.745 0.070 66.815 ;
+    END
+  END wd_in[13]
+  PIN wd_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 67.165 0.070 67.235 ;
+    END
+  END wd_in[14]
+  PIN wd_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 67.585 0.070 67.655 ;
+    END
+  END wd_in[15]
+  PIN wd_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 68.005 0.070 68.075 ;
+    END
+  END wd_in[16]
+  PIN wd_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 68.425 0.070 68.495 ;
+    END
+  END wd_in[17]
+  PIN wd_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 68.845 0.070 68.915 ;
+    END
+  END wd_in[18]
+  PIN wd_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 69.265 0.070 69.335 ;
+    END
+  END wd_in[19]
+  PIN wd_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 69.685 0.070 69.755 ;
+    END
+  END wd_in[20]
+  PIN wd_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 70.105 0.070 70.175 ;
+    END
+  END wd_in[21]
+  PIN wd_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 70.525 0.070 70.595 ;
+    END
+  END wd_in[22]
+  PIN wd_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 70.945 0.070 71.015 ;
+    END
+  END wd_in[23]
+  PIN wd_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 71.365 0.070 71.435 ;
+    END
+  END wd_in[24]
+  PIN wd_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 71.785 0.070 71.855 ;
+    END
+  END wd_in[25]
+  PIN wd_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 72.205 0.070 72.275 ;
+    END
+  END wd_in[26]
+  PIN wd_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 72.625 0.070 72.695 ;
+    END
+  END wd_in[27]
+  PIN wd_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 73.045 0.070 73.115 ;
+    END
+  END wd_in[28]
+  PIN wd_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 73.465 0.070 73.535 ;
+    END
+  END wd_in[29]
+  PIN wd_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 73.885 0.070 73.955 ;
+    END
+  END wd_in[30]
+  PIN wd_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 74.305 0.070 74.375 ;
+    END
+  END wd_in[31]
+  PIN wd_in[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 74.725 0.070 74.795 ;
+    END
+  END wd_in[32]
+  PIN wd_in[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 75.145 0.070 75.215 ;
+    END
+  END wd_in[33]
+  PIN wd_in[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 75.565 0.070 75.635 ;
+    END
+  END wd_in[34]
+  PIN wd_in[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 75.985 0.070 76.055 ;
+    END
+  END wd_in[35]
+  PIN wd_in[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 76.405 0.070 76.475 ;
+    END
+  END wd_in[36]
+  PIN wd_in[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 76.825 0.070 76.895 ;
+    END
+  END wd_in[37]
+  PIN wd_in[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 77.245 0.070 77.315 ;
+    END
+  END wd_in[38]
+  PIN wd_in[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 77.665 0.070 77.735 ;
+    END
+  END wd_in[39]
+  PIN wd_in[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 78.085 0.070 78.155 ;
+    END
+  END wd_in[40]
+  PIN wd_in[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 78.505 0.070 78.575 ;
+    END
+  END wd_in[41]
+  PIN wd_in[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 78.925 0.070 78.995 ;
+    END
+  END wd_in[42]
+  PIN wd_in[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 79.345 0.070 79.415 ;
+    END
+  END wd_in[43]
+  PIN wd_in[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 79.765 0.070 79.835 ;
+    END
+  END wd_in[44]
+  PIN wd_in[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 80.185 0.070 80.255 ;
+    END
+  END wd_in[45]
+  PIN wd_in[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 80.605 0.070 80.675 ;
+    END
+  END wd_in[46]
+  PIN wd_in[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 81.025 0.070 81.095 ;
+    END
+  END wd_in[47]
+  PIN wd_in[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 81.445 0.070 81.515 ;
+    END
+  END wd_in[48]
+  PIN wd_in[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 81.865 0.070 81.935 ;
+    END
+  END wd_in[49]
+  PIN wd_in[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 82.285 0.070 82.355 ;
+    END
+  END wd_in[50]
+  PIN wd_in[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 82.705 0.070 82.775 ;
+    END
+  END wd_in[51]
+  PIN wd_in[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 83.125 0.070 83.195 ;
+    END
+  END wd_in[52]
+  PIN wd_in[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 83.545 0.070 83.615 ;
+    END
+  END wd_in[53]
+  PIN wd_in[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 83.965 0.070 84.035 ;
+    END
+  END wd_in[54]
+  PIN wd_in[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 84.385 0.070 84.455 ;
+    END
+  END wd_in[55]
+  PIN wd_in[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 84.805 0.070 84.875 ;
+    END
+  END wd_in[56]
+  PIN wd_in[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 85.225 0.070 85.295 ;
+    END
+  END wd_in[57]
+  PIN wd_in[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 85.645 0.070 85.715 ;
+    END
+  END wd_in[58]
+  PIN wd_in[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 86.065 0.070 86.135 ;
+    END
+  END wd_in[59]
+  PIN wd_in[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 86.485 0.070 86.555 ;
+    END
+  END wd_in[60]
+  PIN wd_in[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 86.905 0.070 86.975 ;
+    END
+  END wd_in[61]
+  PIN addr_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 90.895 0.070 90.965 ;
+    END
+  END addr_in[0]
+  PIN addr_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 91.315 0.070 91.385 ;
+    END
+  END addr_in[1]
+  PIN addr_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 91.735 0.070 91.805 ;
+    END
+  END addr_in[2]
+  PIN addr_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 92.155 0.070 92.225 ;
+    END
+  END addr_in[3]
+  PIN addr_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 92.575 0.070 92.645 ;
+    END
+  END addr_in[4]
+  PIN addr_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 92.995 0.070 93.065 ;
+    END
+  END addr_in[5]
+  PIN we_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 96.985 0.070 97.055 ;
+    END
+  END we_in
+  PIN ce_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 97.405 0.070 97.475 ;
+    END
+  END ce_in
+  PIN clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0.000 97.825 0.070 97.895 ;
+    END
+  END clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER metal4 ;
+      RECT 1.960 2.100 2.240 100.100 ;
+      RECT 5.320 2.100 5.600 100.100 ;
+      RECT 8.680 2.100 8.960 100.100 ;
+      RECT 12.040 2.100 12.320 100.100 ;
+      RECT 15.400 2.100 15.680 100.100 ;
+      RECT 18.760 2.100 19.040 100.100 ;
+      RECT 22.120 2.100 22.400 100.100 ;
+      RECT 25.480 2.100 25.760 100.100 ;
+      RECT 28.840 2.100 29.120 100.100 ;
+      RECT 32.200 2.100 32.480 100.100 ;
+      RECT 35.560 2.100 35.840 100.100 ;
+      RECT 38.920 2.100 39.200 100.100 ;
+      RECT 42.280 2.100 42.560 100.100 ;
+      RECT 45.640 2.100 45.920 100.100 ;
+      RECT 49.000 2.100 49.280 100.100 ;
+      RECT 52.360 2.100 52.640 100.100 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER metal4 ;
+      RECT 3.640 2.100 3.920 100.100 ;
+      RECT 7.000 2.100 7.280 100.100 ;
+      RECT 10.360 2.100 10.640 100.100 ;
+      RECT 13.720 2.100 14.000 100.100 ;
+      RECT 17.080 2.100 17.360 100.100 ;
+      RECT 20.440 2.100 20.720 100.100 ;
+      RECT 23.800 2.100 24.080 100.100 ;
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+      RECT 40.600 2.100 40.880 100.100 ;
+      RECT 43.960 2.100 44.240 100.100 ;
+      RECT 47.320 2.100 47.600 100.100 ;
+      RECT 50.680 2.100 50.960 100.100 ;
+    END
+  END VDD
+  OBS
+    LAYER metal1 ;
+    RECT 0 0 56.050 102.200 ;
+    LAYER metal2 ;
+    RECT 0 0 56.050 102.200 ;
+    LAYER metal3 ;
+    RECT 0.070 0 56.050 102.200 ;
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+    LAYER metal4 ;
+    RECT 0 0 56.050 2.100 ;
+    RECT 0 100.100 56.050 102.200 ;
+    RECT 0.000 2.100 1.960 100.100 ;
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+    RECT 20.720 2.100 22.120 100.100 ;
+    RECT 22.400 2.100 23.800 100.100 ;
+    RECT 24.080 2.100 25.480 100.100 ;
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+    RECT 27.440 2.100 28.840 100.100 ;
+    RECT 29.120 2.100 30.520 100.100 ;
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+    RECT 32.480 2.100 33.880 100.100 ;
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+    RECT 42.560 2.100 43.960 100.100 ;
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+    RECT 49.280 2.100 50.680 100.100 ;
+    RECT 50.960 2.100 52.360 100.100 ;
+    RECT 52.640 2.100 56.050 100.100 ;
+    LAYER OVERLAP ;
+    RECT 0 0 56.050 102.200 ;
+  END
+END fakeram45_64x62
+
+END LIBRARY

Enablements/NanGate45/lib/fakeram45_128x116.lib

+library(fakeram45_128x116) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2022-09-13 21:51:08Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 1.1;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 1.1;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(fakeram45_128x116_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(fakeram45_128x116_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(fakeram45_128x116_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(fakeram45_128x116_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(fakeram45_128x116_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (fakeram45_128x116_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 116;
+        bit_from : 115;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (fakeram45_128x116_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 7;
+        bit_from : 6;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(fakeram45_128x116) {
+    area : 14233.128;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 7;
+        word_width : 116;
+    }
+    pin(clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.248 ;
+        internal_power(){
+            rise_power(fakeram45_128x116_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("6.316, 6.316")
+            }
+            fall_power(fakeram45_128x116_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("6.316, 6.316")
+            }
+        }
+    }
+
+    bus(rd_out)   {
+        bus_type : fakeram45_128x116_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : addr_in;
+        }
+        timing() {
+            related_pin : "clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(fakeram45_128x116_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.285, 0.285", \
+                  "0.285, 0.285" \
+                )
+            }
+            cell_fall(fakeram45_128x116_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.285, 0.285", \
+                  "0.285, 0.285" \
+                )
+            }
+            rise_transition(fakeram45_128x116_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(fakeram45_128x116_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(we_in){
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_128x116_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.063, 0.063")
+            }
+            fall_power(fakeram45_128x116_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.063, 0.063")
+            }
+        }
+    }
+    pin(ce_in){
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_128x116_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.063, 0.063")
+            }
+            fall_power(fakeram45_128x116_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.063, 0.063")
+            }
+        }
+    }
+    bus(addr_in)   {
+        bus_type : fakeram45_128x116_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_128x116_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.063, 0.063")
+            }
+            fall_power(fakeram45_128x116_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.063, 0.063")
+            }
+        }
+    }
+    bus(wd_in)   {
+        bus_type : fakeram45_128x116_DATA;
+        memory_write() {
+            address : addr_in;
+            clocked_on : "clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (we_in) )";
+            rise_power(fakeram45_128x116_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.063, 0.063")
+            }
+            fall_power(fakeram45_128x116_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.063, 0.063")
+            }
+        }
+        internal_power(){
+            when : "(we_in)";
+            rise_power(fakeram45_128x116_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.063, 0.063")
+            }
+            fall_power(fakeram45_128x116_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.063, 0.063")
+            }
+        }
+    }
+    bus(w_mask_in)   {
+        bus_type : fakeram45_128x116_DATA;
+        memory_write() {
+            address : addr_in;
+            clocked_on : "clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_128x116_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (we_in) )";
+            rise_power(fakeram45_128x116_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.063, 0.063")
+            }
+            fall_power(fakeram45_128x116_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.063, 0.063")
+            }
+        }
+        internal_power(){
+            when : "(we_in)";
+            rise_power(fakeram45_128x116_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.063, 0.063")
+            }
+            fall_power(fakeram45_128x116_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.063, 0.063")
+            }
+        }
+    }
+    cell_leakage_power : 650.179;
+}
+
+}

Enablements/NanGate45/lib/fakeram45_256x48.lib

+library(fakeram45_256x48) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2022-09-13 21:51:06Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 1.1;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 1.1;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(fakeram45_256x48_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(fakeram45_256x48_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(fakeram45_256x48_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(fakeram45_256x48_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(fakeram45_256x48_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (fakeram45_256x48_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 48;
+        bit_from : 47;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (fakeram45_256x48_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(fakeram45_256x48) {
+    area : 13267.016;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 8;
+        word_width : 48;
+    }
+    pin(clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.230 ;
+        internal_power(){
+            rise_power(fakeram45_256x48_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("4.589, 4.589")
+            }
+            fall_power(fakeram45_256x48_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("4.589, 4.589")
+            }
+        }
+    }
+
+    bus(rd_out)   {
+        bus_type : fakeram45_256x48_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : addr_in;
+        }
+        timing() {
+            related_pin : "clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(fakeram45_256x48_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.270, 0.270", \
+                  "0.270, 0.270" \
+                )
+            }
+            cell_fall(fakeram45_256x48_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.270, 0.270", \
+                  "0.270, 0.270" \
+                )
+            }
+            rise_transition(fakeram45_256x48_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(fakeram45_256x48_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(we_in){
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_256x48_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.046, 0.046")
+            }
+            fall_power(fakeram45_256x48_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.046, 0.046")
+            }
+        }
+    }
+    pin(ce_in){
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_256x48_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.046, 0.046")
+            }
+            fall_power(fakeram45_256x48_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.046, 0.046")
+            }
+        }
+    }
+    bus(addr_in)   {
+        bus_type : fakeram45_256x48_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_256x48_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.046, 0.046")
+            }
+            fall_power(fakeram45_256x48_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.046, 0.046")
+            }
+        }
+    }
+    bus(wd_in)   {
+        bus_type : fakeram45_256x48_DATA;
+        memory_write() {
+            address : addr_in;
+            clocked_on : "clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (we_in) )";
+            rise_power(fakeram45_256x48_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.046, 0.046")
+            }
+            fall_power(fakeram45_256x48_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.046, 0.046")
+            }
+        }
+        internal_power(){
+            when : "(we_in)";
+            rise_power(fakeram45_256x48_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.046, 0.046")
+            }
+            fall_power(fakeram45_256x48_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.046, 0.046")
+            }
+        }
+    }
+    bus(w_mask_in)   {
+        bus_type : fakeram45_256x48_DATA;
+        memory_write() {
+            address : addr_in;
+            clocked_on : "clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_256x48_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (we_in) )";
+            rise_power(fakeram45_256x48_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.046, 0.046")
+            }
+            fall_power(fakeram45_256x48_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.046, 0.046")
+            }
+        }
+        internal_power(){
+            when : "(we_in)";
+            rise_power(fakeram45_256x48_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.046, 0.046")
+            }
+            fall_power(fakeram45_256x48_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.046, 0.046")
+            }
+        }
+    }
+    cell_leakage_power : 690.971;
+}
+
+}

Enablements/NanGate45/lib/fakeram45_32x32.lib

+library(fakeram45_32x32) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2022-09-13 21:51:09Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 1.1;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 1.1;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(fakeram45_32x32_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(fakeram45_32x32_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(fakeram45_32x32_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(fakeram45_32x32_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(fakeram45_32x32_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (fakeram45_32x32_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 32;
+        bit_from : 31;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (fakeram45_32x32_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 5;
+        bit_from : 4;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(fakeram45_32x32) {
+    area : 1851.360;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 5;
+        word_width : 32;
+    }
+    pin(clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.157 ;
+        internal_power(){
+            rise_power(fakeram45_32x32_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("1.345, 1.345")
+            }
+            fall_power(fakeram45_32x32_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("1.345, 1.345")
+            }
+        }
+    }
+
+    bus(rd_out)   {
+        bus_type : fakeram45_32x32_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : addr_in;
+        }
+        timing() {
+            related_pin : "clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(fakeram45_32x32_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.218, 0.218", \
+                  "0.218, 0.218" \
+                )
+            }
+            cell_fall(fakeram45_32x32_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.218, 0.218", \
+                  "0.218, 0.218" \
+                )
+            }
+            rise_transition(fakeram45_32x32_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(fakeram45_32x32_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(we_in){
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_32x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(fakeram45_32x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    pin(ce_in){
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_32x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(fakeram45_32x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    bus(addr_in)   {
+        bus_type : fakeram45_32x32_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_32x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(fakeram45_32x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    bus(wd_in)   {
+        bus_type : fakeram45_32x32_DATA;
+        memory_write() {
+            address : addr_in;
+            clocked_on : "clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (we_in) )";
+            rise_power(fakeram45_32x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(fakeram45_32x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+        internal_power(){
+            when : "(we_in)";
+            rise_power(fakeram45_32x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(fakeram45_32x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    bus(w_mask_in)   {
+        bus_type : fakeram45_32x32_DATA;
+        memory_write() {
+            address : addr_in;
+            clocked_on : "clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_32x32_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (we_in) )";
+            rise_power(fakeram45_32x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(fakeram45_32x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+        internal_power(){
+            when : "(we_in)";
+            rise_power(fakeram45_32x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(fakeram45_32x32_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    cell_leakage_power : 128.900;
+}
+
+}

Enablements/NanGate45/lib/fakeram45_512x64.lib

+library(fakeram45_512x64) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2022-09-13 21:51:05Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 1.1;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 1.1;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(fakeram45_512x64_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(fakeram45_512x64_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(fakeram45_512x64_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(fakeram45_512x64_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(fakeram45_512x64_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (fakeram45_512x64_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 64;
+        bit_from : 63;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (fakeram45_512x64_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 9;
+        bit_from : 8;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(fakeram45_512x64) {
+    area : 26182.380;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 9;
+        word_width : 64;
+    }
+    pin(clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.299 ;
+        internal_power(){
+            rise_power(fakeram45_512x64_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("7.024, 7.024")
+            }
+            fall_power(fakeram45_512x64_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("7.024, 7.024")
+            }
+        }
+    }
+
+    bus(rd_out)   {
+        bus_type : fakeram45_512x64_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : addr_in;
+        }
+        timing() {
+            related_pin : "clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(fakeram45_512x64_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.321, 0.321", \
+                  "0.321, 0.321" \
+                )
+            }
+            cell_fall(fakeram45_512x64_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.321, 0.321", \
+                  "0.321, 0.321" \
+                )
+            }
+            rise_transition(fakeram45_512x64_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(fakeram45_512x64_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(we_in){
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_512x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.070, 0.070")
+            }
+            fall_power(fakeram45_512x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.070, 0.070")
+            }
+        }
+    }
+    pin(ce_in){
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_512x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.070, 0.070")
+            }
+            fall_power(fakeram45_512x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.070, 0.070")
+            }
+        }
+    }
+    bus(addr_in)   {
+        bus_type : fakeram45_512x64_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_512x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.070, 0.070")
+            }
+            fall_power(fakeram45_512x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.070, 0.070")
+            }
+        }
+    }
+    bus(wd_in)   {
+        bus_type : fakeram45_512x64_DATA;
+        memory_write() {
+            address : addr_in;
+            clocked_on : "clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (we_in) )";
+            rise_power(fakeram45_512x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.070, 0.070")
+            }
+            fall_power(fakeram45_512x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.070, 0.070")
+            }
+        }
+        internal_power(){
+            when : "(we_in)";
+            rise_power(fakeram45_512x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.070, 0.070")
+            }
+            fall_power(fakeram45_512x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.070, 0.070")
+            }
+        }
+    }
+    bus(w_mask_in)   {
+        bus_type : fakeram45_512x64_DATA;
+        memory_write() {
+            address : addr_in;
+            clocked_on : "clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_512x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (we_in) )";
+            rise_power(fakeram45_512x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.070, 0.070")
+            }
+            fall_power(fakeram45_512x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.070, 0.070")
+            }
+        }
+        internal_power(){
+            when : "(we_in)";
+            rise_power(fakeram45_512x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.070, 0.070")
+            }
+            fall_power(fakeram45_512x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.070, 0.070")
+            }
+        }
+    }
+    cell_leakage_power : 1327.240;
+}
+
+}

Enablements/NanGate45/lib/fakeram45_64x124.lib

+library(fakeram45_64x124) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2022-09-13 21:51:08Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 1.1;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 1.1;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(fakeram45_64x124_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(fakeram45_64x124_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(fakeram45_64x124_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(fakeram45_64x124_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(fakeram45_64x124_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (fakeram45_64x124_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 124;
+        bit_from : 123;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (fakeram45_64x124_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 6;
+        bit_from : 5;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(fakeram45_64x124) {
+    area : 9812.208;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 6;
+        word_width : 124;
+    }
+    pin(clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.207 ;
+        internal_power(){
+            rise_power(fakeram45_64x124_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("5.492, 5.492")
+            }
+            fall_power(fakeram45_64x124_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("5.492, 5.492")
+            }
+        }
+    }
+
+    bus(rd_out)   {
+        bus_type : fakeram45_64x124_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : addr_in;
+        }
+        timing() {
+            related_pin : "clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(fakeram45_64x124_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.238, 0.238", \
+                  "0.238, 0.238" \
+                )
+            }
+            cell_fall(fakeram45_64x124_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.238, 0.238", \
+                  "0.238, 0.238" \
+                )
+            }
+            rise_transition(fakeram45_64x124_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(fakeram45_64x124_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(we_in){
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_64x124_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.055, 0.055")
+            }
+            fall_power(fakeram45_64x124_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.055, 0.055")
+            }
+        }
+    }
+    pin(ce_in){
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_64x124_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.055, 0.055")
+            }
+            fall_power(fakeram45_64x124_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.055, 0.055")
+            }
+        }
+    }
+    bus(addr_in)   {
+        bus_type : fakeram45_64x124_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_64x124_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.055, 0.055")
+            }
+            fall_power(fakeram45_64x124_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.055, 0.055")
+            }
+        }
+    }
+    bus(wd_in)   {
+        bus_type : fakeram45_64x124_DATA;
+        memory_write() {
+            address : addr_in;
+            clocked_on : "clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (we_in) )";
+            rise_power(fakeram45_64x124_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.055, 0.055")
+            }
+            fall_power(fakeram45_64x124_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.055, 0.055")
+            }
+        }
+        internal_power(){
+            when : "(we_in)";
+            rise_power(fakeram45_64x124_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.055, 0.055")
+            }
+            fall_power(fakeram45_64x124_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.055, 0.055")
+            }
+        }
+    }
+    bus(w_mask_in)   {
+        bus_type : fakeram45_64x124_DATA;
+        memory_write() {
+            address : addr_in;
+            clocked_on : "clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x124_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (we_in) )";
+            rise_power(fakeram45_64x124_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.055, 0.055")
+            }
+            fall_power(fakeram45_64x124_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.055, 0.055")
+            }
+        }
+        internal_power(){
+            when : "(we_in)";
+            rise_power(fakeram45_64x124_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.055, 0.055")
+            }
+            fall_power(fakeram45_64x124_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.055, 0.055")
+            }
+        }
+    }
+    cell_leakage_power : 415.087;
+}
+
+}

Enablements/NanGate45/lib/fakeram45_64x62.lib

+library(fakeram45_64x62) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2022-09-13 21:51:07Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 1.1;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 1.1;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(fakeram45_64x62_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(fakeram45_64x62_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(fakeram45_64x62_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(fakeram45_64x62_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(fakeram45_64x62_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (fakeram45_64x62_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 62;
+        bit_from : 61;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (fakeram45_64x62_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 6;
+        bit_from : 5;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(fakeram45_64x62) {
+    area : 5728.310;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 6;
+        word_width : 62;
+    }
+    pin(clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.193 ;
+        internal_power(){
+            rise_power(fakeram45_64x62_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("3.326, 3.326")
+            }
+            fall_power(fakeram45_64x62_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("3.326, 3.326")
+            }
+        }
+    }
+
+    bus(rd_out)   {
+        bus_type : fakeram45_64x62_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : addr_in;
+        }
+        timing() {
+            related_pin : "clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(fakeram45_64x62_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.237, 0.237", \
+                  "0.237, 0.237" \
+                )
+            }
+            cell_fall(fakeram45_64x62_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.237, 0.237", \
+                  "0.237, 0.237" \
+                )
+            }
+            rise_transition(fakeram45_64x62_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(fakeram45_64x62_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(we_in){
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_64x62_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.033, 0.033")
+            }
+            fall_power(fakeram45_64x62_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.033, 0.033")
+            }
+        }
+    }
+    pin(ce_in){
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_64x62_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.033, 0.033")
+            }
+            fall_power(fakeram45_64x62_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.033, 0.033")
+            }
+        }
+    }
+    bus(addr_in)   {
+        bus_type : fakeram45_64x62_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram45_64x62_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.033, 0.033")
+            }
+            fall_power(fakeram45_64x62_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.033, 0.033")
+            }
+        }
+    }
+    bus(wd_in)   {
+        bus_type : fakeram45_64x62_DATA;
+        memory_write() {
+            address : addr_in;
+            clocked_on : "clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (we_in) )";
+            rise_power(fakeram45_64x62_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.033, 0.033")
+            }
+            fall_power(fakeram45_64x62_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.033, 0.033")
+            }
+        }
+        internal_power(){
+            when : "(we_in)";
+            rise_power(fakeram45_64x62_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.033, 0.033")
+            }
+            fall_power(fakeram45_64x62_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.033, 0.033")
+            }
+        }
+    }
+    bus(w_mask_in)   {
+        bus_type : fakeram45_64x62_DATA;
+        memory_write() {
+            address : addr_in;
+            clocked_on : "clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(fakeram45_64x62_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (we_in) )";
+            rise_power(fakeram45_64x62_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.033, 0.033")
+            }
+            fall_power(fakeram45_64x62_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.033, 0.033")
+            }
+        }
+        internal_power(){
+            when : "(we_in)";
+            rise_power(fakeram45_64x62_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.033, 0.033")
+            }
+            fall_power(fakeram45_64x62_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.033, 0.033")
+            }
+        }
+    }
+    cell_leakage_power : 280.070;
+}
+
+}

Flows/util/RePlAceFlow/convert_bookshelf2odb.py

+import odb
+import os
+import datetime
+import math
+from math import gcd
+
+class BookshelfToOdb:
+    def __init__(
+            self,
+            opendbpy,
+            opendb,
+            cellPadding,
+            modeFormat,
+            plFile,
+            nodeMapFile,
+            netMapFile):
+        self.odbpy = opendbpy
+        self.odb = opendb
+        self.year = datetime.datetime.now().year
+        self.month = datetime.datetime.now().strftime("%b")
+        self.day = datetime.datetime.now().day
+        self.user = 'Seungwon Kim at University of California, San Diego (sek006@ucsd.edu)'
+        self.modeFormat = modeFormat
+        self.plFile = plFile
+        self.nodeMapFile = nodeMapFile
+        self.netMapFile = netMapFile
+
+        self.chip = self.odb.getChip()
+        self.block = self.chip.getBlock()
+        self.siteWidth = self.block.getRows()[0].getSite().getWidth()
+        self.siteHeight = self.block.getRows()[0].getSite().getHeight()
+        print("siteWidth: %s" % self.siteWidth)
+        print("siteHeight: %s" % self.siteHeight)
+        print("GCD: %s" % gcd(self.siteWidth, self.siteHeight))
+        #self.scaleFactor = self.targetScale / self.siteHeight
+        self.scaleFactor = 1 / gcd(self.siteWidth, self.siteHeight)
+        self.targetScale = self.scaleFactor * self.siteHeight
+        print("Target siteHeight Scale: %s" % self.targetScale)
+        print(
+            "Scale Factor (Target siteHeight Scale / siteHeight): %s" %
+            self.scaleFactor)
+
+    def UpdatePl(self, dictNode):
+        with open(self.plFile, 'r') as inFile:
+            for line in inFile:
+                if len(line) < 3:
+                    continue
+                if line.strip().startswith("UCLA"):
+                    continue
+                if line.strip().startswith("#"):
+                    continue
+                elif ':' not in line:
+                    continue
+                elif self.modeFormat == 'ISPD11' and line.split()[-1] == '/FIXED':
+                    # Fixed insts.
+                    # It has defined in the original ODB, so don't need to
+                    # update.
+                    continue
+                elif (self.modeFormat == 'ISPD11' and line.split()[-1] == '/FIXED_NI') or (self.modeFormat != 'ISPD11' and line.split()[-1] == '/FIXED'):
+                    # Fixed insts + boundary terminals
+                    instMappedName = line.split()[0]
+                    instLlx = float(line.split()[1])
+                    instLly = float(line.split()[2])
+                    instOrigName = dictNode[instMappedName]
+                    #print(instOrigName, instMappedName)
+                    # print(self.block.findBTerm(instOrigName))
+                    bTerm = self.block.findBTerm(instOrigName)
+                    if bTerm is not None:
+                        bPins = bTerm.getBPins()
+                        for bPin in bPins:
+
+                            boxes = bPin.getBoxes()
+                            # TODO: do not support multiple boxes
+                            assert(len(boxes) == 1)
+                            for box in boxes:
+                                bTermWidth = int(box.xMax() - box.xMin())
+                                bTermHeight = int(box.yMax() - box.yMin())
+                                #print(bTermWidth, bTermHeight)
+
+                                layerBPin = box.getTechLayer()
+                                bPin.destroy(bPin)
+                                bPin.create(bTerm)
+                                bPinLlx = int(instLlx / self.scaleFactor)
+                                bPinLly = int(instLly / self.scaleFactor)
+                                bPinUrx = int(
+                                    instLlx / self.scaleFactor) + int(bTermWidth)
+                                bPinUry = int(
+                                    instLly / self.scaleFactor) + int(bTermHeight)
+                                box.create(
+                                    bPin, layerBPin, bPinLlx, bPinLly, bPinUrx, bPinUry)
+                                # print(bPinLlx,bPinLly,bPinUrx,bPinUry)
+                                bPin.setPlacementStatus('PLACED')
+                                # TODO: Snapping to on-track?
+                    continue
+                else:
+                    instMappedName = line.split()[0]
+                    instLlx = float(line.split()[1])
+                    instLly = float(line.split()[2])
+                    instOrigName = dictNode[instMappedName]
+                    #print(instOrigName, instMappedName)
+                    # print(self.block.findInst(instOrigName))
+
+                    instOrig = self.block.findInst(instOrigName)
+                    instOrigWidth = instOrig.getMaster().getWidth()
+                    instOrigHeight = instOrig.getMaster().getHeight()
+
+                    instOrigLlx = int(instLlx / self.scaleFactor)
+                    instOrigLly = int(instLly / self.scaleFactor)
+
+                    instOrig.setLocation(instOrigLlx, instOrigLly)
+                    instOrig.setPlacementStatus('PLACED')
+                    # TODO: Snapping to on-track?
+
+    def DecodeMap(self):
+        dictNode = dict()
+        with open(self.nodeMapFile, 'r') as inFile:
+            for line in inFile:
+                origName = line.split()[0]
+                mappedName = line.split()[1]
+                dictNode[mappedName] = origName
+
+        return dictNode
+
+    def UpdateOdb(self):
+        dictNode = self.DecodeMap()
+        self.UpdatePl(dictNode)
+        os.path.exists
+        dbName = './output/%s_pad%s_%s/%s_pad%s_%s_mapped.odb' % (
+            odbName, cellPadding, modeFormat, odbName, cellPadding, modeFormat)
+        defName = './output/%s_pad%s_%s/%s_mapped.def' % (
+            odbName, cellPadding, modeFormat, odbName)
+
+        if os.path.exists(dbName):
+            os.remove(dbName)
+        if os.path.exists(defName):
+            os.remove(defName)
+
+        odb.write_db(
+            self.odb,
+            './%s_pad%s_%s/%s_pad%s_%s_mapped.odb' %
+            (odbName,
+             cellPadding,
+             modeFormat,
+             odbName,
+             cellPadding,
+             modeFormat))
+        odb.write_def(
+            self.block,
+            './%s_pad%s_%s/%s_mapped.def' %
+            (odbName,
+             cellPadding,
+             modeFormat,
+             odbName))
+
+
+if __name__ == "__main__":
+
+    ################ Settings #################
+    odbPath = './odbFiles'
+
+    # The number of sites for cell padding (+left, +right)
+    cellPaddings = [0, 1, 2, 3, 4]
+
+    # Format list of Bookshelf to be created.
+    modeFormats = ['ISPD04', 'ISPD11']
+
+    # OpenDB list for Bookshelf generation
+    odbList = [
+        'sky130hd_ISPD2006_adaptec1',
+    ]
+    ###########################################
+
+    for modeFormat in modeFormats:
+        for cellPadding in cellPaddings:
+            for odbName in odbList:
+                plFile = './output/%s_pad%s_%s/%s_pad%s_%s_mapped.ntup.pl' % (
+                    odbName, cellPadding, modeFormat, odbName, cellPadding, modeFormat)
+                nodeMapFile = './output/%s_pad%s_%s/%s_pad%s_%s_mapped.nodemap' % (
+                    odbName, cellPadding, modeFormat, odbName, cellPadding, modeFormat)
+                netMapFile = './output/%s_pad%s_%s/%s_pad%s_%s_mapped.netmap' % (
+                    odbName, cellPadding, modeFormat, odbName, cellPadding, modeFormat)
+                db = odb.dbDatabase.create()
+                print(odb)
+                odb.read_db(db, '%s/%s.odb' % (odbPath, odbName))
+                bs = BookshelfToOdb(
+                    opendbpy=odb,
+                    opendb=db,
+                    cellPadding=cellPadding,
+                    modeFormat=modeFormat,
+                    plFile=plFile,
+                    nodeMapFile=nodeMapFile,
+                    netMapFile=netMapFile)
+                bs.UpdateOdb()

Flows/util/convert_odb2bookshelf.py → Flows/util/RePlAceFlow/convert_odb2bookshelf.py

-#import opendbpy as odb
 import odb
 import os
 import datetime
 import math
+import namemap
 from math import gcd
-# import namemap
 
 
 class OdbToBookshelf:
@@ -126,7 +125,7 @@ class OdbToBookshelf:
     def WriteNodes(self, bsName):
         print("Writing .nodes")
         f = open('./output/%s/%s.nodes' % (bsName, bsName), 'w')
-        f.write('UCSD nodes 1.0\n')
+        f.write('UCLA nodes 1.0\n')
         f.write(
             '# Created  :  %s  %s %s\n' %
             (self.month, self.day, self.year))
@@ -214,7 +213,7 @@ class OdbToBookshelf:
     def WriteRoute(self, bsName):
         print("Writing .route")
         f = open('./output/%s/%s.route' % (bsName, bsName), 'w')
-        f.write('UCSD route 1.0\n')
+        f.write('UCLA route 1.0\n')
         f.write(
             '# Created  :  %s  %s %s\n' %
             (self.month, self.day, self.year))
@@ -435,7 +434,7 @@ class OdbToBookshelf:
     def WriteWts(self, bsName):
         print("Writing .wts")
         f = open('./output/%s/%s.wts' % (bsName, bsName), 'w')
-        f.write('UCSD wts 1.0\n')
+        f.write('UCLA wts 1.0\n')
         f.write(
             '# Created  :  %s  %s %s\n' %
             (self.month, self.day, self.year))
@@ -445,7 +444,7 @@ class OdbToBookshelf:
     def WriteNets(self, bsName):
         print("Writing .nets")
         f = open('./output/%s/%s.nets' % (bsName, bsName), 'w')
-        f.write('UCSD nets 1.0\n')
+        f.write('UCLA nets 1.0\n')
         f.write(
             '# Created  :  %s  %s %s\n' %
             (self.month, self.day, self.year))
@@ -531,29 +530,15 @@ class OdbToBookshelf:
                         #
                         # "getGeomShape().getPoints()" --> a, b, c, d, a
                         #
-                        #tx = 0
-                        #ty = 0
-                        # t = odb.dbTransform(instOrient, instOrig)
-                        # Calculate center of pin
-                        # for pp in box.getGeomShape().getPoints()[:-1]:
-                        #     t.apply(pp)
-                        #     tx = tx + float(pp.getX())
-                        #     ty = ty + float(pp.getY())
-                        #     #print("tx, ty = %s %s"%(pp.getX()/1000,pp.getY()/1000))
-                        #     tt = tt + 1
                         rr = odb.Rect(box.xMin(), box.yMin(), box.xMax(), box.yMax())
+                        
+                        # Calculate center of pin
                         for pp in rr.getPoints():
                             t.apply(pp)
-                            # print('Hi ',type(pp), type(box))
-                        # print('Here ', box.xMin(), box.yMin(), box.xMax(), box.yMax())
-                        # 
-                        # print(pp)
-                        # # box.getBox(pp)
-                        # print(type(pp))
-                        # t.apply(pp)
                             tt += 1
-                            tx += pp.getX()
-                            ty += pp.getY()
+                            tx += float(pp.getX())
+                            ty += float(pp.getY())
+
 
                 iPinXCen = float(tx) / float(tt)
                 iPinYCen = float(ty) / float(tt)
@@ -575,7 +560,7 @@ class OdbToBookshelf:
     def WritePl(self, bsName):
         print("Writing .pl")
         f = open('./output/%s/%s.pl' % (bsName, bsName), 'w')
-        f.write('UCSD pl 1.0\n')
+        f.write('UCLA pl 1.0\n')
         f.write(
             '# Created  :  %s  %s %s\n' %
             (self.month, self.day, self.year))
@@ -637,7 +622,7 @@ class OdbToBookshelf:
     def WriteScl(self, bsName):
         print("Writing .scl")
         f = open('./output/%s/%s.scl' % (bsName, bsName), 'w')
-        f.write('UCSD scl 1.0\n')
+        f.write('UCLA scl 1.0\n')
         f.write(
             '# Created  :  %s  %s %s\n' %
             (self.month, self.day, self.year))
@@ -731,7 +716,7 @@ class OdbToBookshelf:
     def WriteShapes(self, bsName):
         print("Writing .shapes")
         f = open('./output/%s/%s.shapes' % (bsName, bsName), 'w')
-        f.write('UCSD shapes 1.0\n')
+        f.write('UCLA shapes 1.0\n')
         f.write(
             '# Created  :  %s  %s %s\n' %
             (self.month, self.day, self.year))
@@ -808,11 +793,11 @@ class OdbToBookshelf:
         self.show(bsName)
 
         # convert for mapping
-        # self.convert(bsName)
+        self.convert(bsName)
 
     def convert(self, bsName):
         os.chdir('output/%s' % bsName)
-        # namemap.main('%s.aux' % bsName)
+        namemap.main('%s.aux' % bsName)
         os.chdir('../../')
 
     def show(self, bsName):

Flows/util/RePlAceFlow/lefdef_to_odb.py

+'''
+This script generates OpenDB database from LEF/DEF 
+'''
+import odb
+import sys
+import os
+import re
+
+design = sys.argv[1]
+def_file = sys.argv[2]
+output_dir = sys.argv[3]
+
+work_dir = re.search(r'(/\S+/MacroPlacement)', os.getcwd()).group(1)
+sys.path.append(f'{work_dir}/Flows/util')
+
+from convert_odb2bookshelf import OdbToBookshelf
+
+
+lef_dir = f'{work_dir}/Enablements/NanGate45/lef'
+lef_list = [f'{lef_dir}/NangateOpenCellLibrary.tech.lef',
+            f'{lef_dir}/NangateOpenCellLibrary.macro.mod.lef',
+            f'{lef_dir}/fakeram45_256x16.lef']
+
+db = odb.dbDatabase.create()
+for lef_file in lef_list:
+    odb.read_lef(db, lef_file)
+
+odb.read_def(db, def_file)
+chip = db.getChip()
+tech = db.getTech()
+libs = db.getLibs()
+
+if chip is None:
+    exit("ERROR: READ DEF Failed")
+
+if not os.path.exists(f'{output_dir}/RePlAce'):
+    os.makedirs(f'{output_dir}/RePlAce')
+
+odb_file = f'{output_dir}/RePlAce/{design}.odb'
+export_result = odb.write_db(db, odb_file)
+
+if export_result != 1:
+    exit("ERROR: Export failed")
+
+
+new_db = odb.dbDatabase.create()
+odb.read_db(new_db, odb_file)
+
+if new_db is None:
+    exit("ERROR: Import failed")
+
+if odb.db_diff(db, new_db):
+    exit("ERROR: Difference found in exported and imported DB")
+
+print(f"Successfully generated ODB format from LEF/DEF for {design}")
+
+bs = OdbToBookshelf(
+    opendbpy=odb, 
+    opendb=db, 
+    cellPadding=0,
+    modeFormat="ISPD11",
+    layerCapacity='layeradjust_empty.tcl')
+
+bs.WriteBookshelf(f'{design}_pad0_ISPD11')

Flows/util/RePlAceFlow/namemap.py

+import sys
+import subprocess as sp
+
+
+def ExecuteCommand(command):
+    print(command)
+    sp.call(command, shell=True)
+
+
+def main(arg1):
+    print(arg1, "is parsing...")
+    f = open(arg1)
+    auxCont = f.read()
+    f.close()
+
+    fileList = []
+    afterColon = False
+    for word in auxCont.split(" "):
+        if word == ":":
+            afterColon = True
+            continue
+        if afterColon:
+            fileList.append(word.strip())
+
+    print(fileList)
+
+    nodeName = [l for l in fileList if l.endswith("nodes")][0]
+    netName = [l for l in fileList if l.endswith("nets")][0]
+    plName = [l for l in fileList if l.endswith("pl")][0]
+    routeName = [l for l in fileList if l.endswith("route")][0]
+    #routeName = nodeName.split(".")[0]+".route"
+    benchName = nodeName.split(".")[0]
+    print(nodeName, netName, plName, routeName)
+
+    #######################################
+    # Nodes Mapping
+    #######################################
+
+    f = open(nodeName, "r")
+    nodeCont = f.read()
+    f.close()
+
+    nameMap = dict()
+    instCnt = 0
+    pinCnt = 0
+
+    newCont = ""
+    isFirst = True
+    for curLine in nodeCont.split("\n"):
+        wordList = curLine.split()
+        if isFirst:
+            isFirst = False
+            newCont += curLine + "\n"
+            continue
+        if len(wordList) is 0:
+            newCont += "\n"
+            continue
+        if wordList[0] is "#":
+            newCont += curLine + "\n"
+            continue
+        if wordList[0] == "NumNodes" or wordList[0] == "NumTerminals":
+            newCont += curLine + "\n"
+            continue
+
+        newWord = ""
+        # if len(wordList) >= 4 and wordList[1] is "0" and wordList[2] is "0":
+        if len(wordList) >= 4 and wordList[1] is "1" and wordList[2] is "1":
+            newWord = "p" + str(pinCnt)
+            pinCnt += 1
+            # newCont += newWord + " " + wordList[1] + " " + wordList[2] + " " + wordList[3] + "\n"
+            #newCont += "  " + newWord + " 0 0 terminal_NI\n"
+            newCont += "  " + newWord + " 1 1 terminal_NI\n"
+        elif len(wordList) >= 4 and wordList[3] == "terminal":
+            #newWord = "p"+str(pinCnt)
+            #pinCnt += 1
+            newWord = "o" + str(instCnt)
+            instCnt += 1
+            newCont += "  " + newWord + " " + " ".join(wordList[1:]) + "\n"
+        else:
+            newWord = "o" + str(instCnt)
+            instCnt += 1
+            newCont += "  " + newWord + " " + \
+                wordList[1] + " " + wordList[2] + "\n"
+        nameMap[wordList[0]] = newWord
+
+    f = open(benchName + "_mapped.nodes", "w")
+    f.write(newCont)
+    f.close()
+
+    newCont = ""
+    for key, cont in nameMap.items():
+        newCont += "%s %s\n" % (key, cont)
+    f = open(benchName + "_mapped.nodemap", "w")
+    f.write(newCont)
+    f.close()
+
+    #######################################
+    # Nets Mapping
+    #######################################
+
+    f = open(netName, "r")
+    netCont = f.read()
+    f.close()
+
+    newCont = ""
+    isFirst = True
+
+    netCnt = 0
+    netNameMap = dict()
+
+    for curLine in netCont.split("\n"):
+        wordList = curLine.split()
+        if isFirst:
+            isFirst = False
+            newCont += curLine + "\n"
+            continue
+        if len(wordList) is 0:
+            newCont += "\n"
+            continue
+        if wordList[0] is "#":
+            newCont += curLine + "\n"
+            continue
+        if wordList[0] == "NumNets" or wordList[0] == "NumPins":
+            newCont += curLine + "\n"
+            continue
+        if wordList[0] == "NetDegree":
+            newWord = "n" + str(netCnt)
+            netCnt += 1
+            netNameMap[wordList[3]] = newWord
+            newCont += " ".join(wordList[0:3]) + " " + newWord + "\n"
+            continue
+
+        newCont += "  " + nameMap[wordList[0]] + " " + wordList[1] + \
+            " " + wordList[2] + " " + wordList[3] + " " + wordList[4] + "\n"
+    f = open(benchName + "_mapped.nets", "w")
+    f.write(newCont)
+    f.close()
+
+    newCont = ""
+    for key, cont in netNameMap.items():
+        newCont += "%s %s\n" % (key, cont)
+    f = open(benchName + "_mapped.netmap", "w")
+    f.write(newCont)
+    f.close()
+
+    #######################################
+    # DP PL Mapping
+    #######################################
+    #
+    #dpPlName = plName.split(".")[0] + ".ntup.pl"
+    #f = open(dpPlName, "r")
+    #plCont= f.read()
+    # f.close()
+    #
+    #newCont = ""
+    #isFirst = True
+    #
+    # for curLine in plCont.split("\n"):
+    #  wordList = curLine.split()
+    #  if isFirst:
+    #    isFirst = False
+    #    newCont += curLine + "\n"
+    #    continue
+    #  if len(wordList) is 0:
+    #    newCont += "\n"
+    #    continue
+    #  if wordList[0] is "#":
+    #    newCont += curLine + "\n"
+    #    continue
+    #  if len(wordList) == 5:
+    #    newCont += nameMap[ wordList[0] ] + " " + " ".join(wordList[1:5]) + "\n"
+    #  elif len(wordList) == 6:
+    #    newCont += nameMap[ wordList[0] ] + " " + " ".join(wordList[1:6]) + "\n"
+    #
+    #f = open(benchName + "_mapped.ntup.pl", "w")
+    # f.write(newCont)
+    # f.close()
+    #
+    #######################################
+    # GP PL Mapping
+    #######################################
+
+    gpPlName = plName.split(".")[0] + ".pl"
+    f = open(gpPlName, "r")
+    plCont = f.read()
+    f.close()
+
+    newCont = ""
+    isFirst = True
+
+    for curLine in plCont.split("\n"):
+        wordList = curLine.split()
+        if isFirst:
+            isFirst = False
+            newCont += curLine + "\n"
+            continue
+        if len(wordList) is 0:
+            newCont += "\n"
+            continue
+        if wordList[0] is "#":
+            newCont += curLine + "\n"
+            continue
+        if len(wordList) == 5:
+            newCont += nameMap[wordList[0]] + \
+                " " + " ".join(wordList[1:5]) + "\n"
+        elif len(wordList) == 6:
+            newCont += nameMap[wordList[0]] + \
+                " " + " ".join(wordList[1:6]) + "\n"
+
+    f = open(benchName + "_mapped.pl", "w")
+    f.write(newCont)
+    f.close()
+
+    #######################################
+    # ROUTE Mapping
+    #######################################
+
+    f = open(routeName, "r")
+    routeCont = f.read()
+    f.close()
+
+    newCont = ""
+    isFirst = True
+
+    for curLine in routeCont.split("\n"):
+        wordList = curLine.split()
+        if isFirst:
+            isFirst = False
+            newCont += curLine + "\n"
+            continue
+        if len(wordList) is 0:
+            newCont += "\n"
+            continue
+        if wordList[0] is "#":
+            newCont += curLine + "\n"
+            continue
+        if ":" in wordList:
+            newCont += curLine + "\n"
+            continue
+        newCont += "  " + nameMap[wordList[0]] + "  " + \
+            "  ".join(wordList[1:len(wordList)]) + "\n"
+
+    f = open(benchName + "_mapped.route", "w")
+    f.write(newCont)
+    f.close()
+
+    #######################################
+    # scl, wts Mapping
+    #######################################
+
+    ExecuteCommand("cp %s.scl %s.scl" % (benchName, benchName + "_mapped"))
+    ExecuteCommand("cp %s.wts %s.wts" % (benchName, benchName + "_mapped"))
+
+    #######################################
+    # shapes Mapping
+    #######################################
+
+    f1 = open(benchName + "_mapped.nodemap", "r")
+    linesMap = f1.readlines()
+    f1.close()
+
+    listOrigName = []
+    listMapName = []
+    for line in linesMap:
+        listOrigName.append(line.split()[0])
+        listMapName.append(line.split()[1])
+
+    f2 = open(benchName + ".shapes", "r")
+    linesShapes = f2.readlines()
+    f2.close()
+    # Search mapping name from '.nodemap' file.
+
+    f = open(benchName + "_mapped.shapes", "w")
+    for line in linesShapes:
+        if len(line.split()) > 1:
+            if ':' == line.split()[1] and line.split()[
+                    0] != 'NumNonRectangularNodes':
+                origName = line.split()[0]
+                idxMap = listOrigName.index(origName)
+                f.write('%s  :  %s\n' % (listMapName[idxMap], line.split()[2]))
+                continue
+            else:
+                f.write(line)
+        else:
+            f.write(line)
+
+    f.close()
+
+    #######################################
+    # aux writing
+    #######################################
+
+    f = open(benchName + "_mapped.aux", "w")
+    newCont = "RowBasedPlacement : %s_mapped.nodes %s_mapped.nets %s_mapped.wts %s_mapped.pl %s_mapped.scl %s_mapped.shapes %s_mapped.route" % (
+        benchName, benchName, benchName, benchName, benchName, benchName, benchName)
+    f.write(newCont)
+    f.close()

Flows/util/RePlAceFlow/runme

+rm -rf output/ ETC/ outputs/
+
+# run ODB to Bookshelf
+#./openroad -python odb2bs.py
+./openroad -python lefdef_to_odb.py ariane ../../ariane_replace.def ./
+
+# prepare input dir structure for RePlAce
+mkdir -p ETC/
+ln -s $(readlink -f ./output/*) ./ETC/
+
+# run RePlAce. If you want to change density, please put -den 0.8 (80%), etc.
+./RePlAce-static -bmflag etc -bmname ariane_pad0_ISPD11 -pcofmax 1.03 |& tee replace_result.log
+
+# bring the results
+#ln -s outputs/ETC/ariane_pad0_ISPD11/experiment0/*.pl ./
+
+# you can run invs to load *.pl results from here

Flows/util/namemap.py

-/home/mgwoo/95_openroad/rosettaStone/github/RosettaStone/odbComm/namemap.py
\ No newline at end of file

Flows/util/odb_to_bookshelf.py

-'''
-This script generates bookshelf format from odb format
-'''
-import os
-import odb
-import sys
-import re
-
-work_dir = re.search(r'(/\S+/MacroPlacement)', os.getcwd()).group(1)
-sys.path.append(f'{work_dir}/Flows/util')
-
-from convert_odb2bookshelf import OdbToBookshelf
-
-design = sys.argv[1]
-odb_file = sys.argv[2]
-output_dir = sys.argv[3]
-
-modeFormat = 'ISPD11'
-cellPadding = 0
-layerCapacity = 'layeradjust_empty.tcl'
-
-def touch(fname, times=None):
-    with open(fname, 'a'):
-        os.utime(fname, times)
-
-if  not os.path.exists(layerCapacity):
-    touch(layerCapacity)
-
-db = odb.dbDatabase.create()
-odb.read_db(db, odb_file)
-bs = OdbToBookshelf(opendbpy=odb, opendb=db, cellPadding=cellPadding,
-                    modeFormat=modeFormat, layerCapacity=layerCapacity)
-
-if not os.path.exists(f'{output_dir}/RePlAce'):
-    os.makedirs(f'{output_dir}/RePlAce')
-
-bs.WriteBookshelf(f'{design}.bookshelf')

Flows/util/write_required_def.tcl

@@ -2,7 +2,7 @@
 deselectAll
 set top_module [dbget top.name]
 
-if {[dbget top.terms.pStatus -v -e fixed] == "" } {
+if {[dbget top.terms.pStatus -v -e fixed] != "" } {
     source ../../../../util/place_pin.tcl
 }
 

README.md

@@ -201,7 +201,8 @@ while allowing soft macros (standard-cell clusters) to also find good locations.
 - [Hypergraph clustering](./CodeElements/Clustering/) clusters millions of standard cells into a few thousand clusters.  In Circuit Training, the purpose of clustering is to enable an approximate but fast standard cell placement that facilitates policy network optimization.
 - [Force-directed placement](./CodeElements/FDPlacement/) places the center of each standard cell cluster onto  centers of gridcells generated by [Gridding](./CodeElements/Gridding/).
 - [Simulated annealing](./CodeElements/SimulatedAnnealing/) places the center of each macro onto centers of gridcells generated by [Gridding](./CodeElements/Gridding/).  In Circuit Training,  simulated annealing is used as a baseline to show the relative sample efficiency of RL.
-- [LEF/DEF and Bookshelf (OpenDB, RosettaStone) translators](./CodeElements/FormatTranslators/) ease the translation between different representations of the same netlist. 
+- [LEF/DEF and Bookshelf (OpenDB, RosettaStone) translators](./CodeElements/FormatTranslators/) ease the translation between different representations of the same netlist.
+- [Plc client](./CodeElements/Plc_client/) implements all three components of the proxy cost function: wirelength cost, density cost and congestion cost.
 
 
 <!--## **Reproducible Example Solutions** -->
@@ -218,18 +219,16 @@ We provide a competitive baseline for [Google Brain's Circuit Training](https://
 - We do understand that Google has been working hard to complete the open-sourcing of Morpheus, and that this effort continues today. However, as pointed out in [this Doc](https://docs.google.com/document/d/1vkPRgJEiLIyT22AkQNAxO8JtIKiL95diVdJ_O4AFtJ8/edit?usp=sharing), it has been more than a year since "Data and Code Availability" was committed with publication of the [Nature paper](https://www.nature.com/articles/s41586-021-03544-w). We consider our work a "backstop" or "safety net" for Google's internal efforts, and a platform for researchers to build on. 
 
 **What can others contribute?**
-- Our shopping list includes the following. Please join in! 
-  - force-directed placement (and API): documentation and implementation
-  - adjacency matrix generation: documentation and implementation
+- Our shopping list (updated August 2022) includes the following. Please join in!  
   - simulated annealing on the gridded canvas: documentation and implementation
+  - force-directed placement: documentation and implementation
   - donated cloud resources (credits) for experimental studies
   - relevant testcases with reference implementations and implementation flows (Cadence, OpenROAD preferred since scripts can be shared)
-  - protobuf, lef/def, Bookshelf: detailed and confirmed documentation, plus tests and other help to improve our initial versions of translators
-  - "fakeram" generator for the ASAP7 research PDK
-  - qrctechfile for NanGate45
+  - improved "fakeram" generator for the ASAP7 research PDK
 
 **What is your timeline?**
-- We hope to show significant progress at the [DAC-2022 Birds-of-a-Feather](https://59dac.conference-program.com/session/?sess=sess294) meeting (Open-Source EDA and Benchmarking Summit) on July 12, 2022, 7-10pm in Room 3000 of Moscone West in San Francisco.
+- We showed our [progress](https://open-source-eda-birds-of-a-feather.github.io/doc/slides/MacroPlacement-SpecPart-DAC-BOF-v5.pdf) at the Open-Source EDA and Benchmarking Summit birds-of-a-feather [meeting](https://open-source-eda-birds-of-a-feather.github.io/) on July 12 at DAC-2022.
+- We are now (late August 2022) studying benefits and limitations of the CT methodology itself, as noted in [this Doc](https://docs.google.com/document/d/1c-uweo3DHiCWZyBzAdNCqqcOrAbKq1sVIfY0_4bFCYE/edit).
 
 
 ## **Related Links**