@@ -17,6 +17,9 @@ The setup to run SP&R on the available test cases for the given enablements are
-[Ariane133](./SKY130HD/ariane133/)
-[MemPool tile](./SKY130HD/mempool_tile/)
-[NVDLA](./SKY130HD/nvdla/)
-[Scripts](./scripts/)
-[Cadence](./scripts/cadence/)
-[DCTopo](./scripts/DCTopoFlow/)
-[Utility](./util/)
- Contains utility scripts for SP&R runs.
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@@ -32,16 +35,18 @@ Inside each directory are the following sub-directories that contain all of the
The runscripts for all the flows are available in the *./\<enablement\>/\<testcase\>/scripts/* directory. Inside *script* directory are the following sub-directories.
-*cadence* directory contains all the runscripts related to [Flow-1](./figures/flow-1.PNG), [Flow-2](./figures/flow-2.PNG). We will also add [Flow-4](./figures/flow-4.PNG) scripts here.
-*OpenROAD* directory contains the *<testcase>.tar.gz* file, which includes all the required files to run [Flow-3](./figures/flow-3.PNG) using OpenROAD-flow-scripts ([ORFS](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/)).
- We provide detailed scripts to run physical synthesis using Synopsys DCTopo. All the scripts are available in the [*./scripts/DCTopoFlow*](./scripts/DCTopoFlow/) directory. We also add the scripts required to generate the inputs for DCTopo along with the detailed description of each step.
All the flows uses the *RTL* from the [*Testcases*](../Testcases/) directory and the *.lef*, *.lib* and *qrc* files from the [*Enablements*](../Enablements/) directory. The required SRAM models for each testcase are generated and also available under the [*Enablements*](../Enablements/) directory. The detailed steps for different tools are as follows.
All the required runscripts are available in the *./\<enablement\>/\<testcase\>/scripts/cadence/* directory. The steps to modify *run.sh* to launch SP&R runs for Flow-1 and Flow-2 are as follows.
- To launch Flow-1 set the **PHY_SYNTH** environment variable to *0* in the *run.sh* file.
``` export PHY_SYNTH=0 ```
- To laucnh Flow-2 set the **PHY_SYNTH** environment variable to *1* in the *run.sh* file.
- To launch Flow-2 set the **PHY_SYNTH** environment variable to *1* in the *run.sh* file.
``` export PHY_SYNTH=1 ```
- To start the SP&R run use the following command.
We implement [Ariane design with 133 macros](../../../Testcases/ariane133) on the [SKY130HD](../../../Enablements/SKY130HD) platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R).
We implement [Ariane design with 133 macros](../../../Testcases/ariane133) on the [SKY130HD FakeStack](../../../Enablements/SKY130HD) platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R).
The screenshot of the design using Cadence Flow-1 on SKY130HD enablement is shown below
The screenshot of the design using Cadence Flow-1 on SKY130HD FakeStack enablement is shown below
We implement [Ariane design with 136 macros](../../../Testcases/ariane136) on the [SKY130HD](../../../Enablements/SKY130HD) platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R).
We implement [Ariane design with 136 macros](../../../Testcases/ariane136) on the [SKY130HD FakeStack](../../../Enablements/SKY130HD) platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R).
The screenshot of the design using Cadence Flow-1 on SKY130HD enablement is shown below
The screenshot of the design using Cadence Flow-1 on SKY130HD FakeStack enablement is shown below
We implement [Mempool tile](../../../Testcases/mempool) on the [SKY130HD](../../../Enablements/SKY130HD) platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R).
We implement [Mempool tile](../../../Testcases/mempool) on the [SKY130HD FakeStack](../../../Enablements/SKY130HD) platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R).
The screenshot of the design using Cadence Flow-1 on SKY130HD enablement is shown below
The screenshot of the design using Cadence Flow-1 on SKY130HD FakeStack enablement is shown below
We implement [NVDLA](../../../Testcases/nvdla) on the [SKY130HD](../../../Enablements/SKY130HD) platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R).
We implement [NVDLA](../../../Testcases/nvdla) on the [SKY130HD FakeStack](../../../Enablements/SKY130HD) platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R).
The screenshot of the design using Cadence Flow-1 on SKY130HD enablement is shown below. The 256x64 SRAM memory dimension is weird. This is the memory we have generated using the [bsg_fakeram](https://github.com/jjcherry56/bsg_fakeram) memory compiler.
The screenshot of the design using Cadence Flow-1 on SKY130HD FakeStack enablement is shown below. The 256x64 SRAM memory dimension is weird. This is the memory we have generated using the [bsg_fakeram](https://github.com/jjcherry56/bsg_fakeram) memory compiler.
This directory contains three types of scripts: (1) TCL scripts, (2) Python scripts and (3) Shell scripts, as detailed below:
- TCL Scripts:
-[extract_report.tcl](./extract_report.tcl): Contains procedure to extract metrics (i.e., Core Area, Standard Cell Area, Macro Area, Total Power, Wire Length, WNS, TNS, Congestion) at different stages of P&R in the Innovus shell. First source this file in the Innovus shell and then you can use the following commands:
-[extract_report.tcl](./extract_report.tcl): Contains procedure to extract metrics (e.g., Core Area, Standard Cell Area, Macro Area, Total Power, Wire Length, WNS, TNS, Congestion) at different stages of P&R in the Innovus shell. First source this file in the Innovus shell and then you can use the following commands:
-*extract_report preCTS*: Use this command to extract metric after running the *place_opt_design* command.
-*extract_report postCTS*: Use this command to extract metric after running the *ccopt_design* command.
-*extract_report postRoute*: Use this command to extract metric after running the *routeDesing* or *opt_desing -postRoute* command.
-[gen_pb.tcl](./gen_pb.tcl): Contains procedure to write out flat netlist in protocol buffer format in Innovus shell. First source this file in the Innovus shell and then use gen_pb_netlist.
-[gen_pb.tcl](./gen_pb.tcl): Contains procedure to write out a flat netlist in the [protocol buffer](https://github.com/google-research/circuit_training/blob/main/docs/NETLIST_FORMAT.md) format in the Innovus shell. First source this file in the Innovus shell and then use the *gen_pb_netlist* command.
-*gen_pb_netlist*: This command writes out the flat netlist in the protobuf format. The output file name is \<top design\>.pb.txt.
-[pdn_flow.tcl](./pdn_flow.tcl): This script generates the power delivery network (PDN) for Innovus implementation. It uses the PDN configuration file available in the [*./Enablements/\**](../../Enablements/) directory.
-[pdn_flow.tcl](./pdn_flow.tcl): This script generates the power delivery network (PDN) for the Innovus implementation. It uses the following PDN configuration file available in the [*./Enablements/\**](../../Enablements/) directory.
-[place_pin.tcl](./place_pin.tcl): This script places all the toplevel design ports on the left boundary. Pins are spreaded over 65\% length around the center of the left boundary.
-[place_pin.tcl](./place_pin.tcl): This script places all the top-level design ports on the left boundary. Pins are spreaded over 65\% length around the center of the left boundary.
-[write_required_def.tcl](./write_required_def.tcl): This script writes out the def and netlist files from the Innovus shell. We use these def and netlist files as inputs to CodeElement to generate the clustered netlist.
- Python Scripts:
-[flow.py](./flow.py): This script runs gridding, grouping and clustering to generate the clustered netlist. It requires two inputs:
