Version abc90424

abclib.dsp

@@ -2959,6 +2959,10 @@ SOURCE=.\src\aig\aig\aigDup.c
 # End Source File
 # Begin Source File
 
+SOURCE=.\src\aig\aig\aigFact.c
+# End Source File
+# Begin Source File
+
 SOURCE=.\src\aig\aig\aigFanout.c
 # End Source File
 # Begin Source File

src/aig/aig/aigFact.c

+/**CFile****************************************************************
+
+  FileName    [aigFactor.c]
+
+  SystemName  []
+
+  PackageName []
+
+  Synopsis    []
+
+  Author      [Alan Mishchenko]
+  
+  Affiliation []
+
+  Date        [Ver. 1.0. Started - April 17, 2009.]
+
+  Revision    [$Id: aigFactor.c,v 1.00 2009/04/17 00:00:00 alanmi Exp $]
+
+***********************************************************************/
+
+#include "aig.h"
+
+////////////////////////////////////////////////////////////////////////
+///                        DECLARATIONS                              ///
+////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////
+///                     FUNCTION DEFINITIONS                         ///
+////////////////////////////////////////////////////////////////////////
+
+/**Function*************************************************************
+
+  Synopsis    [Detects multi-input AND gate rooted at this node.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Aig_ManFindImplications_rec( Aig_Obj_t * pObj, Vec_Ptr_t * vImplics )
+{
+    if ( Aig_IsComplement(pObj) || Aig_ObjIsPi(pObj) )
+    {
+        Vec_PtrPushUnique( vImplics, pObj );
+        return;
+    }
+    Aig_ManFindImplications_rec( Aig_ObjChild0(pObj), vImplics );
+    Aig_ManFindImplications_rec( Aig_ObjChild1(pObj), vImplics );
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Returns the nodes whose values are implied by pNode.]
+
+  Description [Attention!  Both pNode and results can be complemented!
+  Also important: Currently, this procedure only does backward propagation. 
+  In general, it may find more implications if forward propagation is enabled.]
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Vec_Ptr_t * Aig_ManFindImplications( Aig_Man_t * p, Aig_Obj_t * pNode )
+{
+    Vec_Ptr_t * vImplics;
+    vImplics = Vec_PtrAlloc( 100 );
+    Aig_ManFindImplications_rec( pNode, vImplics );
+    return vImplics;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Returns 1 if the cone of the node overlaps with the vector.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Aig_ManFindConeOverlap_rec( Aig_Man_t * p, Aig_Obj_t * pNode )
+{
+    if ( Aig_ObjIsTravIdPrevious( p, pNode ) )
+        return 1;
+    if ( Aig_ObjIsTravIdCurrent( p, pNode ) )
+        return 0;
+    Aig_ObjSetTravIdCurrent( p, pNode );
+    if ( Aig_ObjIsPi(pNode) )
+        return 0;
+    if ( Aig_ManFindConeOverlap_rec( p, Aig_ObjFanin0(pNode) ) )
+        return 1;
+    if ( Aig_ManFindConeOverlap_rec( p, Aig_ObjFanin1(pNode) ) )
+        return 1;
+    return 0;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Returns 1 if the cone of the node overlaps with the vector.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Aig_ManFindConeOverlap( Aig_Man_t * p, Vec_Ptr_t * vImplics, Aig_Obj_t * pNode )
+{
+    Aig_Obj_t * pTemp;
+    int i;
+    assert( !Aig_IsComplement(pNode) );
+    assert( !Aig_ObjIsConst1(pNode) );
+    Aig_ManIncrementTravId( p );
+    Vec_PtrForEachEntry( vImplics, pTemp, i )
+        Aig_ObjSetTravIdCurrent( p, Aig_Regular(pTemp) );
+    Aig_ManIncrementTravId( p );
+    return Aig_ManFindConeOverlap_rec( p, pNode );
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Returns 1 if the cone of the node overlaps with the vector.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Aig_Obj_t * Aig_ManDeriveNewCone_rec( Aig_Man_t * p, Aig_Obj_t * pNode )
+{
+    if ( Aig_ObjIsTravIdCurrent( p, pNode ) )
+        return pNode->pData;
+    Aig_ObjSetTravIdCurrent( p, pNode );
+    if ( Aig_ObjIsPi(pNode) )
+        return pNode->pData = pNode;
+    Aig_ManDeriveNewCone_rec( p, Aig_ObjFanin0(pNode) );
+    Aig_ManDeriveNewCone_rec( p, Aig_ObjFanin1(pNode) );
+    return pNode->pData = Aig_And( p, Aig_ObjChild0Copy(pNode), Aig_ObjChild1Copy(pNode) );
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Returns 1 if the cone of the node overlaps with the vector.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Aig_Obj_t * Aig_ManDeriveNewCone( Aig_Man_t * p, Vec_Ptr_t * vImplics, Aig_Obj_t * pNode )
+{
+    Aig_Obj_t * pTemp;
+    int i;
+    assert( !Aig_IsComplement(pNode) );
+    assert( !Aig_ObjIsConst1(pNode) );
+    Aig_ManIncrementTravId( p );
+    Vec_PtrForEachEntry( vImplics, pTemp, i )
+    {
+        Aig_ObjSetTravIdCurrent( p, Aig_Regular(pTemp) );
+        Aig_Regular(pTemp)->pData = Aig_NotCond( Aig_ManConst1(p), Aig_IsComplement(pTemp) );
+    }
+    return Aig_ManDeriveNewCone_rec( p, pNode );
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Returns algebraic factoring of B in terms of A.]
+
+  Description [Returns internal node C (an AND gate) that is equal to B 
+  under assignment A = 'Value', or NULL if there is no such node C. ]
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Aig_Obj_t * Aig_ManFactorAlgebraic_int( Aig_Man_t * p, Aig_Obj_t * pPoA, Aig_Obj_t * pPoB, int Value )
+{
+    Aig_Obj_t * pNodeA, * pNodeC;
+    Vec_Ptr_t * vImplics;
+    int RetValue;
+    if ( Aig_ObjIsConst1(Aig_ObjFanin0(pPoA)) || Aig_ObjIsConst1(Aig_ObjFanin0(pPoB)) )
+        return NULL;
+    if ( Aig_ObjIsPi(Aig_ObjFanin0(pPoB)) )
+        return NULL;
+    // get the internal node representing function of A under assignment A = 'Value'
+    pNodeA = Aig_ObjChild0( pPoA );
+    pNodeA = Aig_NotCond( pNodeA, Value==0 );
+    // find implications of this signal (nodes whose value is fixed under assignment A = 'Value')
+    vImplics = Aig_ManFindImplications( p, pNodeA );
+    // check if the TFI cone of B overlaps with the implied nodes
+    RetValue = Aig_ManFindConeOverlap( p, vImplics, Aig_ObjFanin0(pPoB) );
+    if ( RetValue == 0 ) // no overlap
+    {
+        Vec_PtrFree( vImplics );
+        return NULL;
+    }
+    // there is overlap - derive node representing value of B under assignment A = 'Value'
+    pNodeC = Aig_ManDeriveNewCone( p, vImplics, Aig_ObjFanin0(pPoB) );
+    pNodeC = Aig_NotCond( pNodeC, Aig_ObjFaninC0(pPoB) );
+    Vec_PtrFree( vImplics );
+    return pNodeC;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Returns algebraic factoring of B in terms of A.]
+
+  Description [Returns internal node C (an AND gate) that is equal to B 
+  under assignment A = 'Value', or NULL if there is no such node C. ]
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Aig_Obj_t * Aig_ManFactorAlgebraic( Aig_Man_t * p, int iPoA, int iPoB, int Value )
+{
+    assert( iPoA >= 0 && iPoA < Aig_ManPoNum(p) );
+    assert( iPoB >= 0 && iPoB < Aig_ManPoNum(p) );
+    assert( Value == 0 || Value == 1 );
+    return Aig_ManFactorAlgebraic_int( p, Aig_ManPo(p, iPoA), Aig_ManPo(p, iPoB), Value ); 
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Testing procedure.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Aig_ManFactorAlgebraicTest( Aig_Man_t * p )
+{
+    int iPoA  = 0;
+    int iPoB  = 1;
+    int Value = 0;
+    Aig_Obj_t * pRes;
+//    Aig_Obj_t * pObj;
+//    int i;
+    pRes = Aig_ManFactorAlgebraic( p, iPoA, iPoB, Value );
+    Aig_ManShow( p, 0, NULL );
+    Aig_ObjPrint( p, pRes );
+    printf( "\n" );
+/*
+    printf( "Results:\n" );
+    Aig_ManForEachObj( p, pObj, i )
+    {
+        printf( "Object = %d.\n", i );
+        Aig_ObjPrint( p, pObj );
+        printf( "\n" );
+        Aig_ObjPrint( p, pObj->pData );
+        printf( "\n" );
+    }
+*/
+}
+
+////////////////////////////////////////////////////////////////////////
+///                       END OF FILE                                ///
+////////////////////////////////////////////////////////////////////////

src/aig/aig/aigObj.c

@@ -313,6 +313,16 @@ void Aig_ObjPrint( Aig_Man_t * p, Aig_Obj_t * pObj )
     int fHaig = 0;
     int fShowFanouts = 0;
     Aig_Obj_t * pTemp;
+    if ( pObj == NULL )
+    {
+        printf( "Object is NULL." );
+        return;
+    }
+    if ( Aig_IsComplement(pObj) )
+    {
+        printf( "Compl " );
+        pObj = Aig_Not(pObj);
+    }
     assert( !Aig_IsComplement(pObj) );
     printf( "Node %4d : ", Aig_ObjId(pObj) );
     if ( Aig_ObjIsConst1(pObj) )

src/aig/bbl/bblif.h

@@ -36,6 +36,14 @@
     (3) read a binary BLIF file with a mapped network produced by ABC
     (4) return the mapped network to the caller through a set of APIs
 
+    It should be noted that the BBLIF interface can be used to pass
+    the network from the calling application into ABC without writing it
+    into a file. In this case, ABC should be compiled as a library and
+    linked to the calling application. The BBLIF manager can be given
+    directly to the procedure Bbl_ManToAbc() to convert it into an AIG.
+    Similarly, the resulting mapped network can be converted into
+    BBLIF manager and passed back after the call to Bbl_ManFromAbc().
+
     Here these steps are described in more detail:
 
     (1) The BBLIF manager is allocated by calling Bbl_ManStart() and 

src/aig/cec/cec.h

@@ -122,6 +122,7 @@ struct Cec_ParCor_t_
     int              nWords;        // the number of simulation words
     int              nRounds;       // the number of simulation rounds
     int              nFrames;       // the number of time frames
+    int              nPrefix;       // the number of time frames in the prefix
     int              nBTLimit;      // conflict limit at a node
     int              fLatchCorr;    // consider only latch outputs
     int              fUseRings;     // use rings

src/aig/cec/cecCec.c

@@ -236,6 +236,33 @@ int Cec_ManVerifyTwoAigs( Aig_Man_t * pAig0, Aig_Man_t * pAig1, int fVerbose )
     return RetValue;
 }
 
+/**Function*************************************************************
+
+  Synopsis    [Implementation of new signal correspodence.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Aig_Man_t * Cec_SignalCorrespondence( Aig_Man_t * pAig, int nConfs, int fUseCSat )
+{
+    extern int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars );
+    Gia_Man_t * pGia;
+    Cec_ParCor_t CorPars, * pCorPars = &CorPars;
+    Cec_ManCorSetDefaultParams( pCorPars );
+    pCorPars->fUseCSat  = fUseCSat;
+    pCorPars->nBTLimit  = nConfs;
+    pGia = Gia_ManFromAigSimple( pAig );
+    Cec_ManLSCorrespondenceClasses( pGia, pCorPars );
+    Gia_ManReprToAigRepr( pAig, pGia );
+    Gia_ManStop( pGia );
+    return Aig_ManDupSimple( pAig );
+}
+
+
 ////////////////////////////////////////////////////////////////////////
 ///                       END OF FILE                                ///
 ////////////////////////////////////////////////////////////////////////

src/aig/cec/cecClass.c

@@ -712,6 +712,8 @@ int Cec_ManSimSimulateRound( Cec_ManSim_t * p, Vec_Ptr_t * vInfoCis, Vec_Ptr_t *
         pRes0 = Cec_ManSimSimDeref( p, Gia_ObjFaninId0(pObj,i) );
         pRes1 = Cec_ManSimSimDeref( p, Gia_ObjFaninId1(pObj,i) );
 
+//        printf( "%d,%d  ", Gia_ObjValue( Gia_ObjFanin0(pObj) ), Gia_ObjValue( Gia_ObjFanin1(pObj) ) );
+
         if ( Gia_ObjFaninC0(pObj) )
         {
             if ( Gia_ObjFaninC1(pObj) )

src/aig/cec/cecSolve.c

@@ -823,13 +823,13 @@ Vec_Int_t * Cec_ManSatSolveMiter( Gia_Man_t * pAig, Cec_ParSat_t * pPars, Vec_St
         {
             if ( Gia_ObjFaninC0(pObj) )
             {
-                printf( "Constant 1 output of SRM!!!\n" );
+//                printf( "Constant 1 output of SRM!!!\n" );
                 Cec_ManSatAddToStore( vCexStore, p->vCex, i ); // trivial counter-example
                 Vec_StrPush( vStatus, 0 );
             }
             else
             {
-                printf( "Constant 0 output of SRM!!!\n" );
+//                printf( "Constant 0 output of SRM!!!\n" );
                 Vec_StrPush( vStatus, 1 );
             }
             continue;

src/aig/dar/darCut.c

@@ -627,6 +627,7 @@ void Dar_ManCutsRestart( Dar_Man_t * p, Aig_Obj_t * pRoot )
 {
     Aig_Obj_t * pObj;
     int i;
+    Dar_ObjSetCuts( Aig_ManConst1(p->pAig), NULL );
     Vec_PtrForEachEntry( p->vCutNodes, pObj, i )
         if ( !Aig_ObjIsNone(pObj) )
             Dar_ObjSetCuts( pObj, NULL );

src/aig/dar/darLib.c

@@ -813,6 +813,12 @@ void Dar_LibEvalAssignNums( Dar_Man_t * p, int Class, Aig_Obj_t * pRoot )
             pData->Level = Aig_Regular(pData->pFunc)->Level;
             // mark the node if it is part of MFFC
             pData->fMffc = Aig_ObjIsTravIdCurrent(p->pAig, Aig_Regular(pData->pFunc));
+            // assign the probability
+            if ( p->pPars->fPower )
+            {
+                float Prob = Aig_Int2Float( Vec_IntEntry( p->pAig->vProbs, Aig_ObjId(Aig_Regular(pData->pFunc)) ) );
+                pData->dProb = Aig_IsComplement(pData->pFunc)? 1.0-Prob : Prob;
+            }
         }
     }
 }
@@ -830,22 +836,30 @@ void Dar_LibEvalAssignNums( Dar_Man_t * p, int Class, Aig_Obj_t * pRoot )
 ***********************************************************************/
 int Dar_LibEval_rec( Dar_LibObj_t * pObj, int Out, int nNodesSaved, int Required, float * pPower )
 {
-    float Power0, Power1;
     Dar_LibDat_t * pData;
+    float Power0, Power1;
     int Area;
     if ( pPower )
         *pPower = (float)0.0;
+    pData = s_DarLib->pDatas + pObj->Num;
+    if ( pData->TravId == Out )
+        return 0;
+    pData->TravId = Out;
     if ( pObj->fTerm )
+    {
+        if ( pPower )
+            *pPower = pData->dProb;
         return 0;
+    }
     assert( pObj->Num > 3 );
-    pData = s_DarLib->pDatas + pObj->Num;
     if ( pData->Level > Required )
         return 0xff;
     if ( pData->pFunc && !pData->fMffc )
+    {
+        if ( pPower )
+            *pPower = pData->dProb;
         return 0;
-    if ( pData->TravId == Out )
-        return 0;
-    pData->TravId = Out;
+    }
     // this is a new node - get a bound on the area of its branches
     nNodesSaved--;
     Area = Dar_LibEval_rec( Dar_LibObj(s_DarLib, pObj->Fan0), Out, nNodesSaved, Required+1, pPower? &Power0 : NULL );

src/aig/gia/gia.h

@@ -513,6 +513,7 @@ extern Gia_Man_t *         Gia_ManDupOrderDfs( Gia_Man_t * p );
 extern Gia_Man_t *         Gia_ManDupOrderDfsReverse( Gia_Man_t * p );
 extern Gia_Man_t *         Gia_ManDupOrderAiger( Gia_Man_t * p );
 
+extern Gia_Man_t *         Gia_ManDupFlip( Gia_Man_t * p, int * pInitState );
 extern Gia_Man_t *         Gia_ManDup( Gia_Man_t * p );  
 extern Gia_Man_t *         Gia_ManDupSelf( Gia_Man_t * p );
 extern Gia_Man_t *         Gia_ManDupFlopClass( Gia_Man_t * p, int iClass );

src/aig/gia/giaAig.c

@@ -105,6 +105,46 @@ Gia_Man_t * Gia_ManFromAig( Aig_Man_t * p )
 
 /**Function*************************************************************
 
+  Synopsis    [Duplicates AIG in the DFS order.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Gia_Man_t * Gia_ManFromAigSimple( Aig_Man_t * p )
+{
+    Gia_Man_t * pNew;
+    Aig_Obj_t * pObj;
+    int i;
+    // create the new manager
+    pNew = Gia_ManStart( Aig_ManObjNum(p) );
+    pNew->pName = Gia_UtilStrsav( p->pName );
+    // create the PIs
+    Aig_ManCleanData( p );
+    Aig_ManForEachObj( p, pObj, i )
+    {
+        if ( Aig_ObjIsAnd(pObj) )
+            pObj->iData = Gia_ManAppendAnd( pNew, Gia_ObjChild0Copy(pObj), Gia_ObjChild1Copy(pObj) );
+        else if ( Aig_ObjIsPi(pObj) )
+            pObj->iData = Gia_ManAppendCi( pNew );
+        else if ( Aig_ObjIsPo(pObj) )
+            pObj->iData = Gia_ManAppendCo( pNew, Gia_ObjChild0Copy(pObj) );
+        else if ( Aig_ObjIsConst1(pObj) )
+            pObj->iData = 1;
+        else
+            assert( 0 );
+    }
+    Gia_ManSetRegNum( pNew, Aig_ManRegNum(p) );
+    if ( pNew->pNexts )
+        Gia_ManDeriveReprs( pNew );
+    return pNew;
+}
+
+/**Function*************************************************************
+
   Synopsis    [Handles choices as additional combinational outputs.]
 
   Description []
@@ -243,6 +283,43 @@ Aig_Man_t * Gia_ManCofactorAig( Aig_Man_t * p, int nFrames, int nCofFanLit )
     return pMan;
 }
 
+
+/**Function*************************************************************
+
+  Synopsis    [Transfers representatives from pGia to pAig.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Gia_ManReprToAigRepr( Aig_Man_t * p, Gia_Man_t * pGia )
+{
+    Aig_Obj_t * pObj;
+    Gia_Obj_t * pGiaObj, * pGiaRepr;
+    int i;
+    assert( p->pReprs == NULL );
+    assert( pGia->pReprs != NULL );
+    // move pointers from AIG to GIA
+    Aig_ManForEachObj( p, pObj, i )
+    {
+        assert( i == 0 || !Gia_LitIsCompl(pObj->iData) );
+        pGiaObj = Gia_ManObj( pGia, Gia_Lit2Var(pObj->iData) );
+        pGiaObj->Value = i;
+    }
+    // set the pointers to the nodes in AIG
+    Aig_ManReprStart( p, Aig_ManObjNumMax(p) );
+    Gia_ManForEachObj( pGia, pGiaObj, i )
+    {
+        pGiaRepr = Gia_ObjReprObj( pGia, i );
+        if ( pGiaRepr == NULL )
+            continue;
+        Aig_ObjCreateRepr( p, Aig_ManObj(p, pGiaRepr->Value), Aig_ManObj(p, pGiaObj->Value) );
+    }
+}
+
 ////////////////////////////////////////////////////////////////////////
 ///                       END OF FILE                                ///
 ////////////////////////////////////////////////////////////////////////

src/aig/gia/giaAig.h

@@ -47,8 +47,10 @@
 
 /*=== giaAig.c =============================================================*/
 extern Gia_Man_t *         Gia_ManFromAig( Aig_Man_t * p );
+extern Gia_Man_t *         Gia_ManFromAigSimple( Aig_Man_t * p );
 extern Gia_Man_t *         Gia_ManFromAigSwitch( Aig_Man_t * p );
 extern Aig_Man_t *         Gia_ManToAig( Gia_Man_t * p, int fChoices );
+extern void                Gia_ManReprToAigRepr( Aig_Man_t * p, Gia_Man_t * pGia );
  
 #ifdef __cplusplus
 }

src/aig/gia/giaCSat.c

@@ -473,6 +473,8 @@ static inline void Cbs_ManCancelUntil( Cbs_Man_t * p, int iBound )
     Vec_IntShrink( p->vLevReas, 3*iBound );
 }
 
+int s_Counter = 0;
+
 /**Function*************************************************************
 
   Synopsis    [Assigns the variables a value.]
@@ -498,6 +500,7 @@ static inline void Cbs_ManAssign( Cbs_Man_t * p, Gia_Obj_t * pObj, int Level, Gi
     Vec_IntPush( p->vLevReas, pRes0 ? pRes0-pObjR : 0 );
     Vec_IntPush( p->vLevReas, pRes1 ? pRes1-pObjR : 0 );
     assert( Vec_IntSize(p->vLevReas) == 3 * p->pProp.iTail );
+    s_Counter++;
 }
 
 
@@ -925,6 +928,7 @@ int Cbs_ManSolve_rec( Cbs_Man_t * p, int Level )
 int Cbs_ManSolve( Cbs_Man_t * p, Gia_Obj_t * pObj )
 {
     int RetValue = 0;
+    s_Counter = 0;
     assert( !p->pProp.iHead && !p->pProp.iTail );
     assert( !p->pJust.iHead && !p->pJust.iTail );
     assert( p->pClauses.iHead == 1 && p->pClauses.iTail == 1 );
@@ -941,6 +945,8 @@ int Cbs_ManSolve( Cbs_Man_t * p, Gia_Obj_t * pObj )
     p->Pars.nJustTotal = ABC_MAX( p->Pars.nJustTotal, p->Pars.nJustThis );
     if ( Cbs_ManCheckLimits( p ) )
         RetValue = -1;
+
+//    printf( "%d ", s_Counter );
     return RetValue;
 }
 
@@ -1019,7 +1025,7 @@ Vec_Int_t * Cbs_ManSolveMiterNc( Gia_Man_t * pAig, int nConfs, Vec_Str_t ** pvSt
         {
             if ( Gia_ObjFaninC0(pRoot) )
             {
-                printf( "Constant 1 output of SRM!!!\n" );
+//                printf( "Constant 1 output of SRM!!!\n" );
                 Cec_ManSatAddToStore( vCexStore, vCex, i ); // trivial counter-example
                 Vec_StrPush( vStatus, 0 );
             }

src/aig/gia/giaDup.c

@@ -246,6 +246,47 @@ Gia_Man_t * Gia_ManDupOrderAiger( Gia_Man_t * p )
     return pNew;
 }
 
+/**Function*************************************************************
+
+  Synopsis    [Duplicates AIG while complementing the flops.]
+
+  Description [The array of initial state contains the init state
+  for each state bit of the flops in the design.]
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Gia_Man_t * Gia_ManDupFlip( Gia_Man_t * p, int * pInitState )
+{
+    Gia_Man_t * pNew;
+    Gia_Obj_t * pObj;
+    int i;
+    pNew = Gia_ManStart( Gia_ManObjNum(p) );
+    pNew->pName = Gia_UtilStrsav( p->pName );
+    Gia_ManConst0(p)->Value = 0;
+    Gia_ManForEachObj1( p, pObj, i )
+    {
+        if ( Gia_ObjIsAnd(pObj) )
+            pObj->Value = Gia_ManAppendAnd( pNew, Gia_ObjFanin0Copy(pObj), Gia_ObjFanin1Copy(pObj) );
+        else if ( Gia_ObjIsCi(pObj) )
+        {
+            pObj->Value = Gia_ManAppendCi( pNew );
+            if ( Gia_ObjCioId(pObj) >= Gia_ManPiNum(p) )
+                pObj->Value = Gia_LitNotCond( pObj->Value, Gia_InfoHasBit(pInitState, Gia_ObjCioId(pObj) - Gia_ManPiNum(p)) );
+        }
+        else if ( Gia_ObjIsCo(pObj) )
+        {
+            pObj->Value = Gia_ObjFanin0Copy(pObj);
+            if ( Gia_ObjCioId(pObj) >= Gia_ManPoNum(p) )
+                pObj->Value = Gia_LitNotCond( pObj->Value, Gia_InfoHasBit(pInitState, Gia_ObjCioId(pObj) - Gia_ManPoNum(p)) );
+            pObj->Value = Gia_ManAppendCo( pNew, pObj->Value );
+        }
+    }
+    Gia_ManSetRegNum( pNew, Gia_ManRegNum(p) );
+    return pNew;
+}
 
 
 /**Function*************************************************************

src/aig/ntl/ntl.h

@@ -162,9 +162,10 @@ struct Ntl_Net_t_
         int            iTemp;          // other data
     };
     Ntl_Obj_t *        pDriver;        // driver of the net
-    int                NetId;          // unique ID of the net
-    char               nVisits;        // the number of times the net is visited
-    char               fMark;          // temporary mark
+    unsigned           NetId     : 28; // unique ID of the net
+    unsigned           nVisits   :  2; // the number of times the net is visted
+    unsigned           fMark     :  1; // temporary mark
+    unsigned           fFixed    :  1; // the fixed net
     char               pName[0];       // the name of this net
 };
 
@@ -392,6 +393,7 @@ extern ABC_DLL int             Ntl_ModelSeqLeafNum( Ntl_Mod_t * p );
 extern ABC_DLL int             Ntl_ModelSeqRootNum( Ntl_Mod_t * p );
 extern ABC_DLL int             Ntl_ModelCheckNetsAreNotMarked( Ntl_Mod_t * pModel );
 extern ABC_DLL void            Ntl_ModelClearNets( Ntl_Mod_t * pModel );
+extern ABC_DLL void            Ntl_ManRemoveUselessNets( Ntl_Man_t * p );
 
 #ifdef __cplusplus
 }

src/aig/ntl/ntlFraig.c

@@ -422,6 +422,8 @@ Ntl_Man_t * Ntl_ManScl( Ntl_Man_t * p, int fLatchConst, int fLatchEqual, int fVe
 
     // collapse the AIG
     pAig = Ntl_ManExtract( p );
+//Ntl_ManPrintStats( p );
+//Aig_ManPrintStats( pAig );
     pNew = Ntl_ManInsertAig( p, pAig );
     pAigCol = Ntl_ManCollapseSeq( pNew, 0 );
     if ( pAigCol == NULL )
@@ -429,6 +431,8 @@ Ntl_Man_t * Ntl_ManScl( Ntl_Man_t * p, int fLatchConst, int fLatchEqual, int fVe
         Aig_ManStop( pAig );
         return pNew;
     }
+//Ntl_ManPrintStats( pNew );
+//Aig_ManPrintStats( pAigCol );
 
     // perform SCL for the given design
     pTemp = Aig_ManScl( pAigCol, fLatchConst, fLatchEqual, fVerbose );

src/aig/ntl/ntlInsert.c

@@ -245,6 +245,42 @@ Ntl_Man_t * Ntl_ManInsertAig( Ntl_Man_t * p, Aig_Man_t * pAig )
 
 /**Function*************************************************************
 
+  Synopsis    [Find drivers of the given net.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Ntl_ManFindDriver( Ntl_Man_t * p, char * pName )
+{
+    Ntl_Mod_t * pRoot;
+    Ntl_Obj_t * pNode;
+    Ntl_Net_t * pNet, * pNetThis;
+    int i, k;
+    pRoot = Ntl_ManRootModel( p );
+    pNetThis = Ntl_ModelFindNet( pRoot, pName );
+    printf( "\n*** Net %d \"%s\":\n", pNetThis->NetId, pName );
+    // mark from the nodes
+    Ntl_ModelForEachPo( pRoot, pNode, i )
+        if ( pNetThis == Ntl_ObjFanin0(pNode) )
+            printf( "driven by PO %d\n", i );
+    Ntl_ModelForEachNode( pRoot, pNode, i )
+        Ntl_ObjForEachFanin( pNode, pNet, k )
+            if ( pNetThis == pNet )
+                printf( "driven by node %d with %d fanins and %d fanouts\n (%s)\n", 
+                    pNode->Id, Ntl_ObjFaninNum(pNode), Ntl_ObjFanoutNum(pNode), Ntl_ObjFanout(pNode,0)->pName );
+    Ntl_ModelForEachBox( pRoot, pNode, i )
+        Ntl_ObjForEachFanin( pNode, pNet, k )
+            if ( pNetThis == pNet )
+                printf( "driven by box %d with %d fanins and %d fanouts\n (%s)\n", 
+                    pNode->Id, Ntl_ObjFaninNum(pNode), Ntl_ObjFanoutNum(pNode), Ntl_ObjFanout(pNode,0)->pName );
+}
+
+/**Function*************************************************************
+
   Synopsis    [Inserts the given mapping into the netlist.]
 
   Description []

src/aig/ntl/ntlMan.c

@@ -460,6 +460,8 @@ Ntl_Mod_t * Ntl_ModelStartFrom( Ntl_Man_t * pManNew, Ntl_Mod_t * pModelOld )
         }
         else
             pNet->pCopy = NULL;
+        if ( pNet->pCopy )
+            ((Ntl_Net_t *)pNet->pCopy)->fFixed = pNet->fFixed;
     }
     Ntl_ModelForEachObj( pModelOld, pObj, i )
     {
@@ -511,6 +513,7 @@ Ntl_Mod_t * Ntl_ModelDup( Ntl_Man_t * pManNew, Ntl_Mod_t * pModelOld )
     Ntl_ModelForEachNet( pModelOld, pNet, i )
     {
         pNet->pCopy = Ntl_ModelFindOrCreateNet( pModelNew, pNet->pName );
+        ((Ntl_Net_t *)pNet->pCopy)->fFixed = pNet->fFixed;
         if ( pNet->pDriver == NULL )
         {
             assert( !pModelOld->attrWhite );

src/aig/ntl/ntlUtil.c

@@ -657,6 +657,68 @@ void Ntl_ModelClearNets( Ntl_Mod_t * pModel )
     }
 }
 
+/**Function*************************************************************
+
+  Synopsis    [Removes nets without fanins and fanouts.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Ntl_ManRemoveUselessNets( Ntl_Man_t * p )
+{
+    Ntl_Mod_t * pRoot;
+    Ntl_Obj_t * pNode;
+    Ntl_Net_t * pNet;
+    int i, k, Counter;
+    pRoot = Ntl_ManRootModel( p );
+    Ntl_ModelForEachNet( pRoot, pNet, i )
+        pNet->fMark = 0;
+    Ntl_ModelForEachPi( pRoot, pNode, i )
+    {
+        pNet = Ntl_ObjFanout0(pNode);
+        pNet->fMark = 1;
+    }
+    Ntl_ModelForEachPo( pRoot, pNode, i )
+    {
+        pNet = Ntl_ObjFanin0(pNode);
+        pNet->fMark = 1;
+    }
+    Ntl_ModelForEachNode( pRoot, pNode, i )
+    {
+        Ntl_ObjForEachFanin( pNode, pNet, k )
+            pNet->fMark = 1;
+        Ntl_ObjForEachFanout( pNode, pNet, k )
+            pNet->fMark = 1;
+    }
+    Ntl_ModelForEachBox( pRoot, pNode, i )
+    {
+        Ntl_ObjForEachFanin( pNode, pNet, k )
+            pNet->fMark = 1;
+        Ntl_ObjForEachFanout( pNode, pNet, k )
+            pNet->fMark = 1;
+    }
+    Counter = 0;
+    Ntl_ModelForEachNet( pRoot, pNet, i )
+    {
+        if ( pNet->fMark )
+        {
+            pNet->fMark = 0;
+            continue;
+        }
+        if ( pNet->fFixed )
+            continue;
+        Ntl_ModelDeleteNet( pRoot, pNet );
+        Vec_PtrWriteEntry( pRoot->vNets, pNet->NetId, NULL );
+        Counter++;
+    }
+    if ( Counter )
+        printf( "Deleted %d nets without fanins/fanouts.\n", Counter );
+}
+
 ////////////////////////////////////////////////////////////////////////
 ///                       END OF FILE                                ///
 ////////////////////////////////////////////////////////////////////////

src/aig/nwk/nwkUtil.c

@@ -518,9 +518,21 @@ void Nwk_ManMinimumBase( Nwk_Man_t * pNtk, int fVerbose )
     Vec_Int_t * vTruth;
     Nwk_Obj_t * pObj;
     int i, Counter = 0;
+    Nwk_Obj_t * pNodeThis = pNtk->vObjs->pArray[72688];
+
     vTruth = Vec_IntAlloc( 1 << 16 );
     Nwk_ManForEachNode( pNtk, pObj, i )
+    {
+        if ( i == 641386 )
+        {
+            int x = 0;
+        }
         Counter += Nwk_ManMinimumBaseNode( pObj, vTruth, fVerbose );
+        if ( pNodeThis->nFanouts != 15 )
+        {
+            int s = 0;
+        }
+    }
     if ( fVerbose && Counter )
         printf( "Support minimization reduced support of %d nodes.\n", Counter );
     Vec_IntFree( vTruth );

src/aig/saig/saig.h

@@ -90,7 +90,7 @@ static inline Aig_Obj_t *  Saig_ObjLiToLo( Aig_Man_t * p, Aig_Obj_t * pObj )  {
 ////////////////////////////////////////////////////////////////////////
 
 /*=== sswAbs.c ==========================================================*/
-extern Aig_Man_t *       Saig_ManProofAbstraction( Aig_Man_t * p, int nFrames, int nConfMax, int fDynamic, int fExtend, int fSkipProof, int nFramesBmc, int nConfMaxBmc, int fVerbose );
+extern Aig_Man_t *       Saig_ManProofAbstraction( Aig_Man_t * p, int nFrames, int nConfMax, int fDynamic, int fExtend, int fSkipProof, int nFramesBmc, int nConfMaxBmc, int nRatio, int fVerbose );
 /*=== saigBmc.c ==========================================================*/
 extern int               Saig_ManBmcSimple( Aig_Man_t * pAig, int nFrames, int nSizeMax, int nBTLimit, int fRewrite, int fVerbose, int * piFrame, int nCofFanLit );
 extern void              Saig_BmcPerform( Aig_Man_t * pAig, int nFramesMax, int nNodesMax, int nConfMaxOne, int nConfMaxAll, int fVerbose );

src/aig/saig/saigAbs.c

@@ -765,7 +765,7 @@ Aig_Man_t * Saig_ManProofRefine( Aig_Man_t * p, Aig_Man_t * pAbs, Vec_Int_t * vF
   SeeAlso     []
  
 ***********************************************************************/
-Aig_Man_t * Saig_ManProofAbstraction( Aig_Man_t * p, int nFrames, int nConfMax, int fDynamic, int fExtend, int fSkipProof, int nFramesBmc, int nConfMaxBmc, int fVerbose )
+Aig_Man_t * Saig_ManProofAbstraction( Aig_Man_t * p, int nFrames, int nConfMax, int fDynamic, int fExtend, int fSkipProof, int nFramesBmc, int nConfMaxBmc, int nRatio, int fVerbose )
 {
     Aig_Man_t * pResult, * pTemp;
     Cnf_Dat_t * pCnf;
@@ -869,9 +869,13 @@ Aig_Man_t * Saig_ManProofAbstraction( Aig_Man_t * p, int nFrames, int nConfMax,
                 Aig_ManPrintStats( pResult );
             else
                 printf( " -----------------------------------------------------\n" );
+            if ( 100.0*(Aig_ManRegNum(p)-Aig_ManRegNum(pTemp))/Aig_ManRegNum(p) < 1.0*nRatio )
+            {
+                printf( "Refinements is stopped because flop reduction is less than %d%%\n", nRatio );
+                break;
+            }
         }
     }
-
     Vec_IntFree( vFlops );
     return pResult;
 }

src/aig/ssw/ssw.h

@@ -61,6 +61,8 @@ struct Ssw_Pars_t_
     int              fLocalSim;     // enable local simulation simulation
     int              fPartSigCorr;  // uses partial signal correspondence
     int              nIsleDist;     // extends islands by the given distance
+    int              fScorrGia;     // new signal correspondence implementation
+    int              fUseCSat;      // new SAT solver using when fScorrGia is selected
     int              fVerbose;      // verbose stats
     int              fFlopVerbose;  // verbose printout of redundant flops
     // optimized latch correspondence

src/aig/ssw/sswCore.c

@@ -277,6 +277,13 @@ Aig_Man_t * Ssw_SignalCorrespondence( Aig_Man_t * pAig, Ssw_Pars_t * pPars )
              || (pAig->vClockDoms && Vec_VecSize(pAig->vClockDoms) > 0)  )
             return Ssw_SignalCorrespondencePart( pAig, pPars );
     }
+
+    if ( pPars->fScorrGia )
+    {
+        extern Aig_Man_t * Cec_SignalCorrespondence( Aig_Man_t * pAig, int nConfs, int fUseCSat );
+        return Cec_SignalCorrespondence( pAig, pPars->nBTLimit, pPars->fUseCSat );
+    }
+
     // start the induction manager
     p = Ssw_ManCreate( pAig, pPars );
     // compute candidate equivalence classes

src/base/abc/abcNtk.c

@@ -1185,6 +1185,81 @@ void Abc_NtkMakeComb( Abc_Ntk_t * pNtk, int fRemoveLatches )
         fprintf( stdout, "Abc_NtkMakeComb(): Network check has failed.\n" );
 }
 
+/**Function*************************************************************
+
+  Synopsis    [Converts the network to sequential.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Abc_NtkMakeSeq( Abc_Ntk_t * pNtk, int nLatchesToAdd )
+{
+    Abc_Obj_t * pObjLi, * pObjLo, * pObj;
+    int i;
+    assert( Abc_NtkBoxNum(pNtk) == 0 );
+    if ( !Abc_NtkIsComb(pNtk) )
+    {
+        printf( "The network is a not a combinational one.\n" );
+        return;
+    }
+    if ( nLatchesToAdd >= Abc_NtkPiNum(pNtk) )
+    {
+        printf( "The number of latches is more or equal than the number of PIs.\n" );
+        return;
+    }
+    if ( nLatchesToAdd >= Abc_NtkPoNum(pNtk) )
+    {
+        printf( "The number of latches is more or equal than the number of POs.\n" );
+        return;
+    }
+
+    // move the last PIs to become CIs
+    Vec_PtrClear( pNtk->vPis );
+    Abc_NtkForEachCi( pNtk, pObj, i )
+    {
+        if ( i < Abc_NtkCiNum(pNtk) - nLatchesToAdd )
+        {
+            Vec_PtrPush( pNtk->vPis, pObj );
+            continue;
+        }
+        pObj->Type = ABC_OBJ_BO;
+        pNtk->nObjCounts[ABC_OBJ_PI]--;
+        pNtk->nObjCounts[ABC_OBJ_BO]++;
+    }
+
+    // move the last POs to become COs
+    Vec_PtrClear( pNtk->vPos );
+    Abc_NtkForEachCo( pNtk, pObj, i )
+    {
+        if ( i < Abc_NtkCoNum(pNtk) - nLatchesToAdd )
+        {
+            Vec_PtrPush( pNtk->vPos, pObj );
+            continue;
+        }
+        pObj->Type = ABC_OBJ_BI;
+        pNtk->nObjCounts[ABC_OBJ_PO]--;
+        pNtk->nObjCounts[ABC_OBJ_BI]++;
+    }
+
+    // create latches
+    for ( i = 0; i < nLatchesToAdd; i++ )
+    {
+        pObjLo = Abc_NtkCi( pNtk, Abc_NtkCiNum(pNtk) - nLatchesToAdd + i );
+        pObjLi = Abc_NtkCo( pNtk, Abc_NtkCoNum(pNtk) - nLatchesToAdd + i );
+        pObj = Abc_NtkCreateLatch( pNtk );
+        Abc_ObjAddFanin( pObj, pObjLi );
+        Abc_ObjAddFanin( pObjLo, pObj );
+        Abc_LatchSetInit0( pObj );
+    }
+
+    if ( !Abc_NtkCheck( pNtk ) )
+        fprintf( stdout, "Abc_NtkMakeSeq(): Network check has failed.\n" );
+}
+
 
 /**Function*************************************************************
 

src/base/abci/abcDar.c

@@ -1743,6 +1743,18 @@ int Abc_NtkDarProve( Abc_Ntk_t * pNtk, Fra_Sec_t * pSecPar )
         RetValue = Abc_NtkIvyProve( &pNtkComb, pParams );
         // transfer model if given
 //        pNtk->pModel = pNtkComb->pModel; pNtkComb->pModel = NULL;
+        if ( RetValue == 0  && (Abc_NtkLatchNum(pNtk) == 0) )
+        {
+            pNtk->pModel = pNtkComb->pModel; pNtkComb->pModel = NULL;
+            printf( "Networks are not equivalent.\n" );
+            ABC_PRT( "Time", clock() - clk );
+            if ( pSecPar->fReportSolution )
+            {
+                printf( "SOLUTION: FAIL       " );
+                ABC_PRT( "Time", clock() - clkTotal );
+            }
+            return RetValue;
+        }
         Abc_NtkDelete( pNtkComb );
         // return the result, if solved
         if ( RetValue == 1 )
@@ -2570,7 +2582,7 @@ ABC_PRT( "Time", clock() - clkTotal );
   SeeAlso     []
 
 ***********************************************************************/
-Abc_Ntk_t * Abc_NtkDarPBAbstraction( Abc_Ntk_t * pNtk, int nFramesMax, int nConfMax, int fDynamic, int fExtend, int fSkipProof, int nFramesBmc, int nConfMaxBmc, int fVerbose )
+Abc_Ntk_t * Abc_NtkDarPBAbstraction( Abc_Ntk_t * pNtk, int nFramesMax, int nConfMax, int fDynamic, int fExtend, int fSkipProof, int nFramesBmc, int nConfMaxBmc, int nRatio, int fVerbose )
 {
     Abc_Ntk_t * pNtkAig;
     Aig_Man_t * pMan, * pTemp;
@@ -2580,7 +2592,7 @@ Abc_Ntk_t * Abc_NtkDarPBAbstraction( Abc_Ntk_t * pNtk, int nFramesMax, int nConf
         return NULL;
 
     Aig_ManSetRegNum( pMan, pMan->nRegs );
-    pMan = Saig_ManProofAbstraction( pTemp = pMan, nFramesMax, nConfMax, fDynamic, fExtend, fSkipProof, nFramesBmc, nConfMaxBmc, fVerbose );
+    pMan = Saig_ManProofAbstraction( pTemp = pMan, nFramesMax, nConfMax, fDynamic, fExtend, fSkipProof, nFramesBmc, nConfMaxBmc, nRatio, fVerbose );
     if ( pTemp->pSeqModel )
     {
         ABC_FREE( pNtk->pModel );
@@ -2710,7 +2722,7 @@ Abc_Ntk_t * Abc_NtkInter( Abc_Ntk_t * pNtkOn, Abc_Ntk_t * pNtkOff, int fRelation
     // consider the case of one output
     if ( Abc_NtkCoNum(pNtkOn) == 1 )
         return Abc_NtkInterOne( pNtkOn, pNtkOff, fRelation, fVerbose );
-    // start the new newtork
+    // start the new network
     pNtkInter = Abc_NtkAlloc( ABC_NTK_STRASH, ABC_FUNC_AIG, 1 );
     pNtkInter->pName = Extra_UtilStrsav(pNtkOn->pName);
     Abc_NtkForEachPi( pNtkOn, pObj, i )
@@ -3393,7 +3405,7 @@ Abc_Ntk_t * Abc_NtkDarTestNtk( Abc_Ntk_t * pNtk )
         return NULL;
 /*
     Aig_ManSetRegNum( pMan, pMan->nRegs );
-    pMan = Saig_ManProofAbstraction( pTemp = pMan, 5, 10000, 0, 0, 0, -1, -1, 1 );
+    pMan = Saig_ManProofAbstraction( pTemp = pMan, 5, 10000, 0, 0, 0, -1, -1, 99, 1 );
     Aig_ManStop( pTemp );
     if ( pMan == NULL )
         return NULL;

src/base/abci/abcStrash.c

@@ -103,6 +103,7 @@ Abc_Ntk_t * Abc_NtkRestrashZero( Abc_Ntk_t * pNtk, bool fCleanup )
     Abc_Ntk_t * pNtkAig;
     Abc_Obj_t * pObj;
     int i, nNodes;//, RetValue;
+    int Counter = 0;
     assert( Abc_NtkIsStrash(pNtk) );
 //timeRetime = clock();
     // print warning about choice nodes
@@ -112,8 +113,14 @@ Abc_Ntk_t * Abc_NtkRestrashZero( Abc_Ntk_t * pNtk, bool fCleanup )
     pNtkAig = Abc_NtkStartFrom( pNtk, ABC_NTK_STRASH, ABC_FUNC_AIG );
     // complement the 1-values registers
     Abc_NtkForEachLatch( pNtk, pObj, i )
-        if ( Abc_LatchIsInit1(pObj) )
+    {
+        if ( Abc_LatchIsInitDc(pObj) )
+            Counter++;
+        else if ( Abc_LatchIsInit1(pObj) )
             Abc_ObjFanout0(pObj)->pCopy = Abc_ObjNot(Abc_ObjFanout0(pObj)->pCopy);
+    }
+    if ( Counter )
+    printf( "Converting %d flops from don't-care to zero initial value.\n", Counter );
     // restrash the nodes (assuming a topological order of the old network)
     Abc_NtkForEachNode( pNtk, pObj, i )
         pObj->pCopy = Abc_AigAnd( pNtkAig->pManFunc, Abc_ObjChild0Copy(pObj), Abc_ObjChild1Copy(pObj) );

src/base/abci/abcXsim.c

@@ -204,6 +204,7 @@ void Abc_NtkCycleInitState( Abc_Ntk_t * pNtk, int nFrames, int fUseXval, int fVe
     {
         Abc_NtkForEachPi( pNtk, pObj, i )
             Abc_ObjSetXsim( pObj, fUseXval? ABC_INIT_DC : Abc_XsimRand2() );
+//            Abc_ObjSetXsim( pObj, ABC_INIT_ONE );
         Abc_AigForEachAnd( pNtk, pObj, i )
             Abc_ObjSetXsim( pObj, Abc_XsimAnd(Abc_ObjGetXsimFanin0(pObj), Abc_ObjGetXsimFanin1(pObj)) );
         Abc_NtkForEachCo( pNtk, pObj, i )
@@ -213,7 +214,11 @@ void Abc_NtkCycleInitState( Abc_Ntk_t * pNtk, int nFrames, int fUseXval, int fVe
     }
     // set the final values
     Abc_NtkForEachLatch( pNtk, pObj, i )
+    {
         pObj->pData = (void *)(ABC_PTRINT_T)Abc_ObjGetXsim(Abc_ObjFanout0(pObj));
+//        printf( "%d", Abc_LatchIsInit1(pObj) );
+    }
+//    printf( "\n" );
 }
 
 ///////////////////////////////////////////////////////////////////////

src/base/io/io.c

@@ -1823,13 +1823,18 @@ int IoCommandWriteCounter( Abc_Frame_t * pAbc, int argc, char **argv )
     char * pFileName;
     int c;
     int fNames;
+    int forceSeq;
 
     fNames = 0;
+    forceSeq = 0;
     Extra_UtilGetoptReset();
-    while ( ( c = Extra_UtilGetopt( argc, argv, "nh" ) ) != EOF )
+    while ( ( c = Extra_UtilGetopt( argc, argv, "snh" ) ) != EOF )
     {
         switch ( c )
         {
+            case 's':
+                forceSeq ^= 1;
+                break;
             case 'n':
                 fNames ^= 1;
                 break;
@@ -1912,8 +1917,10 @@ int IoCommandWriteCounter( Abc_Frame_t * pAbc, int argc, char **argv )
         }
         if ( fNames )
         {
+            char *cycle_ctr = forceSeq?"@0":"";
             Abc_NtkForEachPi( pNtk, pObj, i )
-                fprintf( pFile, "%s=%c ", Abc_ObjName(pObj), '0'+(pNtk->pModel[i]==1) );
+//                fprintf( pFile, "%s=%c\n", Abc_ObjName(pObj), '0'+(pNtk->pModel[i]==1) );
+                fprintf( pFile, "%s%s=%c\n", Abc_ObjName(pObj), cycle_ctr, '0'+(pNtk->pModel[i]==1) );
         }
         else
         {
@@ -1927,9 +1934,10 @@ int IoCommandWriteCounter( Abc_Frame_t * pAbc, int argc, char **argv )
     return 0;
 
 usage:
-    fprintf( pAbc->Err, "usage: write_counter [-nh] <file>\n" );
+    fprintf( pAbc->Err, "usage: write_counter [-snh] <file>\n" );
     fprintf( pAbc->Err, "\t         saves counter-example derived by \"sat\", \"iprove\", or \"dprove\"\n" );
     fprintf( pAbc->Err, "\t         the file contains values for each PI in the natural order\n" );
+    fprintf( pAbc->Err, "\t-s     : always report a sequential ctrex (cycle 0 for comb) [default = %s]\n", forceSeq? "yes": "no" );
     fprintf( pAbc->Err, "\t-n     : write input names into the file [default = %s]\n", fNames? "yes": "no" );
     fprintf( pAbc->Err, "\t-h     : print the help massage\n" );
     fprintf( pAbc->Err, "\tfile   : the name of the file to write\n" );