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Commit d6d0627d by Alan Mishchenko
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Organizing commands for barbuf-aware flow.

parent 1a5a11cb
Showing with 353 additions and 103 deletions
src/base/cba/cbaBlast.c
......@@ -63,25 +63,27 @@ int Cba_ManAddBarbuf( Gia_Man_t * pNew, int iRes, Cba_Man_t * p, int iLNtk, int
}
return iBufLit;
}
int Cba_ManExtract_rec( Gia_Man_t * pNew, Cba_Ntk_t * p, int i, Vec_Int_t * vMap )
int Cba_ManExtract_rec( Gia_Man_t * pNew, Cba_Ntk_t * p, int i, int fBuffers, Vec_Int_t * vMap )
{
int iRes = Cba_NtkCopy( p, i );
if ( iRes >= 0 )
return iRes;
if ( Cba_ObjIsCo(p, i) )
iRes = Cba_ManExtract_rec( pNew, p, Cba_ObjFanin0(p, i), vMap );
iRes = Cba_ManExtract_rec( pNew, p, Cba_ObjFanin0(p, i), fBuffers, vMap );
else if ( Cba_ObjIsBo(p, i) )
{
Cba_Ntk_t * pBox = Cba_ObjBoModel( p, i );
int iObj = Cba_NtkPo( pBox, Cba_ObjCioIndex(p, i) );
iRes = Cba_ManExtract_rec( pNew, pBox, iObj, vMap );
iRes = Cba_ManExtract_rec( pNew, pBox, iObj, fBuffers, vMap );
if ( fBuffers )
iRes = Cba_ManAddBarbuf( pNew, iRes, p->pDesign, Cba_NtkId(p), i, Cba_NtkId(pBox), iObj, vMap );
}
else if ( Cba_ObjIsPi(p, i) )
{
Cba_Ntk_t * pHost = Cba_NtkHostNtk( p );
int iObj = Cba_ObjBoxBi( pHost, Cba_NtkHostObj(p), Cba_ObjCioIndex(p, i) );
iRes = Cba_ManExtract_rec( pNew, pHost, iObj, vMap );
iRes = Cba_ManExtract_rec( pNew, pHost, iObj, fBuffers, vMap );
if ( fBuffers )
iRes = Cba_ManAddBarbuf( pNew, iRes, p->pDesign, Cba_NtkId(p), i, Cba_NtkId(pHost), iObj, vMap );
}
else if ( Cba_ObjIsNode(p, i) )
......@@ -100,15 +102,15 @@ int Cba_ManExtract_rec( Gia_Man_t * pNew, Cba_Ntk_t * p, int i, Vec_Int_t * vMap
else if ( pFanins[0] == 1 )
{
if ( Type == CBA_NODE_BUF )
iRes = Cba_ManExtract_rec( pNew, p, pFanins[1], vMap );
iRes = Cba_ManExtract_rec( pNew, p, pFanins[1], fBuffers, vMap );
else if ( Type == CBA_NODE_INV )
iRes = Abc_LitNot( Cba_ManExtract_rec( pNew, p, pFanins[1], vMap ) );
iRes = Abc_LitNot( Cba_ManExtract_rec( pNew, p, pFanins[1], fBuffers, vMap ) );
else assert( 0 );
}
else
{
for ( k = 0; k < pFanins[0]; k++ )
pLits[k] = Cba_ManExtract_rec( pNew, p, pFanins[k+1], vMap );
pLits[k] = Cba_ManExtract_rec( pNew, p, pFanins[k+1], fBuffers, vMap );
if ( Type == CBA_NODE_AND )
iRes = Gia_ManHashAnd( pNew, pLits[0], pLits[1] );
else if ( Type == CBA_NODE_OR )
......@@ -124,7 +126,7 @@ int Cba_ManExtract_rec( Gia_Man_t * pNew, Cba_Ntk_t * p, int i, Vec_Int_t * vMap
Cba_NtkSetCopy( p, i, iRes );
return iRes;
}
Gia_Man_t * Cba_ManExtract( Cba_Man_t * p, int fVerbose )
Gia_Man_t * Cba_ManExtract( Cba_Man_t * p, int fBuffers, int fVerbose )
{
Cba_Ntk_t * pRoot = Cba_ManRoot(p);
Gia_Man_t * pNew, * pTemp;
......@@ -154,7 +156,7 @@ Gia_Man_t * Cba_ManExtract( Cba_Man_t * p, int fVerbose )
pNew->vBarBufs = Vec_IntAlloc( 10000 );
vMap = Vec_IntStartFull( 10000 );
Cba_NtkForEachPo( pRoot, iObj, i )
Cba_ManExtract_rec( pNew, pRoot, iObj, vMap );
Cba_ManExtract_rec( pNew, pRoot, iObj, fBuffers, vMap );
Vec_IntFreeP( &vMap );
Gia_ManHashStop( pNew );
......@@ -166,7 +168,7 @@ Gia_Man_t * Cba_ManExtract( Cba_Man_t * p, int fVerbose )
// cleanup
pNew = Gia_ManCleanup( pTemp = pNew );
Gia_ManStop( pTemp );
Gia_ManPrintStats( pNew, NULL );
//Gia_ManPrintStats( pNew, NULL );
return pNew;
}
......@@ -347,7 +349,7 @@ Cba_Man_t * Cba_ManInsertGia( Cba_Man_t * p, Gia_Man_t * pGia )
***********************************************************************/
Cba_Man_t * Cba_ManBlastTest( Cba_Man_t * p )
{
Gia_Man_t * pGia = Cba_ManExtract( p, 0 );
Gia_Man_t * pGia = Cba_ManExtract( p, 1, 0 );
Cba_Man_t * pNew = Cba_ManInsertGia( p, pGia );
Gia_ManStop( pGia );
Cba_ManAssignInternNames( pNew );
......@@ -355,6 +357,26 @@ Cba_Man_t * Cba_ManBlastTest( Cba_Man_t * p )
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void * Cba_ManInsertAbc( Cba_Man_t * p, void * pAbc )
{
Abc_Ntk_t * pNtk = pAbc;
Cba_Man_t * pNew = NULL;
return pNew;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
......
src/base/cba/cbaBuild.c
......@@ -204,7 +204,6 @@ Cba_Ntk_t * Cba_NtkBuild( Cba_Man_t * pNew, Cba_Ntk_t * pNtk, Vec_Int_t * vMap,
{
ObjId = Vec_IntEntry( &pNtkNew->vBoxes, nBoxes++ );
pNtkBox = Cba_ObjBoxModel( pNtk, iObj );
Cba_NtkSetHost( pNtkBox, Cba_NtkId(pNtk), ObjId );
// collect fanins
Vec_IntFill( vTemp, Cba_NtkPiNum(pNtkBox), -1 );
Vec_IntForEachEntry( vFanins, Index, i )
......@@ -227,6 +226,7 @@ Cba_Ntk_t * Cba_NtkBuild( Cba_Man_t * pNew, Cba_Ntk_t * pNtk, Vec_Int_t * vMap,
// create box
Vec_IntWriteEntry( &pNtkNew->vTypes, ObjId, CBA_OBJ_BOX );
Vec_IntWriteEntry( &pNtkNew->vFuncs, ObjId, Cba_ManNtkId(pNew, Cba_NtkName(pNtkBox)) );
Cba_NtkSetHost( Cba_ObjBoxModel(pNtkNew, ObjId), Cba_NtkId(pNtkNew), ObjId );
// create box inputs
Cba_BoxForEachBi( pNtkNew, ObjId, FaninId, i )
{
......@@ -311,7 +311,8 @@ Cba_Man_t * Cba_ManBuild( Cba_Man_t * p )
Vec_Int_t * vMap = Vec_IntStartFull( Abc_NamObjNumMax(p->pNames) + 1 );
Vec_Int_t * vNonDr = Vec_IntAlloc( 1000 );
Vec_Int_t * vTemp = Vec_IntAlloc( 1000 );
Cba_Ntk_t * pNtk; int i, nObjs;
Cba_Ntk_t * pNtk;
int i, nObjs;
assert( Abc_NamObjNumMax(p->pModels) == Cba_ManNtkNum(p) + 1 );
Cba_ManForEachNtk( p, pNtk, i )
{
......
src/base/cba/cbaNtk.c
......@@ -74,13 +74,6 @@ void Cba_ManAssignInternNames( Cba_Man_t * p )
SeeAlso []
***********************************************************************/
int Cba_NtkNodeNum( Cba_Ntk_t * p )
{
int iObj, Count = 0;
Cba_NtkForEachNode( p, iObj )
Count++;
return Count;
}
int Cba_ManObjNum( Cba_Man_t * p )
{
Cba_Ntk_t * pNtk;
......@@ -136,6 +129,9 @@ void Cba_NtkDupStart( Cba_Ntk_t * pNew, Cba_Ntk_t * p )
Cba_ObjDupStart( pNew, p, iObj );
Cba_BoxForEachBo( p, iObj, iTerm, k )
Cba_ObjDupStart( pNew, p, iTerm );
// connect box outputs to boxes
Cba_BoxForEachBo( p, iObj, iTerm, k )
Vec_IntWriteEntry( &pNew->vFanins, Cba_NtkCopy(p, iTerm), Cba_NtkCopy(p, Cba_ObjFanin0(p, iTerm)) );
}
assert( Cba_NtkBoxNum(p) == Cba_NtkBoxNum(pNew) );
}
......@@ -174,10 +170,11 @@ void Cba_NtkDupNodes( Cba_Ntk_t * pNew, Cba_Ntk_t * p, Vec_Int_t * vTemp )
// connect
Cba_NtkForEachObjType( p, Type, i )
{
if ( Type == CBA_OBJ_PI || Type == CBA_OBJ_BOX )
if ( Type == CBA_OBJ_PI || Type == CBA_OBJ_BOX || Type == CBA_OBJ_BO )
continue;
if ( Type == CBA_OBJ_PO || Type == CBA_OBJ_BI || Type == CBA_OBJ_BO )
if ( Type == CBA_OBJ_PO || Type == CBA_OBJ_BI )
{
assert( Vec_IntEntry(&pNew->vFanins, Cba_NtkCopy(p, i)) == -1 );
Vec_IntWriteEntry( &pNew->vFanins, Cba_NtkCopy(p, i), Cba_NtkCopy(p, Cba_ObjFanin0(p, i)) );
continue;
}
......
src/base/cba/cbaPrs.h
......@@ -168,7 +168,7 @@ static inline Cba_Prs_t * Cba_PrsAlloc( char * pFileName )
p->pBuffer = pBuffer;
p->pLimit = pLimit;
p->pCur = pBuffer;
p->pDesign = Cba_ManAlloc( pFileName );
p->pDesign = Cba_ManAlloc( NULL, pFileName );
return p;
}
static inline void Cba_PrsFree( Cba_Prs_t * p )
......@@ -195,6 +195,20 @@ static inline void Cba_PrsFree( Cba_Prs_t * p )
ABC_FREE( p->pBuffer );
ABC_FREE( p );
}
static inline void Cba_PrsRemapBoxModels( Cba_Man_t * p )
{
Cba_Ntk_t * pNtk;
int i, Type, iObj;
Cba_ManForEachNtk( p, pNtk, i )
Cba_NtkForEachObjType( pNtk, Type, iObj )
if ( Type == CBA_OBJ_BOX )
{
char * pName = Abc_NamStr( p->pNames, Cba_ObjFuncId(pNtk, iObj) );
int iModelId = Abc_NamStrFind( p->pModels, pName );
assert( iModelId > 0 );
Vec_IntWriteEntry( &pNtk->vFuncs, iObj, iModelId );
}
}
////////////////////////////////////////////////////////////////////////
/// ITERATORS ///
......
src/base/cba/cbaReadBlif.c
......@@ -64,9 +64,9 @@ static inline void Cba_PrsAddBlifDirectives( Cba_Prs_t * p )
for ( i = 1; s_BlifTypes[i]; i++ )
Abc_NamStrFindOrAdd( p->pDesign->pNames, (char *)s_BlifTypes[i], NULL );
assert( Abc_NamObjNumMax(p->pDesign->pNames) == i );
Abc_NamStrFindOrAdd( p->pDesign->pFuncs, (char *)" 0\n", NULL ); // default const 0 function
Abc_NamStrFindOrAdd( p->pDesign->pFuncs, (char *)"1 1\n", NULL ); // default buffer function
assert( Abc_NamObjNumMax(p->pDesign->pFuncs) == 3 );
for ( i = 1; i < CBA_NODE_UNKNOWN; i++ )
Abc_NamStrFindOrAdd( p->pDesign->pFuncs, Ptr_TypeToSop(i), NULL );
assert( Abc_NamObjNumMax(p->pDesign->pFuncs) == i-1 );
}
......@@ -408,6 +408,7 @@ Cba_Man_t * Cba_PrsReadBlif( char * pFileName )
if ( Cba_PrsErrorPrint(p) )
ABC_SWAP( Cba_Man_t *, pDesign, p->pDesign );
Cba_PrsFree( p );
Cba_PrsRemapBoxModels( pDesign );
return pDesign;
}
......
src/base/cba/cbaReadVer.c
......@@ -80,7 +80,7 @@ static inline int Cba_IsChar( char c ) { return (c >= 'a' && c <= 'z') || (c
static inline int Cba_IsSymb1( char c ) { return Cba_IsChar(c) || c == '_'; }
static inline int Cba_IsSymb2( char c ) { return Cba_IsSymb1(c) || Cba_IsDigit(c) || c == '$'; }
static inline int Cba_PrsIsChar( Cba_Prs_t * p, char c ) { return *p->pCur == c; }
static inline int Cba_PrsIsChar( Cba_Prs_t * p, char c ) { return p->pCur[0] == c; }
static inline int Cba_PrsIsChar1( Cba_Prs_t * p, char c ) { return p->pCur[1] == c; }
static inline int Cba_PrsIsDigit( Cba_Prs_t * p ) { return Cba_IsDigit(*p->pCur); }
......@@ -720,6 +720,7 @@ Cba_Man_t * Cba_PrsReadVerilog( char * pFileName )
if ( Cba_PrsErrorPrint(p) )
ABC_SWAP( Cba_Man_t *, pDesign, p->pDesign );
Cba_PrsFree( p );
Cba_PrsRemapBoxModels( pDesign );
return pDesign;
}
......@@ -727,18 +728,18 @@ void Cba_PrsReadVerilogTest( char * pFileName )
{
abctime clk = Abc_Clock();
extern void Cba_PrsWriteVerilog( char * pFileName, Cba_Man_t * p );
// Cba_Man_t * p = Cba_PrsReadVerilog( "c/hie/dump/1/netlist_1.v" );
Cba_Man_t * p = Cba_PrsReadVerilog( "c/hie/dump/1/netlist_1.v" );
// Cba_Man_t * p = Cba_PrsReadVerilog( "aga/me/me_wide.v" );
Cba_Man_t * p = Cba_PrsReadVerilog( "aga/ray/ray_wide.v" );
// Cba_Man_t * p = Cba_PrsReadVerilog( "aga/ray/ray_wide.v" );
if ( !p ) return;
printf( "Finished reading %d networks. ", Cba_ManNtkNum(p) );
printf( "NameIDs = %d. ", Abc_NamObjNumMax(p->pNames) );
printf( "Memory = %.2f MB. ", 1.0*Cba_ManMemory(p)/(1<<20) );
Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
// Abc_NamPrint( p->pDesign->pNames );
// Cba_PrsWriteVerilog( "c/hie/dump/1/netlist_1_out.v", p );
Cba_PrsWriteVerilog( "c/hie/dump/1/netlist_1_out.v", p );
// Cba_PrsWriteVerilog( "aga/me/me_wide_out.v", p );
Cba_PrsWriteVerilog( "aga/ray/ray_wide_out.v", p );
// Cba_PrsWriteVerilog( "aga/ray/ray_wide_out.v", p );
Cba_ManFree( p );
}
......
src/base/cba/cbaSimple.c
......@@ -60,6 +60,8 @@ Cba_NodeType_t Ptr_HopToType( Abc_Obj_t * pObj )
};
assert( Abc_ObjIsNode(pObj) );
uTruth = Hop_ManComputeTruth6( (Hop_Man_t *)Abc_ObjNtk(pObj)->pManFunc, (Hop_Obj_t *)pObj->pData, Abc_ObjFaninNum(pObj) );
if ( uTruth == 0 ) return CBA_NODE_C0;
if ( uTruth == ~(word)0 ) return CBA_NODE_C1;
if ( uTruth == uTruths6[0] ) return CBA_NODE_BUF;
if ( uTruth == ~uTruths6[0] ) return CBA_NODE_INV;
if ( uTruth == (uTruths6[0] & uTruths6[1]) ) return CBA_NODE_AND;
......@@ -107,7 +109,11 @@ Vec_Ptr_t * Ptr_AbcDeriveNode( Abc_Obj_t * pObj )
Vec_Ptr_t * vNode = Vec_PtrAlloc( 2 + Abc_ObjFaninNum(pObj) );
assert( Abc_ObjIsNode(pObj) );
Vec_PtrPush( vNode, Ptr_AbcObjName(pObj) );
if ( Abc_NtkHasAig(pObj->pNtk) )
Vec_PtrPush( vNode, Abc_Int2Ptr(Ptr_HopToType(pObj)) );
else if ( Abc_NtkHasSop(pObj->pNtk) )
Vec_PtrPush( vNode, Abc_Int2Ptr(Ptr_SopToType((char *)pObj->pData)) );
else assert( 0 );
Abc_ObjForEachFanin( pObj, pFanin, i )
Vec_PtrPush( vNode, Ptr_AbcObjName(pFanin) );
assert( Ptr_CheckArray(vNode) );
......@@ -601,47 +607,36 @@ void Cba_PrsReadBoxes( Cba_Man_t * p, Vec_Ptr_t * vBoxes, Vec_Int_t * vTypesCur,
Vec_IntPush( vFaninsCur, Cba_ManHandleArray(p, Cba_PrsReadList(p, vBox, vList, 0, 1)) );
}
}
void Cba_PrsReadModule( Cba_Man_t * p, Cba_Ntk_t * pNtk, Vec_Ptr_t * vNtk )
{
Vec_Int_t * vInputsCur = Vec_IntAlloc( 1000 );
Vec_Int_t * vOutputsCur = Vec_IntAlloc( 1000 );
Vec_Int_t * vTypesCur = Vec_IntAlloc( 1000 );
Vec_Int_t * vFuncsCur = Vec_IntAlloc( 1000 );
Vec_Int_t * vInstIdsCur = Vec_IntAlloc( 1000 );
Vec_Int_t * vFaninsCur = Vec_IntAlloc( 1000 );
Vec_Int_t * vList = Vec_IntAlloc( 1000 );
Vec_Int_t * vBoxes = Vec_IntStart( Vec_PtrSize((Vec_Ptr_t *)Vec_PtrEntry(vNtk, 4)) );
Cba_PrsReadList( p, (Vec_Ptr_t *)Vec_PtrEntry(vNtk, 1), vInputsCur, -1, -1 );
Cba_PrsReadList( p, (Vec_Ptr_t *)Vec_PtrEntry(vNtk, 2), vOutputsCur, -1, -1 );
Cba_PrsReadNodes( p, (Vec_Ptr_t *)Vec_PtrEntry(vNtk, 3), vTypesCur, vFuncsCur, vInstIdsCur, vFaninsCur, vList );
Cba_PrsReadBoxes( p, (Vec_Ptr_t *)Vec_PtrEntry(vNtk, 4), vTypesCur, vFuncsCur, vInstIdsCur, vFaninsCur, vList );
Cba_ManSetupArray( p, &pNtk->vInputs, vInputsCur );
Cba_ManSetupArray( p, &pNtk->vOutputs, vOutputsCur );
Cba_ManSetupArray( p, &pNtk->vTypes, vTypesCur );
Cba_ManSetupArray( p, &pNtk->vFuncs, vFuncsCur );
Cba_ManSetupArray( p, &pNtk->vInstIds, vInstIdsCur );
Cba_ManSetupArray( p, &pNtk->vFanins, vFaninsCur );
Cba_ManSetupArray( p, &pNtk->vBoxes, vBoxes );
Vec_IntFree( vInputsCur );
Vec_IntFree( vOutputsCur );
Vec_IntFree( vTypesCur );
Vec_IntFree( vFuncsCur );
Vec_IntFree( vInstIdsCur );
Vec_IntFree( vFaninsCur );
Vec_IntFree( vList );
Vec_IntFree( vBoxes );
void Cba_PrsReadModule( Cba_Man_t * p, Cba_Ntk_t * pNtk, Vec_Ptr_t * vNtk, Vec_Int_t * vList )
{
Vec_Ptr_t * vInputs = (Vec_Ptr_t *)Vec_PtrEntry(vNtk, 1);
Vec_Ptr_t * vOutputs = (Vec_Ptr_t *)Vec_PtrEntry(vNtk, 2);
Vec_Ptr_t * vNodes = (Vec_Ptr_t *)Vec_PtrEntry(vNtk, 3);
Vec_Ptr_t * vBoxes = (Vec_Ptr_t *)Vec_PtrEntry(vNtk, 4);
Cba_ManAllocArray( p, &pNtk->vInputs, Vec_PtrSize(vInputs) );
Cba_ManAllocArray( p, &pNtk->vOutputs, Vec_PtrSize(vOutputs) );
Cba_ManAllocArray( p, &pNtk->vTypes, Vec_PtrSize(vNodes) + Vec_PtrSize(vBoxes) );
Cba_ManAllocArray( p, &pNtk->vFuncs, Vec_PtrSize(vNodes) + Vec_PtrSize(vBoxes) );
Cba_ManAllocArray( p, &pNtk->vInstIds, Vec_PtrSize(vNodes) + Vec_PtrSize(vBoxes) );
Cba_ManAllocArray( p, &pNtk->vFanins, Vec_PtrSize(vNodes) + Vec_PtrSize(vBoxes) );
Cba_ManAllocArray( p, &pNtk->vBoxes, Vec_PtrSize(vBoxes) );
Cba_PrsReadList( p, vInputs, &pNtk->vInputs, -1, -1 );
Cba_PrsReadList( p, vOutputs, &pNtk->vOutputs, -1, -1 );
Cba_PrsReadNodes( p, vNodes, &pNtk->vTypes, &pNtk->vFuncs, &pNtk->vInstIds, &pNtk->vFanins, vList );
Cba_PrsReadBoxes( p, vBoxes, &pNtk->vTypes, &pNtk->vFuncs, &pNtk->vInstIds, &pNtk->vFanins, vList );
}
Cba_Man_t * Cba_PrsReadPtr( Vec_Ptr_t * vDes )
{
Vec_Ptr_t * vNtk; int i;
Cba_Man_t * p = Cba_ManAlloc( (char *)Vec_PtrEntry(vDes, 0) );
Vec_Int_t * vList = Vec_IntAlloc( 100 );
Cba_Man_t * p = Cba_ManAlloc( NULL, (char *)Vec_PtrEntry(vDes, 0) );
Vec_PtrForEachEntryStart( Vec_Ptr_t *, vDes, vNtk, i, 1 )
Cba_NtkAlloc( p, (char *)Vec_PtrEntry(vNtk, 0) );
Vec_PtrForEachEntryStart( Vec_Ptr_t *, vDes, vNtk, i, 1 )
Cba_PrsReadModule( p, Cba_ManNtk(p, i), vNtk );
Cba_PrsReadModule( p, Cba_ManNtk(p, i), vNtk, vList );
Vec_IntFree( vList );
return p;
}
......
src/base/cba/cbaWriteBlif.c
......@@ -114,7 +114,7 @@ void Cba_PrsWriteBlif( char * pFileName, Cba_Man_t * p )
printf( "Cannot open output file \"%s\".\n", pFileName );
return;
}
fprintf( pFile, "// Design \"%s\" written by ABC on %s\n\n", Cba_ManName(p), Extra_TimeStamp() );
fprintf( pFile, "# Design \"%s\" written by ABC on %s\n\n", Cba_ManName(p), Extra_TimeStamp() );
Cba_ManForEachNtk( p, pNtk, i )
Cba_PrsWriteBlifNtk( pFile, pNtk );
fclose( pFile );
......@@ -207,7 +207,8 @@ void Cba_ManWriteBlif( char * pFileName, Cba_Man_t * p )
printf( "Cannot open output file \"%s\".\n", pFileName );
return;
}
fprintf( pFile, "// Design \"%s\" written by ABC on %s\n\n", Cba_ManName(p), Extra_TimeStamp() );
fprintf( pFile, "# Design \"%s\" written by ABC on %s\n\n", Cba_ManName(p), Extra_TimeStamp() );
Cba_ManAssignInternNames( p );
Cba_ManForEachNtk( p, pNtk, i )
Cba_ManWriteBlifNtk( pFile, pNtk );
fclose( pFile );
......
src/base/cba/cbaWriteVer.c
......@@ -120,7 +120,7 @@ void Cba_PrsWriteVerilogBoxes( FILE * pFile, Cba_Ntk_t * p )
Cba_NtkForEachObjType( p, Type, i )
if ( Type == CBA_OBJ_BOX ) // .subckt/.gate/box (formal/actual binding)
{
fprintf( pFile, " %s %s (", Cba_ObjFuncStr(p, i), Cba_ObjInstStr(p, i) );
fprintf( pFile, " %s %s (", Cba_NtkName(Cba_ObjBoxModel(p, i)), Cba_ObjInstStr(p, i) );
Cba_PrsWriteVerilogArray3( pFile, p, Cba_ObjFaninVec(p, i) );
fprintf( pFile, ");\n" );
}
......@@ -186,6 +186,61 @@ void Cba_PrsWriteVerilog( char * pFileName, Cba_Man_t * p )
/**Function*************************************************************
Synopsis [Collect all nodes names used that are not inputs/outputs.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Cba_NtkCollectWires( Cba_Ntk_t * p, Vec_Int_t * vMap )
{
Vec_Int_t * vWires = &p->vWires;
int i, iObj, iFanin, Type, NameId;
Vec_IntClear( vWires );
Cba_NtkForEachPi( p, iObj, i )
Vec_IntWriteEntry( vMap, Cba_ObjNameId(p, iObj), 1 );
Cba_NtkForEachPo( p, iObj, i )
Vec_IntWriteEntry( vMap, Cba_ObjNameId(p, iObj), 1 );
Cba_NtkForEachObjType( p, Type, iObj )
{
if ( Type == CBA_OBJ_NODE )
{
Vec_Int_t * vFanins = Cba_ObjFaninVec( p, iObj );
Vec_IntForEachEntry( vFanins, iFanin, i )
{
NameId = Cba_ObjNameId( p, iFanin );
if ( Vec_IntEntry(vMap, NameId) == 0 )
{
Vec_IntWriteEntry( vMap, NameId, 1 );
Vec_IntPush( vWires, NameId );
}
}
}
else if ( Cba_ObjIsPo(p, iObj) || Cba_ObjIsBi(p, iObj) )
{
iFanin = Cba_ObjFanin0( p, iObj );
NameId = Cba_ObjNameId( p, iFanin );
if ( Vec_IntEntry(vMap, NameId) == 0 )
{
Vec_IntWriteEntry( vMap, NameId, 1 );
Vec_IntPush( vWires, NameId );
}
}
}
Cba_NtkForEachPi( p, iObj, i )
Vec_IntWriteEntry( vMap, Cba_ObjNameId(p, iObj), 0 );
Cba_NtkForEachPo( p, iObj, i )
Vec_IntWriteEntry( vMap, Cba_ObjNameId(p, iObj), 0 );
Vec_IntForEachEntry( vWires, NameId, i )
Vec_IntWriteEntry( vMap, NameId, 0 );
return vWires;
}
/**Function*************************************************************
Synopsis []
Description []
......@@ -195,6 +250,129 @@ void Cba_PrsWriteVerilog( char * pFileName, Cba_Man_t * p )
SeeAlso []
***********************************************************************/
void Cba_ManWriteVerilogArray2( FILE * pFile, Cba_Ntk_t * p, int iObj, Vec_Int_t * vFanins )
{
int i, iFanin;
fprintf( pFile, "%s%s", Cba_ObjNameStr(p, iObj), (Vec_IntSize(vFanins) == 0) ? "" : ", " );
Vec_IntForEachEntry( vFanins, iFanin, i )
fprintf( pFile, "%s%s", Cba_ObjNameStr(p, iFanin), (i == Vec_IntSize(vFanins) - 1) ? "" : ", " );
}
void Cba_ManWriteVerilogNodes( FILE * pFile, Cba_Ntk_t * p )
{
int Type, Func, i;
Cba_NtkForEachObjType( p, Type, i )
if ( Type == CBA_OBJ_NODE ) // .names/assign/box2 (no formal/actual binding)
{
Func = Cba_ObjFuncId(p, i);
if ( Func >= CBA_NODE_BUF && Func <= CBA_NODE_XNOR )
{
fprintf( pFile, " %s (", Ptr_TypeToName(Func) );
Cba_ManWriteVerilogArray2( pFile, p, i, Cba_ObjFaninVec(p, i) );
fprintf( pFile, ");\n" );
}
// else if ( Func == CBA_NODE_MUX )
// Cba_PrsWriteVerilogMux( pFile, p, Cba_ObjFaninVec(p, i) );
else
{
//char * pName = Cba_NtkStr(p, Func);
assert( 0 );
}
}
}
void Cba_ManWriteVerilogBoxes( FILE * pFile, Cba_Ntk_t * p )
{
int i, k, iTerm, Type;
Cba_NtkForEachObjType( p, Type, i )
if ( Type == CBA_OBJ_BOX ) // .subckt/.gate/box (formal/actual binding)
{
Cba_Ntk_t * pModel = Cba_ObjBoxModel( p, i );
fprintf( pFile, " %s %s (", Cba_NtkName(pModel), Vec_IntSize(&p->vInstIds) ? Cba_ObjInstStr(p, i) : "" );
Cba_NtkForEachPi( pModel, iTerm, k )
fprintf( pFile, " %s=%s", Cba_ObjNameStr(pModel, iTerm), Cba_ObjNameStr(p, Cba_ObjBoxBi(p, i, k)) );
Cba_NtkForEachPo( pModel, iTerm, k )
fprintf( pFile, " %s=%s", Cba_ObjNameStr(pModel, iTerm), Cba_ObjNameStr(p, Cba_ObjBoxBo(p, i, k)) );
fprintf( pFile, "\n" );
}
}
void Cba_ManWriteVerilogSignals( FILE * pFile, Cba_Ntk_t * p, int SigType, int fNoRange )
{
int NameId, RangeId, i;
char * pSigNames[4] = { "inout", "input", "output", "wire" };
Vec_Int_t * vSigs[4] = { &p->vInouts, &p->vInputs, &p->vOutputs, &p->vWires };
if ( fNoRange )
{
Vec_IntForEachEntry( vSigs[SigType], NameId, i )
fprintf( pFile, " %s %s;\n", pSigNames[SigType], SigType==3 ? Cba_NtkStr(p, NameId) : Cba_ObjNameStr(p, NameId) );
}
else
{
Vec_IntForEachEntryDouble( vSigs[SigType], NameId, RangeId, i )
fprintf( pFile, " %s %s%s;\n", pSigNames[SigType], RangeId ? Cba_NtkStr(p, RangeId) : "", SigType==3 ? Cba_NtkStr(p, NameId) : Cba_ObjNameStr(p, NameId) );
}
}
void Cba_ManWriteVerilogSignalList( FILE * pFile, Cba_Ntk_t * p, int SigType, int fSkipComma, int fNoRange )
{
int NameId, RangeId, i;
Vec_Int_t * vSigs[4] = { &p->vInouts, &p->vInputs, &p->vOutputs, &p->vWires };
if ( fNoRange )
{
Vec_IntForEachEntry( vSigs[SigType], NameId, i )
fprintf( pFile, "%s%s", Cba_ObjNameStr(p, NameId), (fSkipComma && i == Vec_IntSize(vSigs[SigType]) - 1) ? "" : ", " );
}
else
{
Vec_IntForEachEntryDouble( vSigs[SigType], NameId, RangeId, i )
fprintf( pFile, "%s%s", Cba_ObjNameStr(p, NameId), (fSkipComma && i == Vec_IntSize(vSigs[SigType]) - 2) ? "" : ", " );
}
}
void Cba_ManWriteVerilogNtk( FILE * pFile, Cba_Ntk_t * p, Vec_Int_t * vMap )
{
int s;
assert( Vec_IntSize(&p->vTypes) == Cba_NtkObjNum(p) );
assert( Vec_IntSize(&p->vFuncs) == Cba_NtkObjNum(p) );
// collect wires
Cba_NtkCollectWires( p, vMap );
// write header
fprintf( pFile, "module %s (\n", Cba_NtkName(p) );
for ( s = 0; s < 3; s++ )
{
if ( s == 0 && Vec_IntSize(&p->vInouts) == 0 )
continue;
fprintf( pFile, " " );
Cba_ManWriteVerilogSignalList( pFile, p, s, s==2, 1 );
fprintf( pFile, "\n" );
}
fprintf( pFile, " );\n" );
// write declarations
for ( s = 0; s < 4; s++ )
Cba_ManWriteVerilogSignals( pFile, p, s, 1 );
fprintf( pFile, "\n" );
// write objects
Cba_ManWriteVerilogNodes( pFile, p );
Cba_ManWriteVerilogBoxes( pFile, p );
fprintf( pFile, "endmodule\n\n" );
Vec_IntErase( &p->vWires );
}
void Cba_ManWriteVerilog( char * pFileName, Cba_Man_t * p )
{
FILE * pFile;
Cba_Ntk_t * pNtk;
Vec_Int_t * vMap;
int i;
pFile = fopen( pFileName, "wb" );
if ( pFile == NULL )
{
printf( "Cannot open output file \"%s\".\n", pFileName );
return;
}
fprintf( pFile, "// Design \"%s\" written by ABC on %s\n\n", Cba_ManName(p), Extra_TimeStamp() );
Cba_ManAssignInternNames( p );
vMap = Vec_IntStart( Abc_NamObjNumMax(p->pNames) + 1 );
Cba_ManForEachNtk( p, pNtk, i )
Cba_ManWriteVerilogNtk( pFile, pNtk, vMap );
Vec_IntFree( vMap );
fclose( pFile );
}
////////////////////////////////////////////////////////////////////////
......
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