Version abc80706

abc.dsp

@@ -386,6 +386,10 @@ SOURCE=.\src\base\abci\abcSat.c
 # End Source File
 # Begin Source File
 
+SOURCE=.\src\base\abci\abcSense.c
+# End Source File
+# Begin Source File
+
 SOURCE=.\src\base\abci\abcStrash.c
 # End Source File
 # Begin Source File
@@ -3314,6 +3318,10 @@ SOURCE=.\src\aig\nwk\nwkMap.c
 # End Source File
 # Begin Source File
 
+SOURCE=.\src\aig\nwk\nwkMerge.c
+# End Source File
+# Begin Source File
+
 SOURCE=.\src\aig\nwk\nwkObj.c
 # End Source File
 # Begin Source File

src/aig/nwk/module.make

@@ -6,6 +6,7 @@ SRC +=    src/aig/nwk/nwkAig.c \
     src/aig/nwk/nwkFlow.c \
     src/aig/nwk/nwkMan.c \
     src/aig/nwk/nwkMap.c \
+    src/aig/nwk/nwkMerge.c \
     src/aig/nwk/nwkObj.c \
     src/aig/nwk/nwkSpeedup.c \
     src/aig/nwk/nwkStrash.c \

src/aig/nwk/nwk.h

@@ -109,6 +109,20 @@ struct Nwk_Obj_t_
 };
 
 
+// the LUT merging parameters
+typedef struct Nwk_LMPars_t_  Nwk_LMPars_t;
+struct Nwk_LMPars_t_
+{
+    int  nMaxLutSize;       // the max LUT size for merging (N=5)
+    int  nMaxSuppSize;      // the max total support size after merging (S=5)
+    int  nMaxDistance;      // the max number of nodes separating LUTs
+    int  nMaxLevelDiff;     // the max difference in levels
+    int  nMaxFanout;        // the max number of fanouts to traverse
+    int  fUseTfiTfo;        // enables the use of TFO/TFO nodes as candidates
+    int  fVeryVerbose;      // enables additional verbose output
+    int  fVerbose;          // enables verbose output
+};
+
 ////////////////////////////////////////////////////////////////////////
 ///                      MACRO DEFINITIONS                           ///
 ////////////////////////////////////////////////////////////////////////

src/base/abci/abcSense.c

+/**CFile****************************************************************
+
+  FileName    [abcSense.c]
+
+  SystemName  [ABC: Logic synthesis and verification system.]
+
+  PackageName [Network and node package.]
+
+  Synopsis    []
+
+  Author      [Alan Mishchenko]
+  
+  Affiliation [UC Berkeley]
+
+  Date        [Ver. 1.0. Started - June 20, 2005.]
+
+  Revision    [$Id: abc_.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
+
+***********************************************************************/
+
+#include "abc.h"
+#include "fraig.h"
+
+////////////////////////////////////////////////////////////////////////
+///                        DECLARATIONS                              ///
+////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////
+///                     FUNCTION DEFINITIONS                         ///
+////////////////////////////////////////////////////////////////////////
+
+/**Function*************************************************************
+
+  Synopsis    [Copies the topmost levels of the network.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Abc_Obj_t * Abc_NtkSensitivityMiter_rec( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNode )
+{
+    assert( !Abc_ObjIsComplement(pNode) );
+    if ( pNode->pCopy )
+        return pNode->pCopy;
+    Abc_NtkSensitivityMiter_rec( pNtkNew, Abc_ObjFanin0(pNode) );
+    Abc_NtkSensitivityMiter_rec( pNtkNew, Abc_ObjFanin1(pNode) );
+    return pNode->pCopy = Abc_AigAnd( pNtkNew->pManFunc, Abc_ObjChild0Copy(pNode), Abc_ObjChild1Copy(pNode) );
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Creates miter for the sensitivity analysis.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Abc_Ntk_t * Abc_NtkSensitivityMiter( Abc_Ntk_t * pNtk, int iVar )
+{
+    Abc_Ntk_t * pMiter;
+    Vec_Ptr_t * vNodes;
+    Abc_Obj_t * pObj, * pNext, * pFanin, * pOutput, * pObjNew;
+    int i;
+    assert( Abc_NtkIsStrash(pNtk) );
+    assert( iVar < Abc_NtkCiNum(pNtk) );
+
+    // duplicate the network
+    pMiter = Abc_NtkAlloc( ABC_NTK_STRASH, ABC_FUNC_AIG, 1 );
+    pMiter->pName = Extra_UtilStrsav(pNtk->pName);
+    pMiter->pSpec = Extra_UtilStrsav(pNtk->pSpec);
+
+    // assign the PIs
+    Abc_NtkCleanCopy( pNtk );
+    Abc_AigConst1(pNtk)->pCopy = Abc_AigConst1(pMiter);
+    Abc_AigConst1(pNtk)->pData = Abc_AigConst1(pMiter);
+    Abc_NtkForEachCi( pNtk, pObj, i )
+        pObj->pCopy = pObj->pData = Abc_NtkCreatePi( pMiter );
+    Abc_NtkAddDummyPiNames( pMiter );
+
+    // assign the cofactors of the CI node to be constants
+    pObj = Abc_NtkCi( pNtk, iVar );
+    pObj->pCopy = Abc_ObjNot( Abc_AigConst1(pMiter) ); 
+    pObj->pData = Abc_AigConst1(pMiter); 
+
+    // collect the internal nodes
+    vNodes = Abc_NtkDfsReverseNodes( pNtk, &pObj, 1 );
+    Vec_PtrForEachEntry( vNodes, pObj, i )
+    {
+        for ( pNext = pObj? pObj->pCopy : pObj; pObj; pObj = pNext, pNext = pObj? pObj->pCopy : pObj )
+        {
+            pFanin = Abc_ObjFanin0(pObj);
+            if ( !Abc_NodeIsTravIdCurrent(pFanin) )
+                pFanin->pData = Abc_NtkSensitivityMiter_rec( pMiter, pFanin );
+            pFanin = Abc_ObjFanin1(pObj);
+            if ( !Abc_NodeIsTravIdCurrent(pFanin) )
+                pFanin->pData = Abc_NtkSensitivityMiter_rec( pMiter, pFanin );
+            pObj->pCopy = Abc_AigAnd( pMiter->pManFunc, Abc_ObjChild0Copy(pObj), Abc_ObjChild1Copy(pObj) );
+            pObj->pData = Abc_AigAnd( pMiter->pManFunc, Abc_ObjChild0Data(pObj), Abc_ObjChild1Data(pObj) );
+        }
+    }
+    Vec_PtrFree( vNodes );
+
+    // update the affected COs
+    pOutput = Abc_ObjNot( Abc_AigConst1(pMiter) ); 
+    Abc_NtkForEachCo( pNtk, pObj, i )
+    {
+        if ( !Abc_NodeIsTravIdCurrent(pObj) )
+            continue;
+        // get the result of quantification
+        if ( i == Abc_NtkCoNum(pNtk) - 1 )
+        {
+            pOutput = Abc_AigAnd( pMiter->pManFunc, pOutput, Abc_ObjChild0Data(pObj) );
+            pOutput = Abc_AigAnd( pMiter->pManFunc, pOutput, Abc_ObjChild0Copy(pObj) );
+        }
+        else
+        {
+            pNext   = Abc_AigXor( pMiter->pManFunc, Abc_ObjChild0Copy(pObj), Abc_ObjChild0Data(pObj) );
+            pOutput = Abc_AigOr( pMiter->pManFunc, pOutput, pNext );
+        }
+    }
+    // add the PO node and name
+    pObjNew = Abc_NtkCreatePo(pMiter);
+    Abc_ObjAddFanin( pObjNew, pOutput );
+    Abc_ObjAssignName( pObjNew, "miter", NULL );
+    // make sure everything is okay
+    if ( !Abc_NtkCheck( pMiter ) )
+    {
+        printf( "Abc_NtkSensitivityMiter: The network check has failed.\n" );
+        Abc_NtkDelete( pMiter );
+        return NULL;
+    }
+    return pMiter;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Computing sensitivity of POs to POs under constaints.]
+
+  Description [The input network is a combinatonal AIG. The last output
+  is a constraint. The procedure returns the list of number of PIs, 
+  such that at least one PO depends on this PI, under the constraint.]
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Vec_Int_t * Abc_NtkSensitivity( Abc_Ntk_t * pNtk, int nConfLim, int fVerbose )
+{
+    ProgressBar * pProgress;
+    Prove_Params_t Params, * pParams = &Params;
+    Vec_Int_t * vResult = NULL;
+    Abc_Ntk_t * pMiter;
+    Abc_Obj_t * pObj;
+    int RetValue, i;
+    assert( Abc_NtkIsStrash(pNtk) );
+    assert( Abc_NtkLatchNum(pNtk) == 0 );
+    // set up solving parameters
+    Prove_ParamsSetDefault( pParams );
+    pParams->nItersMax = 3;
+    pParams->nMiteringLimitLast = nConfLim;
+    // iterate through the PIs
+    vResult = Vec_IntAlloc( 100 );
+    pProgress = Extra_ProgressBarStart( stdout, Abc_NtkCiNum(pNtk) );
+    Abc_NtkForEachCi( pNtk, pObj, i )
+    {
+        Extra_ProgressBarUpdate( pProgress, i, NULL );
+        // generate the sensitivity miter
+        pMiter = Abc_NtkSensitivityMiter( pNtk, i );
+        // solve the miter using CEC engine
+        RetValue = Abc_NtkIvyProve( &pMiter, pParams );
+        if ( RetValue == -1 ) // undecided
+            Vec_IntPush( vResult, i );
+        else if ( RetValue == 0 )
+        {
+            int * pSimInfo = Abc_NtkVerifySimulatePattern( pMiter, pMiter->pModel );
+            if ( pSimInfo[0] != 1 )
+                printf( "ERROR in Abc_NtkMiterProve(): Generated counter-example is invalid.\n" );
+//            else
+//                printf( "Networks are NOT EQUIVALENT.\n" );
+            free( pSimInfo );
+            Vec_IntPush( vResult, i );
+        }
+        Abc_NtkDelete( pMiter );
+    }
+    Extra_ProgressBarStop( pProgress );
+    if ( fVerbose )
+    {
+        printf( "The outputs are sensitive to %d (out of %d) inputs:\n", 
+            Vec_IntSize(vResult), Abc_NtkCiNum(pNtk) );
+        Vec_IntForEachEntry( vResult, RetValue, i )
+            printf( "%d ", RetValue );
+        printf( "\n" );
+    }
+    return vResult;
+}
+
+////////////////////////////////////////////////////////////////////////
+///                       END OF FILE                                ///
+////////////////////////////////////////////////////////////////////////
+
+

src/base/abci/module.make

@@ -48,6 +48,7 @@ SRC +=    src/base/abci/abc.c \
     src/base/abci/abcRewrite.c \
     src/base/abci/abcRr.c \
     src/base/abci/abcSat.c \
+    src/base/abci/abcSense.c \
     src/base/abci/abcStrash.c \
     src/base/abci/abcSweep.c \
     src/base/abci/abcSymm.c \

todo.txt

 - required time support
 - printing ABC version/platform in the output files  
-- fix gcc compiler warnings
-- port "mfs" from MVSIS
 - improve AIG rewriting package
-- unify functional representation of local functions
-- additional rewriting options for delay optimization
-- experiment with yield-aware standard-cell mapping
-- improving area recovery in integrated sequential synthesis 
 - high-effort logic synthesis for hard miters (cofactoring, Boolean division)
-- mapping into MV cells
 - SAT solver with linear constraints
 - specialized synthesis for EXORs and large MUXes
-- sequential AIG rewriting initial state computation
-- placement-aware mapping
-- sequential equivalence checking
 - parser for Verilog netlists
-- hierarchy manager (hierarchical BLIF/BLIF-MV parser)
 
 - required time based on all cuts
 - comparing tts of differently derived the same cut