Version abc81014

abc.dsp

@@ -3474,6 +3474,10 @@ SOURCE=.\src\aig\ssw\sswCore.c
 # End Source File
 # Begin Source File
 
+SOURCE=.\src\aig\ssw\sswDyn.c
+# End Source File
+# Begin Source File
+
 SOURCE=.\src\aig\ssw\sswInt.h
 # End Source File
 # Begin Source File

src/aig/aig/aig.h

@@ -634,6 +634,7 @@ extern int             Aig_ManLevels( Aig_Man_t * p );
 extern void            Aig_ManResetRefs( Aig_Man_t * p );
 extern void            Aig_ManCleanMarkA( Aig_Man_t * p );
 extern void            Aig_ManCleanMarkB( Aig_Man_t * p );
+extern void            Aig_ManCleanMarkAB( Aig_Man_t * p );
 extern void            Aig_ManCleanData( Aig_Man_t * p );
 extern void            Aig_ObjCleanData_rec( Aig_Obj_t * pObj );
 extern void            Aig_ObjCollectMulti( Aig_Obj_t * pFunc, Vec_Ptr_t * vSuper );

src/aig/aig/aigDfs.c

@@ -699,6 +699,8 @@ void Aig_Support_rec( Aig_Man_t * p, Aig_Obj_t * pObj, Vec_Ptr_t * vSupp )
     if ( Aig_ObjIsTravIdCurrent(p, pObj) )
         return;
     Aig_ObjSetTravIdCurrent(p, pObj);
+    if ( Aig_ObjIsConst1(pObj) )
+        return;
     if ( Aig_ObjIsPi(pObj) )
     {
         Vec_PtrPush( vSupp, pObj );

src/aig/aig/aigUtil.c

@@ -168,6 +168,25 @@ void Aig_ManCleanMarkB( Aig_Man_t * p )
 
 /**Function*************************************************************
 
+  Synopsis    [Cleans fMarkB.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Aig_ManCleanMarkAB( Aig_Man_t * p )
+{
+    Aig_Obj_t * pObj;
+    int i;
+    Aig_ManForEachObj( p, pObj, i )
+        pObj->fMarkA = pObj->fMarkB = 0;
+}
+
+/**Function*************************************************************
+
   Synopsis    [Cleans the data pointers for the nodes.]
 
   Description []

src/aig/fra/fra.h

@@ -118,6 +118,8 @@ struct Fra_Sec_t_
     int              nFramesMax;        // the max number of frames used for induction
     int              nBTLimit;          // the conflict limit at a node
     int              nBTLimitGlobal;    // the global conflict limit
+    int              nBTLimitInter;     // the conflict limit for interpolation
+    int              nBddVarsMax;       // the state space limit for BDD reachability
     int              nBddMax;           // the max number of BDD nodes
     int              nBddIterMax;       // the limit on the number of BDD iterations
     int              fPhaseAbstract;    // enables phase abstraction
@@ -361,7 +363,7 @@ extern int                 Fra_NodesAreClause( Fra_Man_t * p, Aig_Obj_t * pOld,
 extern int                 Fra_NodeIsConst( Fra_Man_t * p, Aig_Obj_t * pNew );
 /*=== fraSec.c ========================================================*/
 extern void                Fra_SecSetDefaultParams( Fra_Sec_t * p );
-extern int                 Fra_FraigSec( Aig_Man_t * p, Fra_Sec_t * pParSec );
+extern int                 Fra_FraigSec( Aig_Man_t * p, Fra_Sec_t * pParSec, Aig_Man_t ** ppResult );
 /*=== fraSim.c ========================================================*/
 extern int                 Fra_SmlNodeHash( Aig_Obj_t * pObj, int nTableSize );
 extern int                 Fra_SmlNodeIsConst( Aig_Obj_t * pObj );

src/aig/fra/fraInd.c

@@ -32,7 +32,7 @@
 
 /**Function*************************************************************
 
-  Synopsis    [Performs AIG rewriting on the constaint manager.]
+  Synopsis    [Performs AIG rewriting on the constraint manager.]
 
   Description []
                
@@ -536,7 +536,7 @@ p->timeTrav += clock() - clk2;
         // report the intermediate results
         if ( pPars->fVerbose )
         {
-            printf( "%3d : Const = %6d. Cl = %6d.  L = %6d. LR = %6d.  ", 
+            printf( "%3d : C = %6d. Cl = %6d.  L = %6d. LR = %6d.  ", 
                 nIter, Vec_PtrSize(p->pCla->vClasses1), Vec_PtrSize(p->pCla->vClasses), 
                 Fra_ClassesCountLits(p->pCla), p->pManFraig->nAsserts );
             if ( p->pCla->vImps )

src/aig/fra/fraSec.c

@@ -51,6 +51,8 @@ void Fra_SecSetDefaultParams( Fra_Sec_t * p )
     p->nFramesMax        =       4;  // the max number of frames used for induction
     p->nBTLimit          =    1000;  // conflict limit at a node during induction 
     p->nBTLimitGlobal    = 5000000;  // global conflict limit during induction
+    p->nBTLimitInter     =   10000;  // conflict limit during interpolation
+    p->nBddVarsMax       =     150;  // the limit on the number of registers in BDD reachability
     p->nBddMax           =   50000;  // the limit on the number of BDD nodes 
     p->nBddIterMax       = 1000000;  // the limit on the number of BDD iterations
     p->fPhaseAbstract    =       0;  // enables phase abstraction
@@ -81,7 +83,7 @@ void Fra_SecSetDefaultParams( Fra_Sec_t * p )
   SeeAlso     []
 
 ***********************************************************************/
-int Fra_FraigSec( Aig_Man_t * p, Fra_Sec_t * pParSec )
+int Fra_FraigSec( Aig_Man_t * p, Fra_Sec_t * pParSec, Aig_Man_t ** ppResult )
 {
     Ssw_Pars_t Pars2, * pPars2 = &Pars2;
     Fra_Ssw_t Pars, * pPars = &Pars;
@@ -461,6 +463,7 @@ clk = clock();
         int Depth;
 
         Inter_ManSetDefaultParams( pPars );
+        pPars->nBTLimit = pParSec->nBTLimitInter;
         pPars->fVerbose = pParSec->fVeryVerbose;
         if ( Saig_ManPoNum(pNew) == 1 )
         {
@@ -495,7 +498,7 @@ PRT( "Time", clock() - clk );
     }
 
     // try reachability analysis
-    if ( pParSec->fReachability && RetValue == -1 && Aig_ManRegNum(pNew) > 0 && Aig_ManRegNum(pNew) < 150 )
+    if ( pParSec->fReachability && RetValue == -1 && Aig_ManRegNum(pNew) > 0 && Aig_ManRegNum(pNew) < pParSec->nBddVarsMax )
     {
         extern int Aig_ManVerifyUsingBdds( Aig_Man_t * p, int nBddMax, int nIterMax, int fPartition, int fReorder, int fVerbose, int fSilent );
         pNew->nTruePis = Aig_ManPiNum(pNew) - Aig_ManRegNum(pNew); 
@@ -563,6 +566,8 @@ PRT( "Time", clock() - clkTotal );
         FREE( pNew->pSeqModel );
         }
     }
+    if ( ppResult != NULL )
+        *ppResult = Aig_ManDupSimpleDfs( pNew );
     if ( pNew )
         Aig_ManStop( pNew );
     return RetValue;

src/aig/mfx/mfxResub.c

@@ -463,6 +463,9 @@ int Mfx_ResubNode( Mfx_Man_t * p, Nwk_Obj_t * pNode )
     }
     if ( Nwk_ObjFaninNum(pNode) == p->nFaninMax )
         return 0;
+
+    return 0; /// !!!!! temporary workaround
+
     // try replacing area critical fanins while adding two new fanins
     Nwk_ObjForEachFanin( pNode, pFanin, i )
         if ( !Nwk_ObjIsCi(pFanin) && Nwk_ObjFanoutNum(pFanin) == 1 )

src/aig/ssw/module.make

@@ -3,6 +3,7 @@ SRC +=    src/aig/ssw/sswAig.c \
     src/aig/ssw/sswClass.c \
     src/aig/ssw/sswCnf.c \
     src/aig/ssw/sswCore.c \
+    src/aig/ssw/sswDyn.c \
     src/aig/ssw/sswLcorr.c \
     src/aig/ssw/sswMan.c \
     src/aig/ssw/sswPart.c \

src/aig/ssw/ssw.h

@@ -55,12 +55,16 @@ struct Ssw_Pars_t_
     int              fLatchCorr;    // perform register correspondence
     int              fSemiFormal;   // enable semiformal filtering
     int              fUniqueness;   // enable uniqueness constraints
+    int              fDynamic;      // enable dynamic addition of constraints
     int              fVerbose;      // verbose stats
     int              fFlopVerbose;  // verbose printout of redundant flops
     // optimized latch correspondence
     int              fLatchCorrOpt; // perform register correspondence (optimized)
     int              nSatVarMax;    // max number of SAT vars before recycling SAT solver (optimized latch corr only)
     int              nRecycleCalls; // calls to perform before recycling SAT solver (optimized latch corr only)
+    // optimized signal correspondence
+    int              nSatVarMax2;   // max number of SAT vars before recycling SAT solver (optimized latch corr only)
+    int              nRecycleCalls2;// calls to perform before recycling SAT solver (optimized latch corr only)
     // internal parameters
     int              nIters;        // the number of iterations performed
     int              nConflicts;    // the total number of conflicts performed

src/aig/ssw/sswClass.c

@@ -493,11 +493,22 @@ void Ssw_ClassesRemoveNode( Ssw_Cla_t * p, Aig_Obj_t * pObj )
 ***********************************************************************/
 Ssw_Cla_t * Ssw_ClassesPrepare( Aig_Man_t * pAig, int fLatchCorr, int nMaxLevs, int fVerbose )
 {
+//    int nFrames =  4;
+//    int nWords  =  1;
+//    int nIters  = 16;
+
+//    int nFrames = 32;
+//    int nWords  =  4;
+//    int nIters  =  0;
+
+    int nFrames =  4;
+    int nWords  =  2;
+    int nIters  = 16;
     Ssw_Cla_t * p;
     Ssw_Sml_t * pSml;
     Aig_Obj_t ** ppTable, ** ppNexts, ** ppClassNew;
     Aig_Obj_t * pObj, * pTemp, * pRepr;
-    int i, k, nTableSize, nNodes, iEntry, nEntries, nEntries2;
+    int i, k, nTableSize, nNodes, iEntry, nEntries, nEntries2, RetValue;
     int clk;
 
     // start the classes
@@ -505,10 +516,13 @@ Ssw_Cla_t * Ssw_ClassesPrepare( Aig_Man_t * pAig, int fLatchCorr, int nMaxLevs,
 
     // perform sequential simulation
 clk = clock();
-    pSml = Ssw_SmlSimulateSeq( pAig, 0, 32, 4 );
+    pSml = Ssw_SmlSimulateSeq( pAig, 0, nFrames, nWords );
 if ( fVerbose )
 {
-PRT( "Simulation of 32 frames with 4 words", clock() - clk );
+    printf( "Allocated %.2f Mb for simulation information.\n", 
+        1.0*(sizeof(unsigned) * Aig_ManObjNumMax(pAig) * nFrames * nWords)/(1<<20) );
+    printf( "Initial simulation of %d frames with %d words.     ", nFrames, nWords );
+    PRT( "Time", clock() - clk );
 }
 
     // set comparison procedures
@@ -603,13 +617,36 @@ clk = clock();
 
     // now it is time to refine the classes
     Ssw_ClassesRefine( p, 1 );
+if ( fVerbose )
+{
+    printf( "Collecting candidate equivalence classes.        " );
+PRT( "Time", clock() - clk );
+}
+
+clk = clock();
+    // perform iterative refinement using simulation
+    k = 0;
+    for ( i = 1; i < nIters; i++ )
+    {
+        Ssw_SmlResimulateSeq( pSml );
+        // simulate internal nodes
+        Ssw_SmlSimulateOne( pSml );
+        // check equivalence classes
+        RetValue = Ssw_ClassesRefineConst1( p, 1 );
+        RetValue += Ssw_ClassesRefine( p, 1 );
+        k++;
+        if ( RetValue == 0 )
+            break;
+    }
     Ssw_ClassesCheck( p );
     Ssw_SmlStop( pSml );
-//    Ssw_ClassesPrint( p, 0 );
 if ( fVerbose )
 {
-PRT( "Collecting candidate equival classes", clock() - clk );
+    printf( "Simulation of %d frames with %d words (%2d rounds). ", 
+        nFrames, nWords, k );
+    PRT( "Time", clock() - clk );
 }
+//    Ssw_ClassesPrint( p, 0 );
     return p;
 }
 

src/aig/ssw/sswCnf.c

@@ -77,6 +77,8 @@ Ssw_Sat_t * Ssw_SatStart( int fPolarFlip )
 ***********************************************************************/
 void Ssw_SatStop( Ssw_Sat_t * p )
 {
+//    printf( "Recycling SAT solver with %d vars and %d restarts.\n", 
+//        p->pSat->size, p->pSat->stats.starts );
     if ( p->pSat )
         sat_solver_delete( p->pSat );
     Vec_IntFree( p->vSatVars );

src/aig/ssw/sswCore.c

@@ -60,6 +60,9 @@ void Ssw_ManSetDefaultParams( Ssw_Pars_t * p )
     p->fLatchCorrOpt  =       0;  // performs optimized register correspondence
     p->nSatVarMax     =    1000;  // the max number of SAT variables
     p->nRecycleCalls  =      50;  // calls to perform before recycling SAT solver
+    // signal correspondence
+    p->nSatVarMax2    =    5000;  // the max number of SAT variables
+    p->nRecycleCalls2 =     250;  // calls to perform before recycling SAT solver
     // return values
     p->nIters         =       0;  // the number of iterations performed
 }
@@ -95,7 +98,7 @@ void Ssw_ManSetDefaultParamsLcorr( Ssw_Pars_t * p )
 ***********************************************************************/
 Aig_Man_t * Ssw_SignalCorrespondenceRefine( Ssw_Man_t * p )
 {
-    int nSatProof, nSatCallsSat, nRecycles, nSatFailsReal;
+    int nSatProof, nSatCallsSat, nRecycles, nSatFailsReal, nUniques;
     Aig_Man_t * pAigNew;
     int RetValue, nIter;
     int clk, clkTotal = clock();
@@ -137,7 +140,7 @@ Aig_Man_t * Ssw_SignalCorrespondenceRefine( Ssw_Man_t * p )
     }
 */
     // refine classes using induction
-    nSatProof = nSatCallsSat = nRecycles = nSatFailsReal = 0;
+    nSatProof = nSatCallsSat = nRecycles = nSatFailsReal = nUniques = 0;
     for ( nIter = 0; ; nIter++ )
     {
 clk = clock();
@@ -147,29 +150,44 @@ clk = clock();
             RetValue = Ssw_ManSweepLatch( p );
             if ( p->pPars->fVerbose )
             {
-                printf( "%3d : Const = %6d. Cl = %6d. Pr = %5d. Cex = %5d. Rcl = %3d. F = %3d. ", 
+                printf( "%3d : C =%7d. Cl =%7d. Pr =%6d. Cex =%5d. Rcl = %3d. F = %3d. ", 
                     nIter, Ssw_ClassesCand1Num(p->ppClasses), Ssw_ClassesClassNum(p->ppClasses), 
                     p->nSatProof-nSatProof, p->nSatCallsSat-nSatCallsSat, 
                     p->nRecycles-nRecycles, p->nSatFailsReal-nSatFailsReal );
                 PRT( "T", clock() - clk );
-                nSatProof     = p->nSatProof;
-                nSatCallsSat  = p->nSatCallsSat;
-                nRecycles     = p->nRecycles;
-                nSatFailsReal = p->nSatFailsReal;
             } 
         }
         else
         {
+            if ( p->pPars->fDynamic )
+                RetValue = Ssw_ManSweepDyn( p );
+            else
                 RetValue = Ssw_ManSweep( p );
             p->pPars->nConflicts += p->pMSat->pSat->stats.conflicts;
             if ( p->pPars->fVerbose )
             {
-                printf( "%3d : Const = %6d. Cl = %6d. LR = %6d. NR = %6d. U = %3d. F = %2d. ", 
+                printf( "%3d : C =%7d. Cl =%7d. LR =%6d. NR =%6d. ", 
                     nIter, Ssw_ClassesCand1Num(p->ppClasses), Ssw_ClassesClassNum(p->ppClasses), 
-                    p->nConstrReduced, Aig_ManNodeNum(p->pFrames), p->nUniques, p->nSatFailsReal );
+                    p->nConstrReduced, Aig_ManNodeNum(p->pFrames) );
+                if ( p->pPars->fUniqueness )
+                    printf( "U =%4d. ", p->nUniques-nUniques );
+                else if ( p->pPars->fDynamic )
+                {
+                    printf( "Cex =%5d. ", p->nSatCallsSat-nSatCallsSat );
+                    printf( "R =%3d. ",   p->nRecycles-nRecycles );
+                }
+                printf( "F =%3d. ", p->nSatFailsReal-nSatFailsReal );
                 PRT( "T", clock() - clk );
             } 
         }
+        nSatProof     = p->nSatProof;
+        nSatCallsSat  = p->nSatCallsSat;
+        nRecycles     = p->nRecycles;
+        nSatFailsReal = p->nSatFailsReal;
+        nUniques      = p->nUniques;
+
+        p->nVarsMax  = AIG_MAX( p->nVarsMax,  p->pMSat->nSatVars );
+        p->nCallsMax = AIG_MAX( p->nCallsMax, p->pMSat->nSolverCalls );
         Ssw_SatStop( p->pMSat );
         p->pMSat = NULL;
         Ssw_ManCleanup( p );
@@ -234,13 +252,12 @@ Aig_Man_t * Ssw_SignalCorrespondence( Aig_Man_t * pAig, Ssw_Pars_t * pPars )
     {
         pPars->nFramesAddSim = 0;
         if ( pPars->nFramesK != 2 )
-            printf( "Setting K = 2 for uniqueness constaints to work.\n" );
+            printf( "Setting K = 2 for uniqueness constraints to work.\n" );
         pPars->nFramesK = 2;
     }
     if ( pPars->fLatchCorrOpt )
     {
         pPars->fLatchCorr = 1;
-        pPars->nFramesAddSim = 0;
     }
     else
     {
@@ -259,7 +276,12 @@ Aig_Man_t * Ssw_SignalCorrespondence( Aig_Man_t * pAig, Ssw_Pars_t * pPars )
         // perform one round of seq simulation and generate candidate equivalence classes
         p->ppClasses = Ssw_ClassesPrepare( pAig, pPars->fLatchCorr, pPars->nMaxLevs, pPars->fVerbose );
 //        p->ppClasses = Ssw_ClassesPrepareTargets( pAig );
+        if ( pPars->fLatchCorrOpt )
+            p->pSml = Ssw_SmlStart( pAig, 0, 2, 1 );
+        else if ( pPars->fDynamic )
             p->pSml = Ssw_SmlStart( pAig, 0, p->nFrames + p->pPars->nFramesAddSim, 1 );
+        else
+            p->pSml = Ssw_SmlStart( pAig, 0, 1 + p->pPars->nFramesAddSim, 1 );
         Ssw_ClassesSetData( p->ppClasses, p->pSml, Ssw_SmlObjHashWord, Ssw_SmlObjIsConstWord, Ssw_SmlObjsAreEqualWord );
     }
     else
@@ -271,7 +293,7 @@ Aig_Man_t * Ssw_SignalCorrespondence( Aig_Man_t * pAig, Ssw_Pars_t * pPars )
     // perform refinement of classes
     pAigNew = Ssw_SignalCorrespondenceRefine( p );    
     if ( pPars->fUniqueness )
-        printf( "Uniqueness constaint = %3d. Prevented counter-examples = %3d.\n", 
+        printf( "Uniqueness constraints = %3d. Prevented counter-examples = %3d.\n", 
             p->nUniquesAdded, p->nUniquesUseful );
     // cleanup
     Ssw_ManStop( p );

src/aig/ssw/sswInt.h

@@ -72,14 +72,20 @@ struct Ssw_Man_t_
     int              nCallsUnsat;    // the number of UNSAT calls in this round
     int              nRecycleCalls;  // the number of calls since last recycling
     int              nRecycles;      // the number of time SAT solver was recycled
-    int              nConeMax;       // the maximum cone size
+    int              nRecyclesTotal; // the number of time SAT solver was recycled
+    int              nVarsMax;       // the maximum variables in the solver
+    int              nCallsMax;      // the maximum number of SAT calls
     // uniqueness
     Vec_Ptr_t *      vCommon;        // the set of common variables in the logic cones
-    int              iOutputLit;     // the output literal of the uniqueness constaint
+    int              iOutputLit;     // the output literal of the uniqueness constraint
     Vec_Int_t *      vDiffPairs;     // is set to 1 if reg pair can be diff
-    int              nUniques;       // the number of uniqueness constaints used 
+    int              nUniques;       // the number of uniqueness constraints used 
     int              nUniquesAdded;  // useful uniqueness constraints
     int              nUniquesUseful; // useful uniqueness constraints
+    // dynamic constraint addition
+    int              nSRMiterMaxId;  // max ID after which the last frame begins
+    Vec_Ptr_t *      vNewLos;        // new time frame LOs of to constrain
+    Vec_Int_t *      vNewPos;        // new time frame POs of to add constraints
     // sequential simulator
     Ssw_Sml_t *      pSml;
     // counter example storage
@@ -93,7 +99,6 @@ struct Ssw_Man_t_
     int              nSatCalls;      // the number of SAT calls
     int              nSatProof;      // the number of proofs
     int              nSatFailsReal;  // the number of timeouts
-    int              nSatFailsTotal; // the number of timeouts
     int              nSatCallsUnsat; // the number of unsat SAT calls
     int              nSatCallsSat;   // the number of sat SAT calls
     // node/register/lit statistics
@@ -124,9 +129,9 @@ struct Ssw_Sat_t_
     sat_solver *     pSat;           // recyclable SAT solver
     int              nSatVars;       // the counter of SAT variables
     Vec_Int_t *      vSatVars;       // mapping of each node into its SAT var
-    int              nSatVarsTotal;  // the total number of SAT vars created
     Vec_Ptr_t *      vFanins;        // fanins of the CNF node
     Vec_Ptr_t *      vUsedPis;       // the PIs with SAT variables 
+    int              nSolverCalls;   // the total number of SAT calls
 };
 
 // internal frames manager
@@ -211,6 +216,9 @@ extern void          Ssw_CnfNodeAddToSolver( Ssw_Sat_t * p, Aig_Obj_t * pObj );
 extern int           Ssw_CnfGetNodeValue( Ssw_Sat_t * p, Aig_Obj_t * pObjFraig );
 /*=== sswCore.c ===================================================*/
 extern Aig_Man_t *   Ssw_SignalCorrespondenceRefine( Ssw_Man_t * p );
+/*=== sswDyn.c ===================================================*/
+extern void          Ssw_ManLoadSolver( Ssw_Man_t * p, Aig_Obj_t * pRepr, Aig_Obj_t * pObj );
+extern int           Ssw_ManSweepDyn( Ssw_Man_t * p );
 /*=== sswLcorr.c ==========================================================*/
 extern int           Ssw_ManSweepLatch( Ssw_Man_t * p );
 /*=== sswMan.c ===================================================*/
@@ -229,15 +237,18 @@ extern int           Ssw_SmlObjIsConstWord( Ssw_Sml_t * p, Aig_Obj_t * pObj );
 extern int           Ssw_SmlObjsAreEqualWord( Ssw_Sml_t * p, Aig_Obj_t * pObj0, Aig_Obj_t * pObj1 );
 extern int           Ssw_SmlObjIsConstBit( void * p, Aig_Obj_t * pObj );
 extern int           Ssw_SmlObjsAreEqualBit( void * p, Aig_Obj_t * pObj0, Aig_Obj_t * pObj1 );
+extern void          Ssw_SmlAssignRandomFrame( Ssw_Sml_t * p, Aig_Obj_t * pObj, int iFrame );
 extern Ssw_Sml_t *   Ssw_SmlStart( Aig_Man_t * pAig, int nPref, int nFrames, int nWordsFrame );
 extern void          Ssw_SmlClean( Ssw_Sml_t * p );
 extern void          Ssw_SmlStop( Ssw_Sml_t * p );
+extern int           Ssw_SmlNumFrames( Ssw_Sml_t * p );
 extern void          Ssw_SmlObjAssignConst( Ssw_Sml_t * p, Aig_Obj_t * pObj, int fConst1, int iFrame );
 extern void          Ssw_SmlObjSetWord( Ssw_Sml_t * p, Aig_Obj_t * pObj, unsigned Word, int iWord, int iFrame );
 extern void          Ssw_SmlAssignDist1Plus( Ssw_Sml_t * p, unsigned * pPat );
 extern void          Ssw_SmlSimulateOne( Ssw_Sml_t * p );
 extern void          Ssw_SmlSimulateOneFrame( Ssw_Sml_t * p );
 extern Ssw_Sml_t *   Ssw_SmlSimulateSeq( Aig_Man_t * pAig, int nPref, int nFrames, int nWords );
+extern void          Ssw_SmlResimulateSeq( Ssw_Sml_t * p );
 /*=== sswSimSat.c ===================================================*/
 extern void          Ssw_ManResimulateBit( Ssw_Man_t * p, Aig_Obj_t * pObj, Aig_Obj_t * pRepr );
 extern void          Ssw_ManResimulateWord( Ssw_Man_t * p, Aig_Obj_t * pCand, Aig_Obj_t * pRepr, int f );
@@ -248,7 +259,7 @@ extern int           Ssw_ManSweepBmc( Ssw_Man_t * p );
 extern int           Ssw_ManSweep( Ssw_Man_t * p );
 /*=== sswUnique.c ===================================================*/
 extern void          Ssw_UniqueRegisterPairInfo( Ssw_Man_t * p );
-extern int           Ssw_ManUniqueOne( Ssw_Man_t * p, Aig_Obj_t * pRepr, Aig_Obj_t * pObj );
+extern int           Ssw_ManUniqueOne( Ssw_Man_t * p, Aig_Obj_t * pRepr, Aig_Obj_t * pObj, int fVerbose );
 extern int           Ssw_ManUniqueAddConstraint( Ssw_Man_t * p, Vec_Ptr_t * vCommon, int f1, int f2 );
 
 #ifdef __cplusplus

src/aig/ssw/sswLcorr.c

@@ -300,6 +300,8 @@ int Ssw_ManSweepLatch( Ssw_Man_t * p )
              p->pMSat->nSatVars > p->pPars->nSatVarMax &&
              p->nRecycleCalls > p->pPars->nRecycleCalls )
         {
+            p->nVarsMax  = AIG_MAX( p->nVarsMax,  p->pMSat->nSatVars );
+            p->nCallsMax = AIG_MAX( p->nCallsMax, p->pMSat->nSolverCalls );
             Ssw_SatStop( p->pMSat );
             p->pMSat = Ssw_SatStart( 0 );
             p->nRecycles++;
@@ -311,7 +313,6 @@ int Ssw_ManSweepLatch( Ssw_Man_t * p )
         Ssw_ManSweepResimulate( p );
     // cleanup
     Vec_PtrFree( vClass );
-    p->nSatFailsTotal += p->nSatFailsReal;
 //    if ( p->pPars->fVerbose )
 //        Bar_ProgressStop( pProgress );
 

src/aig/ssw/sswMan.c

@@ -58,6 +58,9 @@ Ssw_Man_t * Ssw_ManCreate( Aig_Man_t * pAig, Ssw_Pars_t * pPars )
     // allocate storage for sim pattern
     p->nPatWords     = Aig_BitWordNum( Saig_ManPiNum(pAig) * p->nFrames + Saig_ManRegNum(pAig) );
     p->pPatWords     = ALLOC( unsigned, p->nPatWords ); 
+    // other
+    p->vNewLos       = Vec_PtrAlloc( 100 );
+    p->vNewPos       = Vec_IntAlloc( 100 );
     return p;
 }
 
@@ -101,10 +104,10 @@ void Ssw_ManPrintStats( Ssw_Man_t * p )
     printf( "AIG       : PI = %d. PO = %d. Latch = %d. Node = %d.  Ave SAT vars = %d.\n", 
         Saig_ManPiNum(p->pAig), Saig_ManPoNum(p->pAig), Saig_ManRegNum(p->pAig), Aig_ManNodeNum(p->pAig), 
         0/p->pPars->nIters );
-    printf( "SAT calls : Proof = %d. Cex = %d. Fail = %d. Equivs = %d. Str = %d.\n", 
-        p->nSatProof, p->nSatCallsSat, p->nSatFailsTotal, Ssw_ManCountEquivs(p), p->nStrangers );
-    printf( "SAT solver: Vars = %d. Max cone = %d. Recycles = %d. Rounds = %d.\n", 
-        0, p->nConeMax, p->nRecycles, p->nSimRounds );
+    printf( "SAT calls : Proof = %d. Cex = %d. Fail = %d. Lits proved = %d.\n", 
+        p->nSatProof, p->nSatCallsSat, p->nSatFailsReal, Ssw_ManCountEquivs(p) );
+    printf( "SAT solver: Vars max = %d. Calls max = %d. Recycles = %d. Sim rounds = %d.\n", 
+        p->nVarsMax, p->nCallsMax, p->nRecyclesTotal, p->nSimRounds );
     printf( "NBeg = %d. NEnd = %d. (Gain = %6.2f %%).  RBeg = %d. REnd = %d. (Gain = %6.2f %%).\n", 
         p->nNodesBeg, p->nNodesEnd, 100.0*(p->nNodesBeg-p->nNodesEnd)/(p->nNodesBeg?p->nNodesBeg:1), 
         p->nRegsBeg, p->nRegsEnd, 100.0*(p->nRegsBeg-p->nRegsEnd)/(p->nRegsBeg?p->nRegsBeg:1) );
@@ -135,10 +138,11 @@ void Ssw_ManPrintStats( Ssw_Man_t * p )
 ***********************************************************************/
 void Ssw_ManCleanup( Ssw_Man_t * p )
 {
+//    Aig_ManCleanMarkAB( p->pAig );
     assert( p->pMSat == NULL );
     if ( p->pFrames )
     {
-        Aig_ManCleanMarkA( p->pFrames );
+        Aig_ManCleanMarkAB( p->pFrames );
         Aig_ManStop( p->pFrames );
         p->pFrames = NULL;
         memset( p->pNodeToFrames, 0, sizeof(Aig_Obj_t *) * Aig_ManObjNumMax(p->pAig) * p->nFrames );
@@ -165,8 +169,6 @@ void Ssw_ManCleanup( Ssw_Man_t * p )
 ***********************************************************************/
 void Ssw_ManStop( Ssw_Man_t * p )
 {
-    Aig_ManCleanMarkA( p->pAig );
-    Aig_ManCleanMarkB( p->pAig );
     if ( p->pPars->fVerbose )
         Ssw_ManPrintStats( p );
     if ( p->ppClasses )
@@ -175,6 +177,8 @@ void Ssw_ManStop( Ssw_Man_t * p )
         Ssw_SmlStop( p->pSml );
     if ( p->vDiffPairs )
         Vec_IntFree( p->vDiffPairs );
+    Vec_PtrFree( p->vNewLos );
+    Vec_IntFree( p->vNewPos );
     Vec_PtrFree( p->vCommon );
     FREE( p->pNodeToFrames );
     FREE( p->pPatWords );

src/aig/ssw/sswSat.c

@@ -44,6 +44,7 @@ int Ssw_NodesAreEquiv( Ssw_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t * pNew )
     int nBTLimit = p->pPars->nBTLimit;
     int pLits[3], nLits, RetValue, RetValue1, clk;//, status;
     p->nSatCalls++;
+    p->pMSat->nSolverCalls++;
 
     // sanity checks
     assert( !Aig_IsComplement(pOld) );
@@ -231,7 +232,7 @@ int Ssw_NodesAreConstrained( Ssw_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t * pNew )
     // consider the constant 1 case
     if ( pOld == Aig_ManConst1(p->pFrames) )
     {
-        // add constaint A = 1  ---->  A
+        // add constraint A = 1  ---->  A
         pLits[0] = toLitCond( Ssw_ObjSatNum(p->pMSat,pNew), fComplNew );
         if ( p->pPars->fPolarFlip )
         {
@@ -242,7 +243,7 @@ int Ssw_NodesAreConstrained( Ssw_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t * pNew )
     }
     else
     {
-        // add constaint A = B  ---->  (A v !B)(!A v B)
+        // add constraint A = B  ---->  (A v !B)(!A v B)
 
         // (A v !B)
         pLits[0] = toLitCond( Ssw_ObjSatNum(p->pMSat,pOld), 0 );

src/aig/ssw/sswSemi.c

@@ -267,7 +267,7 @@ int Ssw_FilterUsingSemi( Ssw_Man_t * pMan, int fCheckTargets, int nConfMax, int
     }
     if ( fVerbose )
     {
-        printf( "AIG : Const = %6d. Cl = %6d. Nodes = %6d.  ConfMax = %6d. FramesMax = %6d.\n", 
+        printf( "AIG : C = %6d. Cl = %6d. Nodes = %6d.  ConfMax = %6d. FramesMax = %6d.\n", 
             Ssw_ClassesCand1Num(p->pMan->ppClasses), Ssw_ClassesClassNum(p->pMan->ppClasses), 
             Aig_ManNodeNum(p->pMan->pAig), p->nConfMax, p->nFramesSweep );
     } 
@@ -279,7 +279,7 @@ clk = clock();
         Frames = Ssw_ManFilterBmc( p, Iter, fCheckTargets );
         if ( fVerbose )
         {
-            printf( "%3d : Const = %6d. Cl = %6d. NR = %6d. F = %3d. C = %5d. P = %3d. %s ", 
+            printf( "%3d : C = %6d. Cl = %6d. NR = %6d. F = %3d. C = %5d. P = %3d. %s ", 
                 Iter, Ssw_ClassesCand1Num(p->pMan->ppClasses), Ssw_ClassesClassNum(p->pMan->ppClasses), 
                 Aig_ManNodeNum(p->pMan->pFrames), Frames, (int)p->pMan->pMSat->pSat->stats.conflicts, p->nPatterns, 
                 p->pMan->nSatFailsReal? "f" : " " );
@@ -300,7 +300,6 @@ clk = clock();
     pMan->nSatCalls = 0;
     pMan->nSatProof = 0;
     pMan->nSatFailsReal = 0; 
-    pMan->nSatFailsTotal = 0;
     pMan->nSatCallsUnsat = 0;
     pMan->nSatCallsSat = 0;  
     pMan->timeSimSat = 0;    

src/aig/ssw/sswSim.c

@@ -359,11 +359,15 @@ int * Ssw_SmlCheckOutput( Ssw_Sml_t * p )
 void Ssw_SmlAssignRandom( Ssw_Sml_t * p, Aig_Obj_t * pObj )
 {
     unsigned * pSims;
-    int i;
+    int i, f;
     assert( Aig_ObjIsPi(pObj) );
     pSims = Ssw_ObjSim( p, pObj->Id );
     for ( i = 0; i < p->nWordsTotal; i++ )
         pSims[i] = Ssw_ObjRandomSim();
+    // set the first bit 0 in each frame
+    assert( p->nWordsFrame * p->nFrames == p->nWordsTotal );
+    for ( f = 0; f < p->nFrames; f++ )
+        pSims[p->nWordsFrame*f] <<= 1;
 }
 
 /**Function*************************************************************
@@ -381,6 +385,7 @@ void Ssw_SmlAssignRandomFrame( Ssw_Sml_t * p, Aig_Obj_t * pObj, int iFrame )
 {
     unsigned * pSims;
     int i;
+    assert( iFrame < p->nFrames );
     assert( Aig_ObjIsPi(pObj) );
     pSims = Ssw_ObjSim( p, pObj->Id ) + p->nWordsFrame * iFrame;
     for ( i = 0; i < p->nWordsFrame; i++ )
@@ -402,6 +407,7 @@ void Ssw_SmlObjAssignConst( Ssw_Sml_t * p, Aig_Obj_t * pObj, int fConst1, int iF
 {
     unsigned * pSims;
     int i;
+    assert( iFrame < p->nFrames );
     assert( Aig_ObjIsPi(pObj) );
     pSims = Ssw_ObjSim( p, pObj->Id ) + p->nWordsFrame * iFrame;
     for ( i = 0; i < p->nWordsFrame; i++ )
@@ -422,6 +428,7 @@ void Ssw_SmlObjAssignConst( Ssw_Sml_t * p, Aig_Obj_t * pObj, int fConst1, int iF
 void Ssw_SmlObjSetWord( Ssw_Sml_t * p, Aig_Obj_t * pObj, unsigned Word, int iWord, int iFrame )
 {
     unsigned * pSims;
+    assert( iFrame < p->nFrames );
     assert( Aig_ObjIsPi(pObj) );
     pSims = Ssw_ObjSim( p, pObj->Id ) + p->nWordsFrame * iFrame;
     pSims[iWord] = Word;
@@ -429,39 +436,6 @@ void Ssw_SmlObjSetWord( Ssw_Sml_t * p, Aig_Obj_t * pObj, unsigned Word, int iWor
 
 /**Function*************************************************************
 
-  Synopsis    [Assings random simulation info for the PIs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Ssw_SmlInitialize( Ssw_Sml_t * p, int fInit )
-{
-    Aig_Obj_t * pObj;
-    int i;
-    if ( fInit )
-    {
-        assert( Aig_ManRegNum(p->pAig) > 0 );
-        assert( Aig_ManRegNum(p->pAig) < Aig_ManPiNum(p->pAig) );
-        // assign random info for primary inputs
-        Saig_ManForEachPi( p->pAig, pObj, i )
-            Ssw_SmlAssignRandom( p, pObj );
-        // assign the initial state for the latches
-        Saig_ManForEachLo( p->pAig, pObj, i )
-            Ssw_SmlObjAssignConst( p, pObj, 0, 0 );
-    }
-    else
-    {
-        Aig_ManForEachPi( p->pAig, pObj, i )
-            Ssw_SmlAssignRandom( p, pObj );
-    }
-}
-
-/**Function*************************************************************
-
   Synopsis    [Assings distance-1 simulation info for the PIs.]
 
   Description []
@@ -558,6 +532,7 @@ void Ssw_SmlNodeSimulate( Ssw_Sml_t * p, Aig_Obj_t * pObj, int iFrame )
 {
     unsigned * pSims, * pSims0, * pSims1;
     int fCompl, fCompl0, fCompl1, i;
+    assert( iFrame < p->nFrames );
     assert( !Aig_IsComplement(pObj) );
     assert( Aig_ObjIsNode(pObj) );
     assert( iFrame == 0 || p->nWordsFrame < p->nWordsTotal );
@@ -623,6 +598,8 @@ int Ssw_SmlNodesCompareInFrame( Ssw_Sml_t * p, Aig_Obj_t * pObj0, Aig_Obj_t * pO
 {
     unsigned * pSims0, * pSims1;
     int i;
+    assert( iFrame0 < p->nFrames );
+    assert( iFrame1 < p->nFrames );
     assert( !Aig_IsComplement(pObj0) );
     assert( !Aig_IsComplement(pObj1) );
     assert( iFrame0 == 0 || p->nWordsFrame < p->nWordsTotal );
@@ -652,6 +629,7 @@ void Ssw_SmlNodeCopyFanin( Ssw_Sml_t * p, Aig_Obj_t * pObj, int iFrame )
 {
     unsigned * pSims, * pSims0;
     int fCompl, fCompl0, i;
+    assert( iFrame < p->nFrames );
     assert( !Aig_IsComplement(pObj) );
     assert( Aig_ObjIsPo(pObj) );
     assert( iFrame == 0 || p->nWordsFrame < p->nWordsTotal );
@@ -685,6 +663,7 @@ void Ssw_SmlNodeTransferNext( Ssw_Sml_t * p, Aig_Obj_t * pOut, Aig_Obj_t * pIn,
 {
     unsigned * pSims0, * pSims1;
     int i;
+    assert( iFrame < p->nFrames );
     assert( !Aig_IsComplement(pOut) );
     assert( !Aig_IsComplement(pIn) );
     assert( Aig_ObjIsPo(pOut) );
@@ -698,6 +677,92 @@ void Ssw_SmlNodeTransferNext( Ssw_Sml_t * p, Aig_Obj_t * pOut, Aig_Obj_t * pIn,
         pSims1[i] = pSims0[i];
 }
 
+/**Function*************************************************************
+
+  Synopsis    [Simulates one node.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Ssw_SmlNodeTransferFirst( Ssw_Sml_t * p, Aig_Obj_t * pOut, Aig_Obj_t * pIn )
+{
+    unsigned * pSims0, * pSims1;
+    int i;
+    assert( !Aig_IsComplement(pOut) );
+    assert( !Aig_IsComplement(pIn) );
+    assert( Aig_ObjIsPo(pOut) );
+    assert( Aig_ObjIsPi(pIn) );
+    assert( p->nWordsFrame < p->nWordsTotal );
+    // get hold of the simulation information
+    pSims0 = Ssw_ObjSim(p, pOut->Id) + p->nWordsFrame * (p->nFrames-1);
+    pSims1 = Ssw_ObjSim(p, pIn->Id);
+    // copy information as it is
+    for ( i = 0; i < p->nWordsFrame; i++ )
+        pSims1[i] = pSims0[i];
+}
+
+
+/**Function*************************************************************
+
+  Synopsis    [Assings random simulation info for the PIs.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Ssw_SmlInitialize( Ssw_Sml_t * p, int fInit )
+{
+    Aig_Obj_t * pObj;
+    int i;
+    if ( fInit )
+    {
+        assert( Aig_ManRegNum(p->pAig) > 0 );
+        assert( Aig_ManRegNum(p->pAig) < Aig_ManPiNum(p->pAig) );
+        // assign random info for primary inputs
+        Saig_ManForEachPi( p->pAig, pObj, i )
+            Ssw_SmlAssignRandom( p, pObj );
+        // assign the initial state for the latches
+        Saig_ManForEachLo( p->pAig, pObj, i )
+            Ssw_SmlObjAssignConst( p, pObj, 0, 0 );
+    }
+    else
+    {
+        Aig_ManForEachPi( p->pAig, pObj, i )
+            Ssw_SmlAssignRandom( p, pObj );
+    }
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Assings random simulation info for the PIs.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Ssw_SmlReinitialize( Ssw_Sml_t * p )
+{
+    Aig_Obj_t * pObj, * pObjLi, * pObjLo;
+    int i;
+    assert( Aig_ManRegNum(p->pAig) > 0 );
+    assert( Aig_ManRegNum(p->pAig) < Aig_ManPiNum(p->pAig) );
+    // assign random info for primary inputs
+    Saig_ManForEachPi( p->pAig, pObj, i )
+        Ssw_SmlAssignRandom( p, pObj );
+    // copy simulation info into the inputs
+    Saig_ManForEachLiLo( p->pAig, pObjLi, pObjLo, i )
+        Ssw_SmlNodeTransferFirst( p, pObjLi, pObjLo );
+}
 
 /**Function*************************************************************
 
@@ -744,12 +809,12 @@ clk = clock();
         // copy simulation info into outputs
         Saig_ManForEachPo( p->pAig, pObj, i )
             Ssw_SmlNodeCopyFanin( p, pObj, f );
-        // quit if this is the last timeframe
-        if ( f == p->nFrames - 1 )
-            break;
         // copy simulation info into outputs
         Saig_ManForEachLi( p->pAig, pObj, i )
             Ssw_SmlNodeCopyFanin( p, pObj, f );
+        // quit if this is the last timeframe
+        if ( f == p->nFrames - 1 )
+            break;
         // copy simulation info into the inputs
         Saig_ManForEachLiLo( p->pAig, pObjLi, pObjLo, i )
             Ssw_SmlNodeTransferNext( p, pObjLi, pObjLo, f );
@@ -845,6 +910,22 @@ void Ssw_SmlStop( Ssw_Sml_t * p )
     free( p );
 }
 
+/**Function*************************************************************
+
+  Synopsis    [Deallocates simulation manager.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Ssw_SmlNumFrames( Ssw_Sml_t * p )
+{
+    return p->nFrames;
+}
+
 
 /**Function*************************************************************
 
@@ -887,6 +968,24 @@ Ssw_Sml_t * Ssw_SmlSimulateSeq( Aig_Man_t * pAig, int nPref, int nFrames, int nW
     return p;
 }
 
+/**Function*************************************************************
+
+  Synopsis    [Performs next round of sequential simulation.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Ssw_SmlResimulateSeq( Ssw_Sml_t * p )
+{
+    Ssw_SmlReinitialize( p );
+    Ssw_SmlSimulateOne( p );
+    p->fNonConstOut = Ssw_SmlCheckNonConstOutputs( p );
+}
+
 
 
 /**Function*************************************************************

src/aig/ssw/sswUnique.c

@@ -42,7 +42,7 @@
 void Ssw_UniqueRegisterPairInfo( Ssw_Man_t * p )
 {
     Aig_Obj_t * pObjLo, * pObj0, * pObj1;
-    int i;
+    int i, RetValue, Counter;
     if ( p->vDiffPairs == NULL )
         p->vDiffPairs = Vec_IntAlloc( Saig_ManRegNum(p->pAig) );
     Vec_IntClear( p->vDiffPairs );
@@ -54,13 +54,22 @@ void Ssw_UniqueRegisterPairInfo( Ssw_Man_t * p )
             Vec_IntPush( p->vDiffPairs, 0 );
         else if ( pObj0 == Aig_Not(pObj1) )
             Vec_IntPush( p->vDiffPairs, 1 );
+//        else
+//            Vec_IntPush( p->vDiffPairs, 1 );
+        else if ( Aig_ObjPhaseReal(pObj0) != Aig_ObjPhaseReal(pObj1) )
+            Vec_IntPush( p->vDiffPairs, 1 );
         else 
         {
-            // assume that if the nodes are structurally different
-            // they can also be functionally different
-            Vec_IntPush( p->vDiffPairs, 1 );
+            RetValue = Ssw_NodesAreEquiv( p, Aig_Regular(pObj0), Aig_Regular(pObj1) );
+            Vec_IntPush( p->vDiffPairs, RetValue!=1 );
         }
     }
+    assert( Vec_IntSize(p->vDiffPairs) == Saig_ManRegNum(p->pAig) );
+    // count the number of ones
+    Counter = 0;
+    Vec_IntForEachEntry( p->vDiffPairs, RetValue, i )
+        Counter += RetValue;
+//    printf( "The number of different register pairs = %d.\n", Counter );
 }
 
 
@@ -75,9 +84,8 @@ void Ssw_UniqueRegisterPairInfo( Ssw_Man_t * p )
   SeeAlso     []
 
 ***********************************************************************/
-int Ssw_ManUniqueOne( Ssw_Man_t * p, Aig_Obj_t * pRepr, Aig_Obj_t * pObj )
+int Ssw_ManUniqueOne( Ssw_Man_t * p, Aig_Obj_t * pRepr, Aig_Obj_t * pObj, int fVerbose )
 {
-    int fVerbose = 0;
     Aig_Obj_t * ppObjs[2], * pTemp;
     int i, k, Value0, Value1, RetValue, fFeasible;
 
@@ -93,8 +101,11 @@ int Ssw_ManUniqueOne( Ssw_Man_t * p, Aig_Obj_t * pRepr, Aig_Obj_t * pObj )
     fFeasible = 0;
     k = 0;
     Vec_PtrForEachEntry( p->vCommon, pTemp, i )
-        if ( Saig_ObjIsLo(p->pAig, pTemp) )
     {
+        assert( Aig_ObjIsPi(pTemp) );
+        if ( !Saig_ObjIsLo(p->pAig, pTemp) )
+            continue;
+        assert( Aig_ObjPioNum(pTemp) > 0 );
         Vec_PtrWriteEntry( p->vCommon, k++, pTemp );
         if ( Vec_IntEntry(p->vDiffPairs, Aig_ObjPioNum(pTemp) - Saig_ManPiNum(p->pAig)) )
             fFeasible = 1;

src/base/abci/abcDar.c

@@ -1694,7 +1694,7 @@ int Abc_NtkDarProve( Abc_Ntk_t * pNtk, Fra_Sec_t * pSecPar )
     }
     else
     {
-        RetValue = Fra_FraigSec( pMan, pSecPar );
+        RetValue = Fra_FraigSec( pMan, pSecPar, NULL );
         FREE( pNtk->pModel );
         FREE( pNtk->pSeqModel );
         pNtk->pSeqModel = pMan->pSeqModel; pMan->pSeqModel = NULL;
@@ -1793,7 +1793,7 @@ int Abc_NtkDarSec( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, Fra_Sec_t * pSecPar )
     assert( pMan->nRegs > 0 );
 
     // perform verification
-    RetValue = Fra_FraigSec( pMan, pSecPar );
+    RetValue = Fra_FraigSec( pMan, pSecPar, NULL );
     Aig_ManStop( pMan );
     return RetValue;
 }

src/base/abci/abcSense.c

@@ -140,7 +140,7 @@ Abc_Ntk_t * Abc_NtkSensitivityMiter( Abc_Ntk_t * pNtk, int iVar )
 
 /**Function*************************************************************
 
-  Synopsis    [Computing sensitivity of POs to POs under constaints.]
+  Synopsis    [Computing sensitivity of POs to POs under constraints.]
 
   Description [The input network is a combinatonal AIG. The last output
   is a constraint. The procedure returns the list of number of PIs, 

src/base/abci/abcSweep.c

@@ -88,6 +88,7 @@ bool Abc_NtkFraigSweep( Abc_Ntk_t * pNtk, int fUseInv, int fExdc, int fVerbose,
 
     // perform fraiging of the AIG
     Fraig_ParamsSetDefault( &Params );
+    Params.fInternal = 1;
     pMan = Abc_NtkToFraig( pNtkAig, &Params, 0, 0 );   
     // cannot use EXDC with FRAIG because it can create classes of equivalent FRAIG nodes
     // with representative nodes that do not correspond to the nodes with the current network

src/base/main/mainMC.c

@@ -107,7 +107,7 @@ int main( int argc, char * argv[] )
             pSecPar->fSilent         =   1;  // disable phase-abstraction
 
             Dar_LibStart();
-            RetValue = Fra_FraigSec( pAig, pSecPar );
+            RetValue = Fra_FraigSec( pAig, pSecPar, NULL );
             Dar_LibStop();
             Cnf_ClearMemory();
         }

src/map/mapper/mapperMatch.c

@@ -226,7 +226,7 @@ int Map_MatchNodePhase( Map_Man_t * p, Map_Node_t * pNode, int fPhase )
             Area2 = Map_SwitchCutRef( pNode, pNode->pCutBest[fPhase], fPhase );
         else 
             assert( 0 );
-        assert( Area2 < Area1 + p->fEpsilon );
+//        assert( Area2 < Area1 + p->fEpsilon );
     }
 
     // make sure that the requited times are met