Version abc60211

Makefile

@@ -10,7 +10,7 @@ MODULES := src/base/abc src/base/abci src/base/seq src/base/cmd src/base/io src/
            src/bdd/cudd src/bdd/dsd src/bdd/epd src/bdd/mtr src/bdd/parse src/bdd/reo \
            src/map/fpga src/map/pga src/map/mapper src/map/mio src/map/super \
            src/misc/extra src/misc/mvc src/misc/st src/misc/util src/misc/vec \
-	   src/opt/cut src/opt/dec src/opt/fxu src/opt/rwr src/opt/sim src/opt/xyz \
+	   src/opt/cut src/opt/dec src/opt/fxu src/opt/rwr src/opt/sim \
            src/sat/asat src/sat/csat src/sat/msat src/sat/fraig
 
 default: $(PROG)

abc.dsp

@@ -174,6 +174,10 @@ SOURCE=.\src\base\abci\abcAttach.c
 # End Source File
 # Begin Source File
 
+SOURCE=.\src\base\abci\abcAuto.c
+# End Source File
+# Begin Source File
+
 SOURCE=.\src\base\abci\abcBalance.c
 # End Source File
 # Begin Source File
@@ -210,10 +214,6 @@ SOURCE=.\src\base\abci\abcMiter.c
 # End Source File
 # Begin Source File
 
-SOURCE=.\src\base\abci\abcNewAig.c
-# End Source File
-# Begin Source File
-
 SOURCE=.\src\base\abci\abcNtbdd.c
 # End Source File
 # Begin Source File
@@ -262,6 +262,10 @@ SOURCE=.\src\base\abci\abcTiming.c
 # End Source File
 # Begin Source File
 
+SOURCE=.\src\base\abci\abcUnate.c
+# End Source File
+# Begin Source File
+
 SOURCE=.\src\base\abci\abcUnreach.c
 # End Source File
 # Begin Source File
@@ -1128,6 +1132,10 @@ SOURCE=.\src\sat\aig\fraigSolver.c
 
 SOURCE=.\src\sat\aig\fraigTrav.c
 # End Source File
+# Begin Source File
+
+SOURCE=.\src\sat\aig\rwrTruth.c
+# End Source File
 # End Group
 # End Group
 # Begin Group "opt"
@@ -1650,6 +1658,10 @@ SOURCE=.\src\misc\extra\extra.h
 # End Source File
 # Begin Source File
 
+SOURCE=.\src\misc\extra\extraBddAuto.c
+# End Source File
+# Begin Source File
+
 SOURCE=.\src\misc\extra\extraBddKmap.c
 # End Source File
 # Begin Source File
@@ -1662,6 +1674,10 @@ SOURCE=.\src\misc\extra\extraBddSymm.c
 # End Source File
 # Begin Source File
 
+SOURCE=.\src\misc\extra\extraBddUnate.c
+# End Source File
+# Begin Source File
+
 SOURCE=.\src\misc\extra\extraUtilBitMatrix.c
 # End Source File
 # Begin Source File

abc.rc

-# global parameters
-#set check         # checks intermediate networks
-#set checkfio      # prints warnings when fanins/fanouts are duplicated
-set checkread     # checks new networks after reading from file
-set backup        # saves backup networks retrived by "undo" and "recall"
-set savesteps 1   # sets the maximum number of backup networks to save
-
-# program names for internal calls
-set dotwin dot.exe
-set dotunix dot
-set gsviewwin gsview32.exe
-set gsviewunix gv
-set siswin sis.exe
-set sisunix sis
-set mvsiswin mvsis.exe
-set mvsisunix mvsis
-
-# standard aliases
-alias b balance
-alias cl cleanup
-alias clp collapse
-alias esd ext_seq_dcs
-alias f fraig
-alias fs fraig_sweep
-alias fsto fraig_store
-alias fres fraig_restore
-alias ft fraig_trust
-alias mu renode -m
-alias pex print_exdc -d
-alias pf print_factor
-alias pfan print_fanio
-alias pl print_level
-alias pio print_io
-alias pk print_kmap
-alias ps print_stats 
-alias psu print_supp
-alias psy print_symm
-alias q quit
-alias r read
-alias ren renode
-alias rl read_blif
-alias rb read_bench
-alias ret retime
-alias rp read_pla
-alias rv read_verilog
-alias rsup read_super mcnc5_old.super
-alias rlib read_library
-alias rw rewrite
-alias rwz rewrite -z
-alias rf refactor
-alias rfz refactor -z
-alias sa set autoexec ps
-alias so source -x
-alias st strash
-alias sw sweep
-alias ssw ssweep
-alias scl scleanup
-alias u undo
-alias wb write_blif
-alias wl write_blif
-alias wp write_pla
-alias wv write_verilog
-
-# standard scripts
-alias cnf       "st; ren -c; write_cnf"
-alias prove     "st; ren -c; sat"
-alias opt       "b; ren; b"
-alias share     "b; ren; fx; b"
-alias sharem    "b; ren -m; fx; b"
-alias sharedsd  "b; ren; dsd -g; sw; fx; b"
-alias resyn     "b; rw; rwz; b; rwz; b"
-alias resyn2    "b; rw; rf; b; rw; rwz; b; rfz; rwz; b"
-alias compress  "b; rw -l; rwz -l; b; rwz -l; b"
-alias compress2 "b; rw -l; rf -l; b; rw -l; rwz -l; b; rfz -l; rwz -l; b"
-alias choice    "fraig_store; resyn; fraig_store; resyn2; fraig_store; fraig_restore"
-alias choice2   "fraig_store; balance; fraig_store; resyn; fraig_store; resyn2; fraig_store; resyn2; fraig_store; fraig_restore"
-alias try       "st; fpga; miter; fraig -rp"
-

abctestlib.plg

-<html>
-<body>
-<pre>
-<h1>Build Log</h1>
-<h3>
---------------------Configuration: abctestlib - Win32 Release--------------------
-</h3>
-<h3>Command Lines</h3>
-Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP86.tmp" with contents
-[
-/nologo /ML /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /Fp"Release/abctestlib.pch" /YX /Fo"Release/" /Fd"Release/" /FD /c 
-"C:\_projects\abctestlib\demo.c"
-]
-Creating command line "cl.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP86.tmp" 
-Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP87.tmp" with contents
-[
-kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib C:\_projects\abc\abclib\abclib_release.lib /nologo /subsystem:console /incremental:no /pdb:"Release/abctestlib.pdb" /machine:I386 /out:"_TEST/abctestlib.exe" 
-.\Release\demo.obj
-]
-Creating command line "link.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP87.tmp"
-<h3>Output Window</h3>
-Compiling...
-demo.c
-Linking...
-
-
-
-<h3>Results</h3>
-abctestlib.exe - 0 error(s), 0 warning(s)
-</pre>
-</body>
-</html>

mcnc_temp.genlib_temp

-# The genlib library "mcnc_temp.genlib".
-GATE         inv1       1.00   O=!a;
-    PIN         a        INV      1    999   0.90   0.00   0.90   0.00
-GATE         inv2       2.00   O=!a;
-    PIN         a        INV      2    999   1.00   0.00   1.00   0.00
-GATE         inv3       3.00   O=!a;
-    PIN         a        INV      3    999   1.10   0.00   1.10   0.00
-GATE         inv4       4.00   O=!a;
-    PIN         a        INV      4    999   1.20   0.00   1.20   0.00
-GATE        nand2       2.00   O=!(a*b);
-    PIN         a        INV      1    999   1.00   0.00   1.00   0.00
-    PIN         b        INV      1    999   1.00   0.00   1.00   0.00
-GATE        nand3       3.00   O=!(a*b*c);
-    PIN         a        INV      1    999   1.10   0.00   1.10   0.00
-    PIN         b        INV      1    999   1.10   0.00   1.10   0.00
-    PIN         c        INV      1    999   1.10   0.00   1.10   0.00
-GATE        nand4       4.00   O=!(a*b*c*d);
-    PIN         a        INV      1    999   1.40   0.00   1.40   0.00
-    PIN         b        INV      1    999   1.40   0.00   1.40   0.00
-    PIN         c        INV      1    999   1.40   0.00   1.40   0.00
-    PIN         d        INV      1    999   1.40   0.00   1.40   0.00
-GATE         nor2       2.00   O=!(a+b);
-    PIN         a        INV      1    999   1.40   0.00   1.40   0.00
-    PIN         b        INV      1    999   1.40   0.00   1.40   0.00
-GATE         nor3       3.00   O=!(a+b+c);
-    PIN         a        INV      1    999   2.40   0.00   2.40   0.00
-    PIN         b        INV      1    999   2.40   0.00   2.40   0.00
-    PIN         c        INV      1    999   2.40   0.00   2.40   0.00
-GATE         nor4       4.00   O=!(a+b+c+d);
-    PIN         a        INV      1    999   3.80   0.00   3.80   0.00
-    PIN         b        INV      1    999   3.80   0.00   3.80   0.00
-    PIN         c        INV      1    999   3.80   0.00   3.80   0.00
-    PIN         d        INV      1    999   3.80   0.00   3.80   0.00
-GATE         xora       5.00   O=a*!b+!a*b;
-    PIN         a    UNKNOWN      2    999   1.90   0.00   1.90   0.00
-    PIN         b    UNKNOWN      2    999   1.90   0.00   1.90   0.00
-GATE         xorb       5.00   O=!(a*b+!a*!b);
-    PIN         a    UNKNOWN      2    999   1.90   0.00   1.90   0.00
-    PIN         b    UNKNOWN      2    999   1.90   0.00   1.90   0.00
-GATE        xnora       5.00   O=a*b+!a*!b;
-    PIN         a    UNKNOWN      2    999   2.10   0.00   2.10   0.00
-    PIN         b    UNKNOWN      2    999   2.10   0.00   2.10   0.00
-GATE        xnorb       5.00   O=!(!a*b+a*!b);
-    PIN         a    UNKNOWN      2    999   2.10   0.00   2.10   0.00
-    PIN         b    UNKNOWN      2    999   2.10   0.00   2.10   0.00
-GATE        aoi21       3.00   O=!(a*b+c);
-    PIN         a        INV      1    999   1.60   0.00   1.60   0.00
-    PIN         b        INV      1    999   1.60   0.00   1.60   0.00
-    PIN         c        INV      1    999   1.60   0.00   1.60   0.00
-GATE        aoi22       4.00   O=!(a*b+c*d);
-    PIN         a        INV      1    999   2.00   0.00   2.00   0.00
-    PIN         b        INV      1    999   2.00   0.00   2.00   0.00
-    PIN         c        INV      1    999   2.00   0.00   2.00   0.00
-    PIN         d        INV      1    999   2.00   0.00   2.00   0.00
-GATE        oai21       3.00   O=!((a+b)*c);
-    PIN         a        INV      1    999   1.60   0.00   1.60   0.00
-    PIN         b        INV      1    999   1.60   0.00   1.60   0.00
-    PIN         c        INV      1    999   1.60   0.00   1.60   0.00
-GATE        oai22       4.00   O=!((a+b)*(c+d));
-    PIN         a        INV      1    999   2.00   0.00   2.00   0.00
-    PIN         b        INV      1    999   2.00   0.00   2.00   0.00
-    PIN         c        INV      1    999   2.00   0.00   2.00   0.00
-    PIN         d        INV      1    999   2.00   0.00   2.00   0.00
-GATE          buf       1.00   O=a;
-    PIN         a     NONINV      1    999   1.00   0.00   1.00   0.00
-GATE         zero       0.00   O=CONST0;
-GATE          one       0.00   O=CONST1;

mcnc_temp.super

-#
-# Supergate library derived for "mcnc_temp.genlib_temp" on Sun Dec 25 06:29:48 2005.
-#
-# Command line: "super  -i 5  -l 1  -d 10000000.00  -a 10000000.00  -t 100    mcnc_temp.genlib_temp".
-#
-# The number of inputs      =          5.
-# The number of levels      =          1.
-# The maximum delay         = 10000000.00.
-# The maximum area          = 10000000.00.
-# The maximum runtime (sec) =        100.
-#
-# The number of attempts    =        860.
-# The number of supergates  =         20.
-# The number of functions   =          0.
-# The total functions       = 4294967296 (2^32).
-#
-# Generation time (sec)     =       0.01.
-#
-mcnc_temp.genlib_temp
-5
-20
-25       
-* xorb 1 0
-* nor4 2 1 0 3
-* nor3 2 1 0
-* oai22 2 1 0 3
-* oai22 2 0 1 3
-* aoi21 1 0 2
-* aoi22 2 3 1 0
-* nor2 1 0
-* oai22 2 3 1 0
-* aoi21 2 0 1
-* aoi22 2 0 1 3
-* aoi21 2 1 0
-* aoi22 2 1 0 3
-* oai21 1 0 2
-* oai21 2 0 1
-* oai21 2 1 0
-* nand2 1 0
-* nand3 2 1 0
-* nand4 2 1 0 3
-* xnora 1 0

regtest_output.txt

-UC Berkeley, ABC 1.01 (compiled Dec  3 2005 16:58:37)
+UC Berkeley, ABC 1.01 (compiled Feb  3 2006 10:48:34)
 abc 01> so regtest.script
 abc - > r examples/apex4.pla;    resyn; sharem; fpga; cec; ps;  clp; share; resyn; map; cec; ps
 Networks are equivalent after fraiging.
-examples/apex4: i/o =    9/  19  lat =    0  nd =  1182  cube =  2193  lev =   7
+examples/apex4: i/o =    9/  19  lat =    0  nd =  1185  cube =  2200  lev =   7
 The shared BDD size is 900 nodes.
 A simple supergate library is derived from gate library "mcnc_temp.genlib".
-Loaded 20 unique 5-input supergates from "mcnc_temp.super".  Time =   0.02 sec
+Loaded 20 unique 5-input supergates from "mcnc_temp.super".  Time =   0.03 sec
 Networks are equivalent after fraiging.
-examples/apex4: i/o =    9/  19  lat =    0  nd =  1849  area = 4581.00  delay = 11.60  lev =  11
+examples/apex4: i/o =    9/  19  lat =    0  nd =  1837  area = 4560.00  delay = 11.70  lev =  11
 abc - > r examples/C2670.blif;   resyn; fpga; cec; ps;          u; map; cec; ps
 Networks are equivalent after fraiging.
-C2670.iscas  : i/o =  233/ 140  lat =    0  nd =   219  cube =   446  lev =   7
+C2670.iscas  : i/o =  233/ 140  lat =    0  nd =   218  cube =   444  lev =   7
 Networks are equivalent after fraiging.
 C2670.iscas  : i/o =  233/ 140  lat =    0  nd =   466  area = 1160.00  delay = 15.50  lev =  14
 abc - > r examples/frg2.blif;    dsd; muxes; cec; clp; share; resyn; map; cec; ps
@@ -20,17 +20,17 @@ Networks are equivalent after fraiging.
 frg2         : i/o =  143/ 139  lat =    0  nd =   547  area = 1381.00  delay =  9.70  lev =   9
 abc - > r examples/pj1.blif;     resyn; fpga; cec; ps;          u; map; cec; ps
 Networks are equivalent after fraiging.
-exCombCkt    : i/o = 1769/1063  lat =    0  nd =  5611  cube = 10398  lev =  15
+exCombCkt    : i/o = 1769/1063  lat =    0  nd =  5609  cube = 10395  lev =  15
 Networks are equivalent after fraiging.
 exCombCkt    : i/o = 1769/1063  lat =    0  nd = 10317  area = 24980.00  delay = 29.80  lev =  27
 abc - > r examples/s38584.bench; resyn; fpga; cec; ps;          u; map; cec; ps
 Networks are equivalent after fraiging.
-examples/s38584: i/o =   12/ 278  lat = 1452  nd =  4411  cube =  7544  lev =   9
+examples/s38584: i/o =   12/ 278  lat = 1452  nd =  4405  cube =  7515  lev =   9
 Networks are equivalent after fraiging.
-examples/s38584: i/o =   12/ 278  lat = 1452  nd =  8510  area = 19315.00  delay = 20.60  lev =  17
+examples/s38584: i/o =   12/ 278  lat = 1452  nd =  8509  area = 19316.00  delay = 20.60  lev =  17
 abc - > r examples/ac.v;         resyn; fpga; cec; ps;          u; map; cec; ps
 Networks are equivalent after fraiging.
-ac97_ctrl    : i/o =   84/  48  lat = 2199  nd =  4086  cube =  7790  lev =   4
+ac97_ctrl    : i/o =   84/  48  lat = 2199  nd =  4085  cube =  7780  lev =   4
 Networks are equivalent after fraiging.
 ac97_ctrl    : i/o =   84/  48  lat = 2199  nd =  8278  area = 19714.00  delay =  8.10  lev =   8
 abc - > r examples/s444.blif;    b; esd -v; dsd; cec; ps
@@ -42,14 +42,14 @@ The number of minterms in the reachable state set = 8865.
 BDD nodes in the unreachable states before reordering 124.
 BDD nodes in the unreachable states after reordering 113.
 Networks are equivalent after fraiging.
-s444         : i/o =    3/   6  lat =   21  nd =    81  cube =   120  lev =   7
+s444         : i/o =    3/   6  lat =   21  nd =    81  cube =   119  lev =   7
 abc - > r examples/i10.blif;     fpga; cec; ps;                 u; map; cec; ps
 The network was strashed and balanced before FPGA mapping.
 Networks are equivalent after fraiging.
-i10          : i/o =  257/ 224  lat =    0  nd =   898  cube =  1603  lev =  13
+i10          : i/o =  257/ 224  lat =    0  nd =   899  cube =  1604  lev =  13
 The network was strashed and balanced before mapping.
 Networks are equivalent after fraiging.
-i10          : i/o =  257/ 224  lat =    0  nd =  1708  area = 4275.00  delay = 30.80  lev =  28
+i10          : i/o =  257/ 224  lat =    0  nd =  1676  area = 4219.00  delay = 30.80  lev =  29
 abc - > r examples/i10.blif;     choice; fpga; cec; ps;         u; map; cec; ps
 The number of AIG nodes added to storage =  2675.
 The number of AIG nodes added to storage =  1744.
@@ -57,21 +57,25 @@ The number of AIG nodes added to storage =  1431.
 Currently stored 3 networks with 5850 nodes will be fraiged.
 Performing FPGA mapping with choices.
 Networks are equivalent after fraiging.
-i10          : i/o =  257/ 224  lat =    0  nd =   793  cube =  1454  lev =  12
+i10          : i/o =  257/ 224  lat =    0  nd =   792  cube =  1459  lev =  12
 Performing mapping with choices.
 Networks are equivalent after fraiging.
-i10          : i/o =  257/ 224  lat =    0  nd =  1485  area = 3521.00  delay = 25.60  lev =  23
+i10          : i/o =  257/ 224  lat =    0  nd =  1484  area = 3518.00  delay = 25.60  lev =  23
 abc - > r examples/s6669.blif;   fpga; ps; sec; u;   sfpga; ps; sec; u;   fpga; ret; ps; sec
 The network was strashed and balanced before FPGA mapping.
-s6669        : i/o =   83/  55  lat =  239  nd =   678  bdd =  3036  lev =  20
+s6669        : i/o =   83/  55  lat =  239  nd =   679  bdd  =  3046  lev =  20
 Networks are equivalent after fraiging.
 The network was strashed and balanced before FPGA mapping/retiming.
-The number of LUTs with incompatible edges = 99.
-The number of LUTs with more than 4 inputs = 61.
-s6669        : i/o =   83/  55  lat =  451  nd =   865  bdd =  4221  lev =   6
+The number of MUXes detected = 120 (34.25 % of logic).  Creating solver =   0.00 sec
+SAT solver time =   0.00 sec
+The number of LUTs with incompatible edges = 24.
+The number of LUTs with more than 4 inputs = 18.
+s6669        : i/o =   83/  55  lat =  404  nd =   818  bdd  =  3829  lev =   6
 Networks are equivalent after fraiging.
 The network was strashed and balanced before FPGA mapping.
-s6669        : i/o =   83/  55  lat =  393  nd =   787  bdd =  3300  lev =   8
+The number of MUXes detected = 69 (37.03 % of logic).  Creating solver =   0.00 sec
+SAT solver time =   0.00 sec
+s6669        : i/o =   83/  55  lat =  346  nd =   772  bdd  =  3254  lev =   9
 Networks are equivalent after fraiging.
 abc - > r examples/s5378.blif;   map -s; ps; sec; u; smap; ps; sec; u;    map; ret; ps; sec
 The network was strashed and balanced before mapping.
@@ -81,10 +85,13 @@ The number of nodes with equal fanins = 5.
 The network was strashed and balanced before SC mapping/retiming.
 The mininum clock period computed is 10.00.
 The resulting network is derived as BDD logic network (this is temporary).
-s5378        : i/o =   35/  49  lat =  396  nd =  1252  bdd =  4619  lev =   7
+The number of MUXes detected = 0 ( 0.00 % of logic).  Creating solver =   0.00 sec
+SAT solver time =   0.00 sec
+s5378        : i/o =   35/  49  lat =  396  nd =  1252  bdd  =  4612  lev =   7
 Networks are equivalent after fraiging.
 The network was strashed and balanced before mapping.
-s5378        : i/o =   35/  49  lat =  364  nd =  1084  area = 2453.00  delay = 11.70  lev =  11
+s5378        : i/o =   35/  49  lat =  360  nd =  1087  area = 2454.00  delay = 12.10  lev =  11
 Networks are equivalent after fraiging.
 abc - > time
-elapse: 42.05 seconds, total: 42.05 seconds
+elapse: 39.54 seconds, total: 39.54 seconds
\ No newline at end of file
+abc 122>
\ No newline at end of file

src/base/abc/abc.h

@@ -425,7 +425,7 @@ extern void               Abc_AigSetNodePhases( Abc_Ntk_t * pNtk );
 /*=== abcAttach.c ==========================================================*/
 extern int                Abc_NtkAttach( Abc_Ntk_t * pNtk );
 /*=== abcBalance.c ==========================================================*/
-extern Abc_Ntk_t *        Abc_NtkBalance( Abc_Ntk_t * pNtk, bool fDuplicate );
+extern Abc_Ntk_t *        Abc_NtkBalance( Abc_Ntk_t * pNtk, bool fDuplicate, bool fSelective );
 /*=== abcCheck.c ==========================================================*/
 extern bool               Abc_NtkCheck( Abc_Ntk_t * pNtk );
 extern bool               Abc_NtkCheckRead( Abc_Ntk_t * pNtk );
@@ -587,6 +587,7 @@ extern DdNode *           Abc_NodeConeDcs( DdManager * dd, DdNode ** pbVarsX, Dd
 extern Vec_Ptr_t *        Abc_NodeCollectTfoCands( Abc_ManCut_t * p, Abc_Obj_t * pRoot, Vec_Ptr_t * vFanins, int LevelMax );
 /*=== abcRefs.c ==========================================================*/
 extern int                Abc_NodeMffcSize( Abc_Obj_t * pNode );
+extern int                Abc_NodeMffcSizeSupp( Abc_Obj_t * pNode );
 extern int                Abc_NodeMffcSizeStop( Abc_Obj_t * pNode );
 extern int                Abc_NodeMffcLabel( Abc_Obj_t * pNode );
 extern int                Abc_NodeMffcLabelFast( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes );
@@ -673,6 +674,7 @@ extern int                Abc_NtkGetChoiceNum( Abc_Ntk_t * pNtk );
 extern int                Abc_NtkGetFaninMax( Abc_Ntk_t * pNtk );
 extern void               Abc_NtkCleanCopy( Abc_Ntk_t * pNtk );
 extern void               Abc_NtkCleanNext( Abc_Ntk_t * pNtk );
+extern void               Abc_NtkCleanMarkA( Abc_Ntk_t * pNtk );
 extern Abc_Obj_t *        Abc_NodeHasUniqueCoFanout( Abc_Obj_t * pNode );
 extern bool               Abc_NtkLogicHasSimpleCos( Abc_Ntk_t * pNtk );
 extern int                Abc_NtkLogicMakeSimpleCos( Abc_Ntk_t * pNtk, bool fDuplicate );

src/base/abc/abcRefs.c

@@ -25,6 +25,7 @@
 ////////////////////////////////////////////////////////////////////////
 
 static int Abc_NodeRefDeref( Abc_Obj_t * pNode, bool fReference, bool fLabel, Vec_Ptr_t * vNodes );
+static int Abc_NodeMffcCountSupp( Vec_Ptr_t * vNodes );
 static int Abc_NodeRefDerefStop( Abc_Obj_t * pNode, bool fReference );
 static int Abc_NodeDeref( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes );
 
@@ -46,6 +47,7 @@ static int Abc_NodeDeref( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes );
 int Abc_NodeMffcSize( Abc_Obj_t * pNode )
 {
     int nConeSize1, nConeSize2;
+    assert( Abc_NtkIsStrash(pNode->pNtk) );
     assert( !Abc_ObjIsComplement( pNode ) );
     assert( Abc_ObjIsNode( pNode ) );
     if ( Abc_ObjFaninNum(pNode) == 0 )
@@ -59,6 +61,36 @@ int Abc_NodeMffcSize( Abc_Obj_t * pNode )
 
 /**Function*************************************************************
 
+  Synopsis    [Returns the MFFC size.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Abc_NodeMffcSizeSupp( Abc_Obj_t * pNode )
+{
+    Vec_Ptr_t * vNodes;
+    int nSuppSize, nConeSize1, nConeSize2;
+    assert( Abc_NtkIsStrash(pNode->pNtk) );
+    assert( !Abc_ObjIsComplement( pNode ) );
+    assert( Abc_ObjIsNode( pNode ) );
+    if ( Abc_ObjFaninNum(pNode) == 0 )
+        return 0;
+    vNodes = Vec_PtrAlloc( 10 );
+    nConeSize1 = Abc_NodeRefDeref( pNode, 0, 0, vNodes ); // dereference
+    nSuppSize = Abc_NodeMffcCountSupp(vNodes);
+    nConeSize2 = Abc_NodeRefDeref( pNode, 1, 0, NULL ); // reference
+    assert( nConeSize1 == nConeSize2 );
+    assert( nConeSize1 > 0 );
+    Vec_PtrFree(vNodes);
+    return nSuppSize;
+}
+
+/**Function*************************************************************
+
   Synopsis    [Returns the MFFC size while stopping at the complemented edges.]
 
   Description []
@@ -71,6 +103,7 @@ int Abc_NodeMffcSize( Abc_Obj_t * pNode )
 int Abc_NodeMffcSizeStop( Abc_Obj_t * pNode )
 {
     int nConeSize1, nConeSize2;
+    assert( Abc_NtkIsStrash(pNode->pNtk) );
     assert( !Abc_ObjIsComplement( pNode ) );
     assert( Abc_ObjIsNode( pNode ) );
     if ( Abc_ObjFaninNum(pNode) == 0 )
@@ -219,6 +252,61 @@ int Abc_NodeRefDeref( Abc_Obj_t * pNode, bool fReference, bool fLabel, Vec_Ptr_t
 
 /**Function*************************************************************
 
+  Synopsis    [References/references the node and returns MFFC supp size.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Abc_NodeMffcCountSupp( Vec_Ptr_t * vNodes )
+{
+    Abc_Obj_t * pNode, * pNode0, * pNode1;
+    int i, Counter = 0;
+    Vec_PtrForEachEntry( vNodes, pNode, i )
+    {
+        if ( Abc_ObjIsCi(pNode) )
+        {
+            if ( pNode->fMarkB == 0 )
+            {
+                pNode->fMarkB = 1;
+                Counter++;
+            }
+            continue;
+        }
+        pNode0 = Abc_ObjFanin0(pNode);
+        if ( pNode0->vFanouts.nSize > 0 && pNode0->fMarkB == 0 )
+        {
+            pNode0->fMarkB = 1;
+            Counter++;
+        }
+        pNode1 = Abc_ObjFanin1(pNode);
+        if ( pNode1->vFanouts.nSize > 0 && pNode1->fMarkB == 0 )
+        {
+            pNode1->fMarkB = 1;
+            Counter++;
+        }
+    }
+    Vec_PtrForEachEntry( vNodes, pNode, i )
+    {
+        if ( Abc_ObjIsCi(pNode) )
+        {
+            pNode->fMarkB = 0;
+            continue;
+        }
+        pNode0 = Abc_ObjFanin0(pNode);
+        pNode0->fMarkB = 0;
+        pNode1 = Abc_ObjFanin1(pNode);
+        pNode1->fMarkB = 0;
+    }
+    return Counter;
+
+}
+
+/**Function*************************************************************
+
   Synopsis    [References/references the node and returns MFFC size.]
 
   Description []

src/base/abc/abcSop.c

@@ -308,7 +308,7 @@ char * Abc_SopCreateXorSpecial( Extra_MmFlex_t * pMan, int nVars )
 char * Abc_SopCreateNxor( Extra_MmFlex_t * pMan, int nVars )
 {
     assert( nVars == 2 );
-    return Abc_SopRegister(pMan, "11 1\n11 1\n");
+    return Abc_SopRegister(pMan, "11 1\n00 1\n");
 }
 
 /**Function*************************************************************

src/base/abc/abcUtil.c

@@ -335,6 +335,25 @@ void Abc_NtkCleanNext( Abc_Ntk_t * pNtk )
 
 /**Function*************************************************************
 
+  Synopsis    [Cleans the copy field of all objects.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Abc_NtkCleanMarkA( Abc_Ntk_t * pNtk )
+{
+    Abc_Obj_t * pObj;
+    int i = 0;
+    Abc_NtkForEachObj( pNtk, pObj, i )
+        pObj->fMarkA = 0;
+}
+
+/**Function*************************************************************
+
   Synopsis    [Checks if the internal node has a unique CO.]
 
   Description [Checks if the internal node can borrow a name from a CO

src/base/abci/abcAuto.c

+/**CFile****************************************************************
+
+  FileName    [abcAuto.c]
+
+  SystemName  [ABC: Logic synthesis and verification system.]
+
+  PackageName [Network and node package.]
+
+  Synopsis    [Computation of autosymmetries.]
+
+  Author      [Alan Mishchenko]
+  
+  Affiliation [UC Berkeley]
+
+  Date        [Ver. 1.0. Started - June 20, 2005.]
+
+  Revision    [$Id: abcAuto.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
+
+***********************************************************************/
+
+#include "abc.h"
+
+////////////////////////////////////////////////////////////////////////
+///                        DECLARATIONS                              ///
+////////////////////////////////////////////////////////////////////////
+
+static void Abc_NtkAutoPrintAll( DdManager * dd, int nInputs, DdNode * pbOutputs[], int nOutputs, char * pInputNames[], char * pOutputNames[], int fNaive );
+static void Abc_NtkAutoPrintOne( DdManager * dd, int nInputs, DdNode * pbOutputs[], int Output, char * pInputNames[], char * pOutputNames[], int fNaive );
+ 
+////////////////////////////////////////////////////////////////////////
+///                     FUNCTION DEFINITIONS                         ///
+////////////////////////////////////////////////////////////////////////
+
+/**Function*************************************************************
+
+  Synopsis    []
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Abc_NtkAutoPrint( Abc_Ntk_t * pNtk, int Output, int fNaive, int fVerbose )
+{
+    DdManager * dd;         // the BDD manager used to hold shared BDDs
+    DdNode ** pbGlobal;     // temporary storage for global BDDs
+    char ** pInputNames;    // pointers to the CI names
+    char ** pOutputNames;   // pointers to the CO names
+    int nOutputs, nInputs, i;
+
+    // compute the global BDDs
+    if ( Abc_NtkGlobalBdds(pNtk, 0) == NULL )
+        return;
+
+    // get information about the network
+    nInputs  = Abc_NtkCiNum(pNtk);
+    nOutputs = Abc_NtkCoNum(pNtk);
+    dd       = pNtk->pManGlob;
+    pbGlobal = (DdNode **)Vec_PtrArray( pNtk->vFuncsGlob );
+
+    // get the network names
+    pInputNames = Abc_NtkCollectCioNames( pNtk, 0 );
+    pOutputNames = Abc_NtkCollectCioNames( pNtk, 1 );
+
+    // print the size of the BDDs
+    if ( fVerbose )
+        printf( "The shared BDD size is %d nodes.\n", Cudd_ReadKeys(dd) - Cudd_ReadDead(dd) );
+
+    // allocate additional variables
+    for ( i = 0; i < nInputs; i++ )
+        Cudd_bddNewVar( dd );
+    assert( Cudd_ReadSize(dd) == 2 * nInputs );
+
+    // create ZDD variables in the manager
+    Cudd_zddVarsFromBddVars( dd, 2 );
+
+    // perform the analysis of the primary output functions for auto-symmetry
+    if ( Output == -1 )
+        Abc_NtkAutoPrintAll( dd, nInputs, pbGlobal, nOutputs, pInputNames, pOutputNames, fNaive );
+    else
+        Abc_NtkAutoPrintOne( dd, nInputs, pbGlobal, Output, pInputNames, pOutputNames, fNaive );
+
+    // deref the PO functions
+    Abc_NtkFreeGlobalBdds( pNtk );
+    // stop the global BDD manager
+    Extra_StopManager( pNtk->pManGlob );
+    pNtk->pManGlob = NULL;
+    free( pInputNames );
+    free( pOutputNames );
+}
+
+/**Function*************************************************************
+
+  Synopsis    []
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Abc_NtkAutoPrintAll( DdManager * dd, int nInputs, DdNode * pbOutputs[], int nOutputs, char * pInputNames[], char * pOutputNames[], int fNaive )
+{
+    DdNode * bSpace1, * bSpace2, * bCanVars, * bReduced, * zEquations;
+    double nMints; 
+    int nSupp, SigCounter, o;
+
+    int nAutos;
+    int nAutoSyms;
+    int nAutoSymsMax;
+    int nAutoSymsMaxSupp;
+    int nAutoSymOuts;
+    int nSuppSizeMax;
+    int clk;
+    
+    nAutoSymOuts = 0;
+    nAutoSyms    = 0;
+    nAutoSymsMax = 0;
+    nAutoSymsMaxSupp = 0;
+    nSuppSizeMax = 0;
+    clk = clock();
+
+    SigCounter = 0;
+    for ( o = 0; o < nOutputs; o++ )
+    {
+        bSpace1  = Extra_bddSpaceFromFunctionFast( dd, pbOutputs[o] );           Cudd_Ref( bSpace1 );
+//        bSpace1  = Extra_bddSpaceFromFunction( dd, pbOutputs[o], pbOutputs[o] ); Cudd_Ref( bSpace1 );
+        bCanVars = Extra_bddSpaceCanonVars( dd, bSpace1 );                       Cudd_Ref( bCanVars );
+        bReduced = Extra_bddSpaceReduce( dd, pbOutputs[o], bCanVars );           Cudd_Ref( bReduced );
+        zEquations = Extra_bddSpaceEquations( dd, bSpace1 );                     Cudd_Ref( zEquations );
+
+        nSupp  = Cudd_SupportSize( dd, bSpace1 );
+        nMints = Cudd_CountMinterm( dd, bSpace1, nSupp );
+        nAutos = Extra_Base2LogDouble(nMints);
+        printf( "Output #%3d: Inputs = %2d. AutoK = %2d.\n", o, nSupp, nAutos );
+
+        if ( nAutos > 0 )
+        {
+            nAutoSymOuts++;
+            nAutoSyms += nAutos;
+            if ( nAutoSymsMax < nAutos )
+            {
+                nAutoSymsMax = nAutos;
+                nAutoSymsMaxSupp = nSupp;
+            }
+        }
+        if ( nSuppSizeMax < nSupp )
+            nSuppSizeMax = nSupp;
+
+
+//PRB( dd, bCanVars );
+//PRB( dd, bReduced );
+//Cudd_PrintMinterm( dd, bReduced );
+//printf( "The equations are:\n" );
+//Cudd_zddPrintCover( dd, zEquations );
+//printf( "\n" );
+//fflush( stdout );
+
+        bSpace2 = Extra_bddSpaceFromMatrixPos( dd, zEquations );   Cudd_Ref( bSpace2 );
+//PRB( dd, bSpace1 );
+//PRB( dd, bSpace2 );
+        if ( bSpace1 != bSpace2 )
+            printf( "Spaces are NOT EQUAL!\n" );
+//        else
+//            printf( "Spaces are equal.\n" );
+    
+        Cudd_RecursiveDeref( dd, bSpace1 );
+        Cudd_RecursiveDeref( dd, bSpace2 );
+        Cudd_RecursiveDeref( dd, bCanVars );
+        Cudd_RecursiveDeref( dd, bReduced );
+        Cudd_RecursiveDerefZdd( dd, zEquations );
+    }
+
+    printf( "The cumulative statistics for all outputs:\n" );
+    printf( "Ins=%3d ",      nInputs );
+    printf( "InMax=%3d   ",  nSuppSizeMax );
+    printf( "Outs=%3d ",     nOutputs );
+    printf( "Auto=%3d   ",   nAutoSymOuts );
+    printf( "SumK=%3d ",     nAutoSyms );
+    printf( "KMax=%2d ",     nAutoSymsMax );
+    printf( "Supp=%3d   ",   nAutoSymsMaxSupp );
+    printf( "Time=%4.2f ", (float)(clock() - clk)/(float)(CLOCKS_PER_SEC) );
+    printf( "\n" );
+}
+
+/**Function*************************************************************
+
+  Synopsis    []
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Abc_NtkAutoPrintOne( DdManager * dd, int nInputs, DdNode * pbOutputs[], int Output, char * pInputNames[], char * pOutputNames[], int fNaive )
+{
+    DdNode * bSpace1, * bCanVars, * bReduced, * zEquations;
+    double nMints; 
+    int nSupp, SigCounter;
+    int nAutos;
+
+    SigCounter = 0;
+    bSpace1  = Extra_bddSpaceFromFunctionFast( dd, pbOutputs[Output] );                Cudd_Ref( bSpace1 );
+//    bSpace1  = Extra_bddSpaceFromFunction( dd, pbOutputs[Output], pbOutputs[Output] ); Cudd_Ref( bSpace1 );
+    bCanVars = Extra_bddSpaceCanonVars( dd, bSpace1 );                                 Cudd_Ref( bCanVars );
+    bReduced = Extra_bddSpaceReduce( dd, pbOutputs[Output], bCanVars );                Cudd_Ref( bReduced );
+    zEquations = Extra_bddSpaceEquations( dd, bSpace1 );                               Cudd_Ref( zEquations );
+
+    nSupp  = Cudd_SupportSize( dd, bSpace1 );
+    nMints = Cudd_CountMinterm( dd, bSpace1, nSupp );
+    nAutos = Extra_Base2LogDouble(nMints);
+    printf( "Output #%3d: Inputs = %2d. AutoK = %2d.\n", Output, nSupp, nAutos );
+
+    Cudd_RecursiveDeref( dd, bSpace1 );
+    Cudd_RecursiveDeref( dd, bCanVars );
+    Cudd_RecursiveDeref( dd, bReduced );
+    Cudd_RecursiveDerefZdd( dd, zEquations );
+}
+
+////////////////////////////////////////////////////////////////////////
+///                       END OF FILE                                ///
+////////////////////////////////////////////////////////////////////////
+
+

src/base/abci/abcBalance.c

@@ -24,10 +24,11 @@
 ///                        DECLARATIONS                              ///
 ////////////////////////////////////////////////////////////////////////
  
-static void        Abc_NtkBalancePerform( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkAig, bool fDuplicate );
-static Abc_Obj_t * Abc_NodeBalance_rec( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNode, Vec_Vec_t * vStorage, int Level, bool fDuplicate );
-static Vec_Ptr_t * Abc_NodeBalanceCone( Abc_Obj_t * pNode, Vec_Vec_t * vSuper, int Level, int fDuplicate );
-static int         Abc_NodeBalanceCone_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vSuper, bool fFirst, bool fDuplicate );
+static void        Abc_NtkBalancePerform( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkAig, bool fDuplicate, bool fSelective );
+static Abc_Obj_t * Abc_NodeBalance_rec( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNode, Vec_Vec_t * vStorage, int Level, bool fDuplicate, bool fSelective );
+static Vec_Ptr_t * Abc_NodeBalanceCone( Abc_Obj_t * pNode, Vec_Vec_t * vSuper, int Level, int fDuplicate, bool fSelective );
+static int         Abc_NodeBalanceCone_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vSuper, bool fFirst, bool fDuplicate, bool fSelective );
+static void        Abc_NtkMarkCriticalNodes( Abc_Ntk_t * pNtk );
 
 ////////////////////////////////////////////////////////////////////////
 ///                     FUNCTION DEFINITIONS                         ///
@@ -44,14 +45,26 @@ static int         Abc_NodeBalanceCone_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vSupe
   SeeAlso     []
 
 ***********************************************************************/
-Abc_Ntk_t * Abc_NtkBalance( Abc_Ntk_t * pNtk, bool fDuplicate )
+Abc_Ntk_t * Abc_NtkBalance( Abc_Ntk_t * pNtk, bool fDuplicate, bool fSelective )
 {
     Abc_Ntk_t * pNtkAig;
     assert( Abc_NtkIsStrash(pNtk) );
+    // compute the required times
+    if ( fSelective )
+    {
+        Abc_NtkStartReverseLevels( pNtk );
+        Abc_NtkMarkCriticalNodes( pNtk );
+    }
     // perform balancing
     pNtkAig = Abc_NtkStartFrom( pNtk, ABC_NTK_STRASH, ABC_FUNC_AIG );
-    Abc_NtkBalancePerform( pNtk, pNtkAig, fDuplicate );
+    Abc_NtkBalancePerform( pNtk, pNtkAig, fDuplicate, fSelective );
     Abc_NtkFinalize( pNtk, pNtkAig );
+    // undo the required times
+    if ( fSelective )
+    {
+        Abc_NtkStopReverseLevels( pNtk );
+        Abc_NtkCleanMarkA( pNtk );
+    }
     if ( pNtk->pExdc )
         pNtkAig->pExdc = Abc_NtkDup( pNtk->pExdc );
     // make sure everything is okay
@@ -75,7 +88,7 @@ Abc_Ntk_t * Abc_NtkBalance( Abc_Ntk_t * pNtk, bool fDuplicate )
   SeeAlso     []
 
 ***********************************************************************/
-void Abc_NtkBalancePerform( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkAig, bool fDuplicate )
+void Abc_NtkBalancePerform( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkAig, bool fDuplicate, bool fSelective )
 {
     int fCheck = 1;
     ProgressBar * pProgress;
@@ -94,7 +107,7 @@ void Abc_NtkBalancePerform( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkAig, bool fDuplica
         Extra_ProgressBarUpdate( pProgress, i, NULL );
         // strash the driver node
         pDriver = Abc_ObjFanin0(pNode);
-        Abc_NodeBalance_rec( pNtkAig, pDriver, vStorage, 0, fDuplicate );
+        Abc_NodeBalance_rec( pNtkAig, pDriver, vStorage, 0, fDuplicate, fSelective );
     }
     Extra_ProgressBarStop( pProgress );
     Vec_VecFree( vStorage );
@@ -147,7 +160,7 @@ void Abc_NodeBalanceRandomize( Vec_Ptr_t * vSuper )
   SeeAlso     []
 
 ***********************************************************************/
-Abc_Obj_t * Abc_NodeBalance_rec( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNodeOld, Vec_Vec_t * vStorage, int Level, bool fDuplicate )
+Abc_Obj_t * Abc_NodeBalance_rec( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNodeOld, Vec_Vec_t * vStorage, int Level, bool fDuplicate, bool fSelective )
 {
     Abc_Aig_t * pMan = pNtkNew->pManFunc;
     Abc_Obj_t * pNodeNew, * pNode1, * pNode2;
@@ -159,7 +172,7 @@ Abc_Obj_t * Abc_NodeBalance_rec( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNodeOld, Vec_
         return pNodeOld->pCopy;
     assert( Abc_ObjIsNode(pNodeOld) );
     // get the implication supergate
-    vSuper = Abc_NodeBalanceCone( pNodeOld, vStorage, Level, fDuplicate );
+    vSuper = Abc_NodeBalanceCone( pNodeOld, vStorage, Level, fDuplicate, fSelective );
     if ( vSuper->nSize == 0 )
     { // it means that the supergate contains two nodes in the opposite polarity
         pNodeOld->pCopy = Abc_ObjNot(Abc_NtkConst1(pNtkNew));
@@ -168,7 +181,7 @@ Abc_Obj_t * Abc_NodeBalance_rec( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNodeOld, Vec_
     // for each old node, derive the new well-balanced node
     for ( i = 0; i < vSuper->nSize; i++ )
     {
-        pNodeNew = Abc_NodeBalance_rec( pNtkNew, Abc_ObjRegular(vSuper->pArray[i]), vStorage, Level + 1, fDuplicate );
+        pNodeNew = Abc_NodeBalance_rec( pNtkNew, Abc_ObjRegular(vSuper->pArray[i]), vStorage, Level + 1, fDuplicate, fSelective );
         vSuper->pArray[i] = Abc_ObjNotCond( pNodeNew, Abc_ObjIsComplement(vSuper->pArray[i]) );
     }
     if ( vSuper->nSize < 2 )
@@ -207,7 +220,7 @@ Abc_Obj_t * Abc_NodeBalance_rec( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNodeOld, Vec_
   SeeAlso     []
 
 ***********************************************************************/
-Vec_Ptr_t * Abc_NodeBalanceCone( Abc_Obj_t * pNode, Vec_Vec_t * vStorage, int Level, int fDuplicate )
+Vec_Ptr_t * Abc_NodeBalanceCone( Abc_Obj_t * pNode, Vec_Vec_t * vStorage, int Level, int fDuplicate, bool fSelective )
 {
     Vec_Ptr_t * vNodes;
     int RetValue, i;
@@ -219,7 +232,7 @@ Vec_Ptr_t * Abc_NodeBalanceCone( Abc_Obj_t * pNode, Vec_Vec_t * vStorage, int Le
     vNodes = Vec_VecEntry( vStorage, Level );
     Vec_PtrClear( vNodes );
     // collect the nodes in the implication supergate
-    RetValue = Abc_NodeBalanceCone_rec( pNode, vNodes, 1, fDuplicate );
+    RetValue = Abc_NodeBalanceCone_rec( pNode, vNodes, 1, fDuplicate, fSelective );
     assert( vNodes->nSize > 1 );
     // unmark the visited nodes
     for ( i = 0; i < vNodes->nSize; i++ )
@@ -245,7 +258,7 @@ Vec_Ptr_t * Abc_NodeBalanceCone( Abc_Obj_t * pNode, Vec_Vec_t * vStorage, int Le
   SeeAlso     []
 
 ***********************************************************************/
-int Abc_NodeBalanceCone_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vSuper, bool fFirst, bool fDuplicate )
+int Abc_NodeBalanceCone_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vSuper, bool fFirst, bool fDuplicate, bool fSelective )
 {
     int RetValue1, RetValue2, i;
     // check if the node is visited
@@ -263,7 +276,7 @@ int Abc_NodeBalanceCone_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vSuper, bool fFirst,
         return 0;
     }
     // if the new node is complemented or a PI, another gate begins
-    if ( !fFirst && (Abc_ObjIsComplement(pNode) || !Abc_ObjIsNode(pNode) || !fDuplicate && (Abc_ObjFanoutNum(pNode) > 1)) )
+    if ( !fFirst && (Abc_ObjIsComplement(pNode) || !Abc_ObjIsNode(pNode) || !fDuplicate && !fSelective && (Abc_ObjFanoutNum(pNode) > 1)) )
     {
         Vec_PtrPush( vSuper, pNode );
         Abc_ObjRegular(pNode)->fMarkB = 1;
@@ -272,8 +285,8 @@ int Abc_NodeBalanceCone_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vSuper, bool fFirst,
     assert( !Abc_ObjIsComplement(pNode) );
     assert( Abc_ObjIsNode(pNode) );
     // go through the branches
-    RetValue1 = Abc_NodeBalanceCone_rec( Abc_ObjChild0(pNode), vSuper, 0, fDuplicate );
-    RetValue2 = Abc_NodeBalanceCone_rec( Abc_ObjChild1(pNode), vSuper, 0, fDuplicate );
+    RetValue1 = Abc_NodeBalanceCone_rec( Abc_ObjChild0(pNode), vSuper, 0, fDuplicate, fSelective );
+    RetValue2 = Abc_NodeBalanceCone_rec( Abc_ObjChild1(pNode), vSuper, 0, fDuplicate, fSelective );
     if ( RetValue1 == -1 || RetValue2 == -1 )
         return -1;
     // return 1 if at least one branch has a duplicate
@@ -315,7 +328,7 @@ Vec_Ptr_t * Abc_NodeFindCone_rec( Abc_Obj_t * pNode )
     else
     {
         // collect the nodes in the implication supergate
-        RetValue = Abc_NodeBalanceCone_rec( pNode, vNodes, 1, 1 );
+        RetValue = Abc_NodeBalanceCone_rec( pNode, vNodes, 1, 1, 0 );
         assert( vNodes->nSize > 1 );
         // unmark the visited nodes
         Vec_PtrForEachEntry( vNodes, pNode, i )
@@ -442,6 +455,28 @@ void Abc_NtkBalanceLevel( Abc_Ntk_t * pNtk )
 }
 
 
+/**Function*************************************************************
+
+  Synopsis    [Marks the nodes on the critical and near critical paths.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Abc_NtkMarkCriticalNodes( Abc_Ntk_t * pNtk )
+{
+    Abc_Obj_t * pNode;
+    int i, Counter = 0;
+    Abc_NtkForEachNode( pNtk, pNode, i )
+        if ( Abc_NodeReadRequiredLevel(pNode) - pNode->Level <= 1 )
+            pNode->fMarkA = 1, Counter++;
+    printf( "The number of nodes on the critical paths = %6d  (%5.2f %%)\n", Counter, 100.0 * Counter / Abc_NtkNodeNum(pNtk) );
+}
+
+
 ////////////////////////////////////////////////////////////////////////
 ///                       END OF FILE                                ///
 ////////////////////////////////////////////////////////////////////////

src/base/abci/abcDsd.c

@@ -172,6 +172,7 @@ void Abc_NtkDsdConstruct( Dsd_Manager_t * pManDsd, Abc_Ntk_t * pNtk, Abc_Ntk_t *
     int i, nNodesDsd;
 
     // save the CI nodes in the DSD nodes
+    Dsd_NodeSetMark( Dsd_ManagerReadConst1(pManDsd), (int)Abc_NtkConst1(pNtk)->pCopy );
     Abc_NtkForEachCi( pNtk, pNode, i )
     {
         pNodeDsd = Dsd_ManagerReadInput( pManDsd, i );

src/base/abci/abcMap.c

@@ -105,7 +105,7 @@ clk = clock();
         Map_ManFree( pMan );
         return NULL;
     }
-//    Map_ManPrintStatsToFile( pNtk->pSpec, Map_ManReadAreaFinal(pMan), Map_ManReadRequiredGlo(pMan), clock()-clk );
+    Map_ManPrintStatsToFile( pNtk->pSpec, Map_ManReadAreaFinal(pMan), Map_ManReadRequiredGlo(pMan), clock()-clk );
 
     // reconstruct the network after mapping
     pNtkNew = Abc_NtkFromMap( pMan, pNtk );

src/base/abci/abcRenode.c

@@ -173,6 +173,8 @@ Abc_Obj_t * Abc_NtkRenode_rec( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNodeOld )
     assert( !Abc_NodeIsConst(pNodeOld) );
     assert( pNodeOld->fMarkA );
 
+//printf( "%d ", Abc_NodeMffcSizeSupp(pNodeOld) );
+
     // collect the renoding cone
     vCone = Vec_PtrAlloc( 10 );
     Abc_NtkRenodeCone( pNodeOld, vCone );

src/base/abci/abcSat.c

@@ -29,6 +29,8 @@ static int  Abc_NodeAddClausesTop( solver * pSat, Abc_Obj_t * pNode, Vec_Int_t *
 
 static solver * Abc_NtkMiterSatCreate2( Abc_Ntk_t * pNtk );
 
+static Vec_Int_t * Abc_NtkGetCiSatVarNums( Abc_Ntk_t * pNtk );
+
 static nMuxes;
 
 ////////////////////////////////////////////////////////////////////////
@@ -46,7 +48,7 @@ static nMuxes;
   SeeAlso     []
 
 ***********************************************************************/
-int Abc_NtkMiterSat( Abc_Ntk_t * pNtk, int nSeconds, int fVerbose )
+int Abc_NtkMiterSat_OldAndRusty( Abc_Ntk_t * pNtk, int nSeconds, int fVerbose )
 {
     solver * pSat;
     lbool   status;
@@ -317,7 +319,7 @@ int Abc_NodeAddClausesTop( solver * pSat, Abc_Obj_t * pNode, Vec_Int_t * vVars )
   SeeAlso     []
 
 ***********************************************************************/
-int Abc_NtkMiterSat2( Abc_Ntk_t * pNtk, int nSeconds, int fVerbose )
+int Abc_NtkMiterSat( Abc_Ntk_t * pNtk, int nSeconds, int fVerbose )
 {
     solver * pSat;
     lbool   status;
@@ -376,7 +378,8 @@ int Abc_NtkMiterSat2( Abc_Ntk_t * pNtk, int nSeconds, int fVerbose )
     // if the problem is SAT, get the counterexample
     if ( status == l_True )
     {
-        Vec_Int_t * vCiIds = Abc_NtkGetCiIds( pNtk );
+//        Vec_Int_t * vCiIds = Abc_NtkGetCiIds( pNtk );
+        Vec_Int_t * vCiIds = Abc_NtkGetCiSatVarNums( pNtk );
         pNtk->pModel = solver_get_model( pSat, vCiIds->pArray, vCiIds->nSize );
         Vec_IntFree( vCiIds );
     }
@@ -385,6 +388,28 @@ int Abc_NtkMiterSat2( Abc_Ntk_t * pNtk, int nSeconds, int fVerbose )
     return RetValue;
 }
 
+/**Function*************************************************************
+
+  Synopsis    [Returns the array of CI IDs.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Vec_Int_t * Abc_NtkGetCiSatVarNums( Abc_Ntk_t * pNtk )
+{
+    Vec_Int_t * vCiIds;
+    Abc_Obj_t * pObj;
+    int i;
+    vCiIds = Vec_IntAlloc( Abc_NtkCiNum(pNtk) );
+    Abc_NtkForEachCi( pNtk, pObj, i )
+        Vec_IntPush( vCiIds, (int)pObj->pCopy );
+    return vCiIds;
+}
+
 
 
  

src/base/abci/abcUnate.c

+/**CFile****************************************************************
+
+  FileName    [abcUnate.c]
+
+  SystemName  [ABC: Logic synthesis and verification system.]
+
+  PackageName [Network and node package.]
+
+  Synopsis    []
+
+  Author      [Alan Mishchenko]
+  
+  Affiliation [UC Berkeley]
+
+  Date        [Ver. 1.0. Started - June 20, 2005.]
+
+  Revision    [$Id: abcUnate.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
+
+***********************************************************************/
+
+#include "abc.h"
+
+////////////////////////////////////////////////////////////////////////
+///                        DECLARATIONS                              ///
+////////////////////////////////////////////////////////////////////////
+
+static void Abc_NtkPrintUnateBdd( Abc_Ntk_t * pNtk, int fUseNaive, int fVerbose );
+static void Abc_NtkPrintUnateSat( Abc_Ntk_t * pNtk, int fVerbose );
+
+////////////////////////////////////////////////////////////////////////
+///                     FUNCTION DEFINITIONS                         ///
+////////////////////////////////////////////////////////////////////////
+
+/**Function*************************************************************
+
+  Synopsis    [Detects unate variables of the multi-output function.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Abc_NtkPrintUnate( Abc_Ntk_t * pNtk, int fUseBdds, int fUseNaive, int fVerbose )
+{
+    if ( fUseBdds || fUseNaive )
+        Abc_NtkPrintUnateBdd( pNtk, fUseNaive, fVerbose );
+    else
+        Abc_NtkPrintUnateSat( pNtk, fVerbose );
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Detects unate variables using BDDs.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Abc_NtkPrintUnateBdd( Abc_Ntk_t * pNtk, int fUseNaive, int fVerbose )
+{
+    Abc_Obj_t * pNode;
+    Extra_UnateInfo_t * p;
+    DdManager * dd;         // the BDD manager used to hold shared BDDs
+    DdNode ** pbGlobal;     // temporary storage for global BDDs
+    int TotalSupps = 0;
+    int TotalUnate = 0;
+    int i, clk = clock();
+    int clkBdd, clkUnate;
+
+    // compute the global BDDs
+    if ( Abc_NtkGlobalBdds(pNtk, 0) == NULL )
+        return;
+clkBdd = clock() - clk;
+
+    // get information about the network
+    dd       = pNtk->pManGlob;
+    pbGlobal = (DdNode **)Vec_PtrArray( pNtk->vFuncsGlob );
+
+    // print the size of the BDDs
+    printf( "The shared BDD size is %d nodes.\n", Cudd_ReadKeys(dd) - Cudd_ReadDead(dd) );
+
+    // perform naive BDD-based computation
+    if ( fUseNaive )
+    {
+        Abc_NtkForEachCo( pNtk, pNode, i )
+        {
+            p = Extra_UnateComputeSlow( dd, pbGlobal[i] );
+            if ( fVerbose )
+                Extra_UnateInfoPrint( p );
+            TotalSupps += p->nVars;
+            TotalUnate += p->nUnate;
+            Extra_UnateInfoDissolve( p );
+        }
+    }
+    // perform smart BDD-based computation
+    else 
+    {
+        // create ZDD variables in the manager
+        Cudd_zddVarsFromBddVars( dd, 2 );
+        Abc_NtkForEachCo( pNtk, pNode, i )
+        {
+            p = Extra_UnateComputeFast( dd, pbGlobal[i] );
+            if ( fVerbose )
+                Extra_UnateInfoPrint( p );
+            TotalSupps += p->nVars;
+            TotalUnate += p->nUnate;
+            Extra_UnateInfoDissolve( p );
+        }
+    }
+clkUnate = clock() - clk - clkBdd;
+
+    // print stats
+    printf( "Ins/Outs = %4d/%4d.  Total supp = %5d.  Total unate = %5d.\n",
+        Abc_NtkCiNum(pNtk), Abc_NtkCoNum(pNtk), TotalSupps, TotalUnate );
+    PRT( "Glob BDDs", clkBdd );
+    PRT( "Unateness", clkUnate );
+    PRT( "Total    ", clock() - clk );
+
+    // deref the PO functions
+    Abc_NtkFreeGlobalBdds( pNtk );
+    // stop the global BDD manager
+    Extra_StopManager( pNtk->pManGlob );
+    pNtk->pManGlob = NULL;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Detects unate variables using SAT.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Abc_NtkPrintUnateSat( Abc_Ntk_t * pNtk, int fVerbose )
+{
+}
+
+////////////////////////////////////////////////////////////////////////
+///                       END OF FILE                                ///
+////////////////////////////////////////////////////////////////////////
+
+

src/base/abci/abcVerify.c

@@ -148,9 +148,9 @@ void Abc_NtkCecFraig( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int nSeconds, int fV
     Fraig_ParamsSetDefault( &Params );
     Params.fVerbose = fVerbose;
     Params.nSeconds = nSeconds;
-    Params.fFuncRed = 0;
-    Params.nPatsRand = 0;
-    Params.nPatsDyna = 0;
+//    Params.fFuncRed = 0;
+//    Params.nPatsRand = 0;
+//    Params.nPatsDyna = 0;
     pMan = Abc_NtkToFraig( pMiter, &Params, 0, 0 ); 
     Fraig_ManProveMiter( pMan );
 
@@ -328,9 +328,9 @@ void Abc_NtkSecFraig( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int nSeconds, int nF
     Fraig_ParamsSetDefault( &Params );
     Params.fVerbose = fVerbose;
     Params.nSeconds = nSeconds;
-    Params.fFuncRed = 0;
-    Params.nPatsRand = 0;
-    Params.nPatsDyna = 0;
+//    Params.fFuncRed = 0;
+//    Params.nPatsRand = 0;
+//    Params.nPatsDyna = 0;
     pMan = Abc_NtkToFraig( pFrames, &Params, 0, 0 ); 
     Fraig_ManProveMiter( pMan );
 

src/base/abci/module.make

 SRC +=    src/base/abci/abc.c \
     src/base/abci/abcAttach.c \
+    src/base/abci/abcAuto.c \
     src/base/abci/abcBalance.c \
     src/base/abci/abcCollapse.c \
     src/base/abci/abcCut.c \
@@ -21,6 +22,7 @@ SRC +=    src/base/abci/abc.c \
     src/base/abci/abcSweep.c \
     src/base/abci/abcSymm.c \
     src/base/abci/abcTiming.c \
+    src/base/abci/abcUnate.c \
     src/base/abci/abcUnreach.c \
     src/base/abci/abcVanEijk.c \
     src/base/abci/abcVanImp.c \

src/base/cmd/cmd.c

@@ -1204,7 +1204,7 @@ int CmdCommandSis( Abc_Frame_t * pAbc, int argc, char **argv )
     char * pSisName;
     int i;
 
-    pNtk = Abc_FrameReadNet(pAbc);
+    pNtk = Abc_FrameReadNtk(pAbc);
     pOut = Abc_FrameReadOut(pAbc);
     pErr = Abc_FrameReadErr(pAbc);
 
@@ -1340,7 +1340,7 @@ int CmdCommandMvsis( Abc_Frame_t * pAbc, int argc, char **argv )
     char * pMvsisName;
     int i;
 
-    pNtk = Abc_FrameReadNet(pAbc);
+    pNtk = Abc_FrameReadNtk(pAbc);
     pOut = Abc_FrameReadOut(pAbc);
     pErr = Abc_FrameReadErr(pAbc);
 

src/base/io/io.h

@@ -69,6 +69,7 @@ extern Abc_Obj_t *        Io_ReadCreateNode( Abc_Ntk_t * pNtk, char * pNameOut,
 extern Abc_Obj_t *        Io_ReadCreateConst( Abc_Ntk_t * pNtk, char * pName, bool fConst1 );
 extern Abc_Obj_t *        Io_ReadCreateInv( Abc_Ntk_t * pNtk, char * pNameIn, char * pNameOut );
 extern Abc_Obj_t *        Io_ReadCreateBuf( Abc_Ntk_t * pNtk, char * pNameIn, char * pNameOut );
+extern FILE *             Io_FileOpen( const char * FileName, const char * PathVar, const char * Mode, int fVerbose );
 /*=== abcWriteBaf.c ==========================================================*/
 extern void               Io_WriteBaf( Abc_Ntk_t * pNtk, char * pFileName );
 /*=== abcWriteBlif.c ==========================================================*/

src/base/io/ioReadBench.c

@@ -47,7 +47,7 @@ Abc_Ntk_t * Io_ReadBench( char * pFileName, int fCheck )
     Abc_Ntk_t * pNtk;
 
     // start the file
-    p = Extra_FileReaderAlloc( pFileName, "#", "\n", " \t\r,()=" );
+    p = Extra_FileReaderAlloc( pFileName, "#", "\n\r", " \t,()=" );
     if ( p == NULL )
         return NULL;
 

src/base/io/ioReadBlif.c

@@ -135,7 +135,8 @@ Io_ReadBlif_t * Io_ReadBlifFile( char * pFileName )
     Io_ReadBlif_t * p;
 
     // start the reader
-    pReader = Extra_FileReaderAlloc( pFileName, "#", "\n", " \t\r" );
+    pReader = Extra_FileReaderAlloc( pFileName, "#", "\n\r", " \t" );
+
     if ( pReader == NULL )
         return NULL;
 

src/base/io/ioReadEdif.c

@@ -47,7 +47,7 @@ Abc_Ntk_t * Io_ReadEdif( char * pFileName, int fCheck )
     Abc_Ntk_t * pNtk;
 
     // start the file
-    p = Extra_FileReaderAlloc( pFileName, "#", "\n", " \t\r()" );
+    p = Extra_FileReaderAlloc( pFileName, "#", "\n\r", " \t()" );
     if ( p == NULL )
         return NULL;
 

src/base/io/ioReadPla.c

@@ -47,7 +47,7 @@ Abc_Ntk_t * Io_ReadPla( char * pFileName, int fCheck )
     Abc_Ntk_t * pNtk;
 
     // start the file
-    p = Extra_FileReaderAlloc( pFileName, "#", "\n", " \t\r|" );
+    p = Extra_FileReaderAlloc( pFileName, "#", "\n\r", " \t|" );
     if ( p == NULL )
         return NULL;
 

src/base/io/ioUtil.c

@@ -194,6 +194,61 @@ Abc_Obj_t * Io_ReadCreateBuf( Abc_Ntk_t * pNtk, char * pNameIn, char * pNameOut
     return pNet;
 }
 
+
+/**Function*************************************************************
+
+  Synopsis    [Provide an fopen replacement with path lookup]
+
+  Description [Provide an fopen replacement where the path stored
+               in pathvar MVSIS variable is used to look up the path
+               for name. Returns NULL if file cannot be opened.]
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+FILE * Io_FileOpen( const char * FileName, const char * PathVar, const char * Mode, int fVerbose )
+{
+    char * t = 0, * c = 0, * i;
+    extern char * Abc_FrameReadFlag( char * pFlag ); 
+
+    if ( PathVar == 0 )
+    {
+        return fopen( FileName, Mode );
+    }
+    else
+    {
+        if ( c = Abc_FrameReadFlag( (char*)PathVar ) )
+        {
+            char ActualFileName[4096];
+            FILE * fp = 0;
+            t = util_strsav( c );
+            for (i = strtok( t, ":" ); i != 0; i = strtok( 0, ":") )
+            {
+#ifdef WIN32
+                _snprintf ( ActualFileName, 4096, "%s/%s", i, FileName );
+#else
+                snprintf ( ActualFileName, 4096, "%s/%s", i, FileName );
+#endif
+                if ( ( fp = fopen ( ActualFileName, Mode ) ) )
+                {
+                    if ( fVerbose )
+                    fprintf ( stdout, "Using file %s\n", ActualFileName );
+                    free( t );
+                    return fp;
+                }
+            }
+            free( t );
+            return 0;
+        }
+        else
+        {
+            return fopen( FileName, Mode );
+        }
+    }
+}
+
 ////////////////////////////////////////////////////////////////////////
 ///                       END OF FILE                                ///
 ////////////////////////////////////////////////////////////////////////

src/base/io/module.make

@@ -16,4 +16,5 @@ SRC +=  src/base/io/io.c \
     src/base/io/ioWriteEqn.c \
     src/base/io/ioWriteGml.c \
     src/base/io/ioWriteList.c \
-    src/base/io/ioWritePla.c
+    src/base/io/ioWritePla.c \
+    src/base/io/ioWriteVerilog.c

src/base/main/main.h

@@ -78,7 +78,7 @@ extern void            Abc_Start();
 extern void            Abc_Stop();
 
 /*=== mainFrame.c ===========================================================*/
-extern Abc_Ntk_t *     Abc_FrameReadNet( Abc_Frame_t * p );
+extern Abc_Ntk_t *     Abc_FrameReadNtk( Abc_Frame_t * p );
 extern FILE *          Abc_FrameReadOut( Abc_Frame_t * p );
 extern FILE *          Abc_FrameReadErr( Abc_Frame_t * p );
 extern bool            Abc_FrameReadMode( Abc_Frame_t * p );

src/base/main/mainFrame.c

@@ -164,7 +164,7 @@ void Abc_FrameRestart( Abc_Frame_t * p )
   SeeAlso     []
 
 ***********************************************************************/
-Abc_Ntk_t * Abc_FrameReadNet( Abc_Frame_t * p )
+Abc_Ntk_t * Abc_FrameReadNtk( Abc_Frame_t * p )
 {
     return p->pNtkCur;
 }

src/base/seq/seqAigCore.c

@@ -351,11 +351,13 @@ int Seq_NtkImplementRetimingBackward( Abc_Ntk_t * pNtk, Vec_Ptr_t * vMoves, int
     printf( "The number of ANDs in the AIG = %5d.\n", Abc_NtkNodeNum(pNtkMiter) );
 
     // transform the miter into a logic network for efficient CNF construction
-    pNtkCnf = Abc_NtkRenode( pNtkMiter, 0, 100, 1, 0, 0 );
-    Abc_NtkDelete( pNtkMiter );
+//    pNtkCnf = Abc_NtkRenode( pNtkMiter, 0, 100, 1, 0, 0 );
+//    Abc_NtkDelete( pNtkMiter );
+    pNtkCnf = pNtkMiter;
 
     // solve the miter
 clk = clock();
+//    RetValue = Abc_NtkMiterSat_OldAndRusty( pNtkCnf, 30, 0 );
     RetValue = Abc_NtkMiterSat( pNtkCnf, 30, 0 );
 if ( fVerbose )
 if ( clock() - clk > 100 )

src/bdd/dsd/dsd.h

@@ -91,6 +91,7 @@ extern void            Dsd_NodeSetMark( Dsd_Node_t * p, int Mark );
 extern DdManager *     Dsd_ManagerReadDd( Dsd_Manager_t * pMan );
 extern Dsd_Node_t *    Dsd_ManagerReadRoot( Dsd_Manager_t * pMan, int i );
 extern Dsd_Node_t *    Dsd_ManagerReadInput( Dsd_Manager_t * pMan, int i );
+extern Dsd_Node_t *    Dsd_ManagerReadConst1( Dsd_Manager_t * pMan );
 /*=== dsdMan.c =======================================================*/
 extern Dsd_Manager_t * Dsd_ManagerStart( DdManager * dd, int nSuppMax, int fVerbose );
 extern void            Dsd_ManagerStop( Dsd_Manager_t * dMan );

src/bdd/dsd/dsdApi.c

@@ -89,6 +89,7 @@ void          Dsd_NodeSetMark( Dsd_Node_t * p, int Mark ){ p->Mark = Mark;     }
 ***********************************************************************/
 Dsd_Node_t *  Dsd_ManagerReadRoot( Dsd_Manager_t * pMan, int i )  { return pMan->pRoots[i];  } 
 Dsd_Node_t *  Dsd_ManagerReadInput( Dsd_Manager_t * pMan, int i ) { return pMan->pInputs[i]; } 
+Dsd_Node_t *  Dsd_ManagerReadConst1( Dsd_Manager_t * pMan )       { return pMan->pConst1;    } 
 DdManager *   Dsd_ManagerReadDd( Dsd_Manager_t * pMan )           { return pMan->dd;         } 
 
 ////////////////////////////////////////////////////////////////////////

src/bdd/dsd/dsdInt.h

@@ -42,6 +42,7 @@ struct Dsd_Manager_t_
     int            nRootsAlloc;// the number of primary outputs
     Dsd_Node_t **  pInputs;    // the primary input nodes
     Dsd_Node_t **  pRoots;     // the primary output nodes
+    Dsd_Node_t *   pConst1;    // the constant node
     int            fVerbose;   // the verbosity level 
 };
 

src/bdd/dsd/dsdMan.c

@@ -73,6 +73,7 @@ Dsd_Manager_t * Dsd_ManagerStart( DdManager * dd, int nSuppMax, int fVerbose )
     pNode->G = b1;  Cudd_Ref( pNode->G );
     pNode->S = b1;  Cudd_Ref( pNode->S );
     st_insert( dMan->Table, (char*)b1, (char*)pNode );
+    dMan->pConst1 = pNode;
 
     Dsd_CheckCacheAllocate( 5000 );
     return dMan;

src/map/fpga/fpga.c

@@ -105,7 +105,7 @@ int Fpga_CommandReadLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
     int fVerbose;
     int c;
 
-    pNet = Abc_FrameReadNet(pAbc);
+    pNet = Abc_FrameReadNtk(pAbc);
     pOut = Abc_FrameReadOut(pAbc);
     pErr = Abc_FrameReadErr(pAbc);
 
@@ -195,7 +195,7 @@ int Fpga_CommandPrintLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
     int fVerbose;
     int c;
 
-    pNet = Abc_FrameReadNet(pAbc);
+    pNet = Abc_FrameReadNtk(pAbc);
     pOut = Abc_FrameReadOut(pAbc);
     pErr = Abc_FrameReadErr(pAbc);
 

src/map/mapper/mapper.c

@@ -87,7 +87,7 @@ int Map_CommandReadLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
     int fAlgorithm;
     int c;
 
-    pNet = Abc_FrameReadNet(pAbc);
+    pNet = Abc_FrameReadNtk(pAbc);
     pOut = Abc_FrameReadOut(pAbc);
     pErr = Abc_FrameReadErr(pAbc);
 
@@ -128,8 +128,8 @@ int Map_CommandReadLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
 
     // get the input file name
     FileName = argv[util_optind];
-//    if ( (pFile = Io_FileOpen( FileName, "open_path", "r" )) == NULL )
-    if ( (pFile = fopen( FileName, "r" )) == NULL )
+    if ( (pFile = Io_FileOpen( FileName, "open_path", "r", 0 )) == NULL )
+//    if ( (pFile = fopen( FileName, "r" )) == NULL )
     {
         fprintf( pErr, "Cannot open input file \"%s\". ", FileName );
         if ( FileName = Extra_FileGetSimilarName( FileName, ".genlib", ".lib", ".gen", ".g", NULL ) )

src/map/mapper/mapperCreate.c

@@ -314,7 +314,7 @@ void Map_ManPrintTimeStats( Map_Man_t * p )
 void Map_ManPrintStatsToFile( char * pName, float Area, float Delay, int Time )
 {
     FILE * pTable;
-    pTable = fopen( "stats.txt", "a+" );
+    pTable = fopen( "map_stats.txt", "a+" );
     fprintf( pTable, "%s ", pName );
     fprintf( pTable, "%4.2f ", Area );
     fprintf( pTable, "%4.2f ", Delay );

src/map/mapper/mapperTree.c

@@ -60,8 +60,8 @@ int Map_LibraryReadTree( Map_SuperLib_t * pLib, char * pFileName, char * pExclud
 
     // read the beginning of the file
     assert( pLib->pGenlib == NULL );
-//    pFile = Io_FileOpen( pFileName, "open_path", "r" );
-    pFile = fopen( pFileName, "r" ); 
+    pFile = Io_FileOpen( pFileName, "open_path", "r", 1 );
+//    pFile = fopen( pFileName, "r" ); 
     if ( pFile == NULL )
     {
         printf( "Cannot open input file \"%s\".\n", pFileName );
@@ -149,8 +149,8 @@ int Map_LibraryReadFileTree( Map_SuperLib_t * pLib, FILE * pFile, char *pFileNam
     }
 #endif
     
-//    pFileGen = Io_FileOpen( pLibFile, "open_path", "r" );
-    pFileGen = fopen( pLibFile, "r" ); 
+    pFileGen = Io_FileOpen( pLibFile, "open_path", "r", 1 );
+//    pFileGen = fopen( pLibFile, "r" ); 
     if ( pFileGen == NULL )
     {
         printf( "Cannot open the GENLIB file \"%s\".\n", pLibFile );

src/map/mio/mio.c

@@ -133,7 +133,7 @@ int Mio_CommandReadLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
     int fVerbose;
     int c;
 
-    pNet = Abc_FrameReadNet(pAbc);
+    pNet = Abc_FrameReadNtk(pAbc);
     pOut = Abc_FrameReadOut(pAbc);
     pErr = Abc_FrameReadErr(pAbc);
 
@@ -163,7 +163,7 @@ int Mio_CommandReadLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
 
     // get the input file name
     FileName = argv[util_optind];
-    if ( (pFile = fopen( FileName, "r" )) == NULL )
+    if ( (pFile = Io_FileOpen( FileName, "open_path", "r", 0 )) == NULL )
     {
         fprintf( pErr, "Cannot open input file \"%s\". ", FileName );
         if ( (FileName = Extra_FileGetSimilarName( FileName, ".genlib", ".lib", ".gen", ".g", NULL )) )
@@ -223,7 +223,7 @@ int Mio_CommandPrintLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
     int fVerbose;
     int c;
 
-    pNet = Abc_FrameReadNet(pAbc);
+    pNet = Abc_FrameReadNtk(pAbc);
     pOut = Abc_FrameReadOut(pAbc);
     pErr = Abc_FrameReadErr(pAbc);
 

src/map/mio/mioRead.c

@@ -114,8 +114,8 @@ Mio_Library_t * Mio_LibraryReadOne( Abc_Frame_t * pAbc, char * FileName, bool fE
         int nFileSize;
 
         // open the BLIF file for binary reading
-//        pFile = Io_FileOpen( FileName, "open_path", "rb" );
-        pFile = fopen( FileName, "rb" );
+        pFile = Io_FileOpen( FileName, "open_path", "rb", 1 );
+//        pFile = fopen( FileName, "rb" );
         // if we got this far, file should be okay otherwise would
         // have been detected by caller
         assert ( pFile != NULL );

src/map/super/super.c

@@ -245,8 +245,8 @@ int Super_CommandSupergates( Abc_Frame_t * pAbc, int argc, char **argv )
 
     // get the input file name
     FileName = argv[util_optind];
-//    if ( (pFile = Io_FileOpen( FileName, "open_path", "r" )) == NULL )
-    if ( (pFile = fopen( FileName, "r" )) == NULL )
+    if ( (pFile = Io_FileOpen( FileName, "open_path", "r", 0 )) == NULL )
+//    if ( (pFile = fopen( FileName, "r" )) == NULL )
     {
         fprintf( pErr, "Cannot open input file \"%s\". ", FileName );
         if (( FileName = Extra_FileGetSimilarName( FileName, ".genlib", ".lib", ".gen", ".g", NULL ) ))

src/misc/extra/extra.h

@@ -106,7 +106,35 @@ typedef unsigned long long uint64;
 /*     Various Utilities                                                     */
 /*===========================================================================*/
 
+/*=== extraBddAuto.c ========================================================*/
+
+extern DdNode *     Extra_bddSpaceFromFunctionFast( DdManager * dd, DdNode * bFunc );
+extern DdNode *     Extra_bddSpaceFromFunction( DdManager * dd, DdNode * bF, DdNode * bG );
+extern DdNode *      extraBddSpaceFromFunction( DdManager * dd, DdNode * bF, DdNode * bG );
+extern DdNode *     Extra_bddSpaceFromFunctionPos( DdManager * dd, DdNode * bFunc );
+extern DdNode *      extraBddSpaceFromFunctionPos( DdManager * dd, DdNode * bFunc );
+extern DdNode *     Extra_bddSpaceFromFunctionNeg( DdManager * dd, DdNode * bFunc );
+extern DdNode *      extraBddSpaceFromFunctionNeg( DdManager * dd, DdNode * bFunc );
+
+extern DdNode *     Extra_bddSpaceCanonVars( DdManager * dd, DdNode * bSpace );
+extern DdNode *      extraBddSpaceCanonVars( DdManager * dd, DdNode * bSpace );
+
+extern DdNode *     Extra_bddSpaceEquations( DdManager * dd, DdNode * bSpace );
+extern DdNode *     Extra_bddSpaceEquationsNeg( DdManager * dd, DdNode * bSpace );
+extern DdNode *      extraBddSpaceEquationsNeg( DdManager * dd, DdNode * bSpace );
+extern DdNode *     Extra_bddSpaceEquationsPos( DdManager * dd, DdNode * bSpace );
+extern DdNode *      extraBddSpaceEquationsPos( DdManager * dd, DdNode * bSpace );
+
+extern DdNode *     Extra_bddSpaceFromMatrixPos( DdManager * dd, DdNode * zA );
+extern DdNode *      extraBddSpaceFromMatrixPos( DdManager * dd, DdNode * zA );
+extern DdNode *     Extra_bddSpaceFromMatrixNeg( DdManager * dd, DdNode * zA );
+extern DdNode *      extraBddSpaceFromMatrixNeg( DdManager * dd, DdNode * zA );
+
+extern DdNode *     Extra_bddSpaceReduce( DdManager * dd, DdNode * bFunc, DdNode * bCanonVars );
+extern DdNode **    Extra_bddSpaceExorGates( DdManager * dd, DdNode * bFuncRed, DdNode * zEquations );
+
 /*=== extraBddMisc.c ========================================================*/
+
 extern DdNode *     Extra_TransferPermute( DdManager * ddSource, DdManager * ddDestination, DdNode * f, int * Permute );
 extern DdNode *     Extra_TransferLevelByLevel( DdManager * ddSource, DdManager * ddDestination, DdNode * f );
 extern DdNode *     Extra_bddRemapUp( DdManager * dd, DdNode * bF );
@@ -126,6 +154,7 @@ extern DdNode *     Extra_bddFindOneCube( DdManager * dd, DdNode * bF );
 extern DdNode *     Extra_bddGetOneCube( DdManager * dd, DdNode * bFunc );
 extern DdNode *     Extra_bddComputeRangeCube( DdManager * dd, int iStart, int iStop );
 extern DdNode *     Extra_bddBitsToCube( DdManager * dd, int Code, int CodeWidth, DdNode ** pbVars, int fMsbFirst );
+extern DdNode *     Extra_bddSupportNegativeCube( DdManager * dd, DdNode * f );
 
 /*=== extraBddKmap.c ================================================================*/
 
@@ -185,6 +214,46 @@ extern DdNode *     extraZddTuplesFromBdd( DdManager * dd, DdNode * bVarsK, DdNo
 extern DdNode *    Extra_zddSelectOneSubset( DdManager * dd, DdNode * zS );
 extern DdNode *     extraZddSelectOneSubset( DdManager * dd, DdNode * zS );
 
+/*=== extraBddUnate.c =================================================================*/
+
+typedef struct Extra_UnateVar_t_  Extra_UnateVar_t;
+struct Extra_UnateVar_t_ {
+    unsigned    iVar : 30;  // index of the variable
+    unsigned    Pos  :  1;  // 1 if positive unate
+    unsigned    Neg  :  1;  // 1 if negative unate
+};
+
+typedef struct Extra_UnateInfo_t_  Extra_UnateInfo_t;
+struct Extra_UnateInfo_t_ {
+    int nVars;      // the number of variables in the support
+    int nVarsMax;   // the number of variables in the DD manager
+    int nUnate;     // the number of unate variables
+    Extra_UnateVar_t * pVars;    // the array of variables present in the support
+};
+
+/* allocates the data structure */
+extern Extra_UnateInfo_t *  Extra_UnateInfoAllocate( int nVars );
+/* deallocates the data structure */
+extern void        Extra_UnateInfoDissolve( Extra_UnateInfo_t * );
+/* print the contents the data structure */
+extern void        Extra_UnateInfoPrint( Extra_UnateInfo_t * );
+/* converts the ZDD into the Extra_SymmInfo_t structure */
+extern Extra_UnateInfo_t *  Extra_UnateInfoCreateFromZdd( DdManager * dd, DdNode * zUnate, DdNode * bVars );
+/* naive check of unateness of one variable */
+extern int         Extra_bddCheckUnateNaive( DdManager * dd, DdNode * bF, int iVar );
+
+/* computes the unateness information for the function */
+extern Extra_UnateInfo_t *  Extra_UnateComputeFast( DdManager * dd, DdNode * bFunc );
+extern Extra_UnateInfo_t *  Extra_UnateComputeSlow( DdManager * dd, DdNode * bFunc );
+
+/* computes the classical symmetry information as a ZDD */
+extern DdNode *    Extra_zddUnateInfoCompute( DdManager * dd, DdNode * bF, DdNode * bVars );
+extern DdNode *     extraZddUnateInfoCompute( DdManager * dd, DdNode * bF, DdNode * bVars );
+
+/* converts a set of variables into a set of singleton subsets */
+extern DdNode *    Extra_zddGetSingletonsBoth( DdManager * dd, DdNode * bVars );
+extern DdNode *     extraZddGetSingletonsBoth( DdManager * dd, DdNode * bVars );
+
 /*=== extraUtilBitMatrix.c ================================================================*/
 
 typedef struct Extra_BitMat_t_ Extra_BitMat_t;

src/misc/extra/extraBddMisc.c

@@ -719,6 +719,83 @@ DdNode * Extra_bddBitsToCube( DdManager * dd, int Code, int CodeWidth, DdNode **
     return bResult;
 }  /* end of Extra_bddBitsToCube */
 
+/**Function********************************************************************
+
+  Synopsis    [Finds the support as a negative polarity cube.]
+
+  Description [Finds the variables on which a DD depends. Returns a BDD 
+  consisting of the product of the variables in the negative polarity 
+  if successful; NULL otherwise.]
+
+  SideEffects [None]
+
+  SeeAlso     [Cudd_VectorSupport Cudd_Support]
+
+******************************************************************************/
+DdNode * Extra_bddSupportNegativeCube( DdManager * dd, DdNode * f )
+{
+    int *support;
+    DdNode *res, *tmp, *var;
+    int i, j;
+    int size;
+
+    /* Allocate and initialize support array for ddSupportStep. */
+    size = ddMax( dd->size, dd->sizeZ );
+    support = ALLOC( int, size );
+    if ( support == NULL )
+    {
+        dd->errorCode = CUDD_MEMORY_OUT;
+        return ( NULL );
+    }
+    for ( i = 0; i < size; i++ )
+    {
+        support[i] = 0;
+    }
+
+    /* Compute support and clean up markers. */
+    ddSupportStep( Cudd_Regular( f ), support );
+    ddClearFlag( Cudd_Regular( f ) );
+
+    /* Transform support from array to cube. */
+    do
+    {
+        dd->reordered = 0;
+        res = DD_ONE( dd );
+        cuddRef( res );
+        for ( j = size - 1; j >= 0; j-- )
+        {                        /* for each level bottom-up */
+            i = ( j >= dd->size ) ? j : dd->invperm[j];
+            if ( support[i] == 1 )
+            {
+                var = cuddUniqueInter( dd, i, dd->one, Cudd_Not( dd->one ) );
+                //////////////////////////////////////////////////////////////////
+                var = Cudd_Not(var);
+                //////////////////////////////////////////////////////////////////
+                cuddRef( var );
+                tmp = cuddBddAndRecur( dd, res, var );
+                if ( tmp == NULL )
+                {
+                    Cudd_RecursiveDeref( dd, res );
+                    Cudd_RecursiveDeref( dd, var );
+                    res = NULL;
+                    break;
+                }
+                cuddRef( tmp );
+                Cudd_RecursiveDeref( dd, res );
+                Cudd_RecursiveDeref( dd, var );
+                res = tmp;
+            }
+        }
+    }
+    while ( dd->reordered == 1 );
+
+    FREE( support );
+    if ( res != NULL )
+        cuddDeref( res );
+    return ( res );
+
+}                                /* end of Extra_SupportNeg */
+
 /*---------------------------------------------------------------------------*/
 /* Definition of internal functions                                          */
 /*---------------------------------------------------------------------------*/

src/misc/extra/extraUtilCanon.c

@@ -99,7 +99,8 @@ int Extra_TruthCanonFastN( int nVarsMax, int nVarsReal, unsigned * pt, unsigned
 
   Description []
                
-  SideEffects []
+  SideEffects [This procedure has a bug, which shows on Solaris.
+  Most likely has something to do with the casts, i.g *((unsigned *)pt0)]
 
   SeeAlso     []
 
@@ -129,21 +130,22 @@ int Extra_TruthCanonN_rec( int nVars, unsigned char * pt, unsigned ** pptRes, ch
     pt0 = pt;
     pt1 = pt + (1 << nVarsN) / 8;
     // 5-var truth tables for this call
-    uInit0 = *((unsigned *)pt0);
-    uInit1 = *((unsigned *)pt1);
+//    uInit0 = *((unsigned *)pt0);
+//    uInit1 = *((unsigned *)pt1);
     if ( nVarsN == 3 )
     {
-        uInit0 &= 0xFF;
-        uInit1 &= 0xFF;
-        uInit0 = (uInit0 << 24) | (uInit0 << 16) | (uInit0 << 8) | uInit0;
-        uInit1 = (uInit1 << 24) | (uInit1 << 16) | (uInit1 << 8) | uInit1;
+        uInit0 = (pt0[0] << 24) | (pt0[0] << 16) | (pt0[0] << 8) | pt0[0];
+        uInit1 = (pt1[0] << 24) | (pt1[0] << 16) | (pt1[0] << 8) | pt1[0];
     }
     else if ( nVarsN == 4 )
     {
-        uInit0 &= 0xFFFF;
-        uInit1 &= 0xFFFF;
-        uInit0 = (uInit0 << 16) | uInit0;
-        uInit1 = (uInit1 << 16) | uInit1;
+        uInit0 = (pt0[1] << 24) | (pt0[0] << 16) | (pt0[1] << 8) | pt0[0];
+        uInit1 = (pt1[1] << 24) | (pt1[0] << 16) | (pt1[1] << 8) | pt1[0];
+    }
+    else
+    {
+        uInit0 = (pt0[3] << 24) | (pt0[2] << 16) | (pt0[1] << 8) | pt0[0];
+        uInit1 = (pt1[3] << 24) | (pt1[2] << 16) | (pt1[1] << 8) | pt1[0];
     }
 
     // storage for truth tables and phases

src/misc/extra/extraUtilReader.c

@@ -262,6 +262,9 @@ void * Extra_FileReaderGetTokens_int( Extra_FileReader_t * p )
     // check if the new data should to be loaded
     if ( p->pBufferCur > p->pBufferStop )
         Extra_FileReaderReload( p );
+
+//    printf( "%d\n", p->pBufferEnd - p->pBufferCur );
+
     // process the string starting from the current position
     for ( pChar = p->pBufferCur; pChar < p->pBufferEnd; pChar++ )
     {
@@ -270,6 +273,10 @@ void * Extra_FileReaderGetTokens_int( Extra_FileReader_t * p )
             p->nLineCounter++;
         // switch depending on the character
         MapValue = p->pCharMap[*pChar];
+
+//        printf( "Char value = %d. Map value = %d.\n", *pChar, MapValue );
+
+
         switch ( MapValue )
         {
             case EXTRA_CHAR_COMMENT:
@@ -326,6 +333,14 @@ void * Extra_FileReaderGetTokens_int( Extra_FileReader_t * p )
         return p->vTokens;
     }
     printf( "Extra_FileReader failed to parse the file \"%s\".\n", p->pFileName );
+/*
+    {
+        int i;
+        for ( i = 0; i < p->vTokens->nSize; i++ )
+            printf( "%s ", p->vTokens->pArray[i] );
+        printf( "\n" );
+    }
+*/
     return NULL;
 }
 

src/misc/extra/module.make

-SRC +=    src/misc/extra/extraBddKmap.c \
+SRC +=    src/misc/extra/extraBddAuto.c \
+    src/misc/extra/extraBddKmap.c \
     src/misc/extra/extraBddMisc.c \
     src/misc/extra/extraBddSymm.c \
     src/misc/extra/extraUtilBitMatrix.c \

src/misc/vec/vecInt.h

@@ -345,6 +345,7 @@ static inline void Vec_IntGrow( Vec_Int_t * p, int nCapMin )
     if ( p->nCap >= nCapMin )
         return;
     p->pArray = REALLOC( int, p->pArray, nCapMin ); 
+    assert( p->pArray );
     p->nCap   = nCapMin;
 }
 

src/opt/dec/decAbc.c

@@ -18,7 +18,7 @@
 
 #include "abc.h"
 #include "dec.h"
-#include "aig.h"
+//#include "aig.h"
 
 ////////////////////////////////////////////////////////////////////////
 ///                        DECLARATIONS                              ///
@@ -214,6 +214,7 @@ void Dec_GraphUpdateNetwork( Abc_Obj_t * pRoot, Dec_Graph_t * pGraph, bool fUpda
   SeeAlso     []
 
 ***********************************************************************/
+/*
 Aig_Node_t * Dec_GraphToNetworkAig( Aig_Man_t * pMan, Dec_Graph_t * pGraph )
 {
     Dec_Node_t * pNode;
@@ -235,6 +236,7 @@ Aig_Node_t * Dec_GraphToNetworkAig( Aig_Man_t * pMan, Dec_Graph_t * pGraph )
     // complement the result if necessary
     return Aig_NotCond( pNode->pFunc, Dec_GraphIsComplement(pGraph) );
 }
+*/
 
 ////////////////////////////////////////////////////////////////////////
 ///                       END OF FILE                                ///

src/sat/aig/aig.h

@@ -160,6 +160,7 @@ struct Aig_Man_t_
     Aig_SimInfo_t *  pInfo;         // random and systematic sim info for PIs
     Aig_SimInfo_t *  pInfoPi;       // temporary sim info for the PI nodes
     Aig_SimInfo_t *  pInfoTemp;     // temporary sim info for all nodes
+    Aig_Pattern_t *  pPatMask;      // the mask which shows what patterns are used
     // simulation patterns
     int              nPiWords;      // the number of words in the PI info
     int              nPatsMax;      // the max number of patterns 
@@ -169,6 +170,7 @@ struct Aig_Man_t_
     // temporary data
     Vec_Ptr_t *      vFanouts;      // temporary storage for fanouts of a node
     Vec_Ptr_t *      vToReplace;    // the nodes to replace
+    Vec_Int_t *      vClassTemp;    // temporary class representatives
 };
 
 // the simulation patter
@@ -254,6 +256,7 @@ static inline int          Aig_NodeWhatFanin( Aig_Node_t * pNode, Aig_Node_t * p
 static inline int          Aig_NodeGetLevelNew( Aig_Node_t * pNode )   { return 1 + AIG_MAX(Aig_NodeFanin0(pNode)->Level, Aig_NodeFanin1(pNode)->Level); }
 static inline int          Aig_NodeRequiredLevel( Aig_Node_t * pNode ) { return pNode->pMan->nLevelMax + 1 - pNode->LevelR; }
 
+static inline unsigned *   Aig_SimInfoForNodeId( Aig_SimInfo_t * p, int NodeId )        { assert(  p->Type ); return p->pData + p->nWords * NodeId;    }
 static inline unsigned *   Aig_SimInfoForNode( Aig_SimInfo_t * p, Aig_Node_t * pNode )  { assert(  p->Type ); return p->pData + p->nWords * pNode->Id; }
 static inline unsigned *   Aig_SimInfoForPi( Aig_SimInfo_t * p, int Num )               { assert( !p->Type ); return p->pData + p->nWords * Num;       }
 
@@ -332,15 +335,16 @@ extern Aig_Node_t *        Aig_NodeRecognizeMux( Aig_Node_t * pNode, Aig_Node_t
 extern Aig_ProofType_t     Aig_FraigProve( Aig_Man_t * pMan );
 /*=== fraigClasses.c ==========================================================*/
 extern Vec_Vec_t *         Aig_ManDeriveClassesFirst( Aig_Man_t * p, Aig_SimInfo_t * pInfoAll );
-extern void                Aig_ManUpdateClasses( Aig_Man_t * p, Aig_SimInfo_t * pInfo, Vec_Vec_t * vClasses );
+extern int                 Aig_ManUpdateClasses( Aig_Man_t * p, Aig_SimInfo_t * pInfo, Vec_Vec_t * vClasses, Aig_Pattern_t * pPatMask );
+extern void                Aig_ManCollectPatterns( Aig_Man_t * p, Aig_SimInfo_t * pInfo, Aig_Pattern_t * pMask, Vec_Ptr_t * vPats );
 /*=== fraigCnf.c ==========================================================*/
 extern Aig_ProofType_t     Aig_ClauseSolverStart( Aig_Man_t * pMan );
 /*=== fraigEngine.c ==========================================================*/
+extern void                Aig_EngineSimulateRandomFirst( Aig_Man_t * p );
 extern void                Aig_EngineSimulateFirst( Aig_Man_t * p );
 extern int                 Aig_EngineSimulate( Aig_Man_t * p );
-extern void                Aig_EngineSimulateRandomFirst( Aig_Man_t * p );
 /*=== fraigSim.c ==========================================================*/
-extern Aig_SimInfo_t *     Aig_SimInfoAlloc( int nNodes, int nWords, int Type );
+extern Aig_SimInfo_t *     Aig_SimInfoAlloc( int nNodes, int nBits, int Type );
 extern void                Aig_SimInfoClean( Aig_SimInfo_t * p );
 extern void                Aig_SimInfoRandom( Aig_SimInfo_t * p );
 extern void                Aig_SimInfoFromPattern( Aig_SimInfo_t * p, Aig_Pattern_t * pPat );
@@ -349,6 +353,8 @@ extern void                Aig_SimInfoFree( Aig_SimInfo_t * p );
 extern void                Aig_ManSimulateInfo( Aig_Man_t * p, Aig_SimInfo_t * pInfoPi, Aig_SimInfo_t * pInfoAll );
 extern Aig_Pattern_t *     Aig_PatternAlloc( int nBits );
 extern void                Aig_PatternClean( Aig_Pattern_t * pPat );
+extern void                Aig_PatternFill( Aig_Pattern_t * pPat );
+extern int                 Aig_PatternCount( Aig_Pattern_t * pPat );
 extern void                Aig_PatternRandom( Aig_Pattern_t * pPat );
 extern void                Aig_PatternFree( Aig_Pattern_t * pPat );
 

src/sat/aig/aigMan.c

@@ -42,7 +42,7 @@
 void Aig_ManSetDefaultParams( Aig_Param_t * pParam )
 {
     memset( pParam, 0, sizeof(Aig_Param_t) );
-    pParam->nPatsRand = 1024;  // the number of random patterns
+    pParam->nPatsRand = 4096;  // the number of random patterns
     pParam->nBTLimit  =   99;  // backtrack limit at the intermediate nodes
     pParam->nSeconds  =    1;  // the timeout for the final miter in seconds
 }
@@ -68,7 +68,7 @@ Aig_Man_t * Aig_ManStart( Aig_Param_t * pParam )
     memset( p, 0, sizeof(Aig_Man_t) );
     p->pParam     = &p->Param;
     p->nTravIds   =  1;
-    p->nPatsMax   = 20;
+    p->nPatsMax   = 25;
     // set the defaults
     *p->pParam    = *pParam;
     // start memory managers
@@ -84,6 +84,8 @@ Aig_Man_t * Aig_ManStart( Aig_Param_t * pParam )
     // initialize other variables
     p->vFanouts   = Vec_PtrAlloc( 10 ); 
     p->vToReplace = Vec_PtrAlloc( 10 ); 
+    p->vClassTemp = Vec_IntAlloc( 10 );
+    p->vPats      = Vec_PtrAlloc( p->nPatsMax );
     return p;
 }
 
@@ -132,6 +134,9 @@ void Aig_ManStop( Aig_Man_t * p )
     if ( p->vFanFans0 )  Vec_PtrFree( p->vFanFans0 );
     if ( p->vFanFans1 )  Vec_PtrFree( p->vFanFans1 );
     if ( p->vClasses  )  Vec_VecFree( p->vClasses );
+    // patterns
+    if ( p->vPats )      Vec_PtrFree( p->vPats );
+    if ( p->pPatMask )   Aig_PatternFree( p->pPatMask );
     // nodes
     Aig_MemFixedStop( p->mmNodes, 0 );
     Vec_PtrFree( p->vNodes );
@@ -140,6 +145,7 @@ void Aig_ManStop( Aig_Man_t * p )
     // temporary
     Vec_PtrFree( p->vFanouts );
     Vec_PtrFree( p->vToReplace );
+    Vec_IntFree( p->vClassTemp );
     Aig_TableFree( p->pTable );
     free( p );
 }

src/sat/aig/fraigClass.c

@@ -80,7 +80,7 @@ Vec_Vec_t * Aig_ManDeriveClassesFirst( Aig_Man_t * p, Aig_SimInfo_t * pInfo )
         }
     }
     stmm_free_table( tSim2Node );
-
+/*
     // print the classes
     {
         Vec_Ptr_t * vVec;
@@ -93,6 +93,8 @@ Vec_Vec_t * Aig_ManDeriveClassesFirst( Aig_Man_t * p, Aig_SimInfo_t * pInfo )
             printf( "%d ", Vec_PtrSize(vVec) );
         printf( "\n" );
     }
+*/
+    printf( "Classes = %6d. Pairs = %6d.\n", Vec_VecSize(vClasses), Vec_VecSizeSize(vClasses) - Vec_VecSize(vClasses) );
     return vClasses;
 }
 
@@ -115,14 +117,86 @@ unsigned Aig_ManHashKey( unsigned * pData, int nWords, bool fPhase )
     uKey = 0;
     if ( fPhase )
         for ( i = 0; i < nWords; i++ )
-            uKey ^= Primes[i%10] * pData[i];
+            uKey ^= i * Primes[i%10] * pData[i];
     else
         for ( i = 0; i < nWords; i++ )
-            uKey ^= Primes[i%10] * ~pData[i];
+            uKey ^= i * Primes[i%10] * ~pData[i];
     return uKey;
 }
 
 
+
+/**Function*************************************************************
+
+  Synopsis    [Splits the equivalence class.]
+
+  Description [Given an equivalence class (vClass) and the simulation info, 
+  split the class into two based on the info.]
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Aig_ManSplitClass( Aig_Man_t * p, Aig_SimInfo_t * pInfo, Vec_Int_t * vClass, Vec_Int_t * vClass2, Aig_Pattern_t * pPat )
+{
+    int NodeId, i, k, w;
+    Aig_Node_t * pRoot, * pTemp;
+    unsigned * pRootData, * pTempData;
+    assert( Vec_IntSize(vClass) > 1 );
+    assert( pInfo->nPatsCur == pPat->nBits );
+//    printf( "Class = %5d.  -->  ", Vec_IntSize(vClass) ); 
+    // clear storage for the new classes
+    Vec_IntClear( vClass2 );
+    // get the root member of the class
+    pRoot = Aig_ManNode( p, Vec_IntEntry(vClass, 0) );
+    pRootData = Aig_SimInfoForNode( pInfo, pRoot );
+    // sort the class members:
+    // (1) with the same siminfo as pRoot remain in vClass
+    // (2) nodes with other siminfo go to vClass2
+    k = 1;
+    Vec_IntForEachEntryStart( vClass, NodeId, i, 1 )
+    {
+        NodeId = Vec_IntEntry(vClass, i);
+        pTemp  = Aig_ManNode( p, NodeId );
+        pTempData = Aig_SimInfoForNode( pInfo, pTemp );
+        if ( pRoot->fPhase == pTemp->fPhase )
+        {
+            for ( w = 0; w < pInfo->nWords; w++ )
+                if ( pRootData[w] != pTempData[w] )
+                    break;
+            if ( w == pInfo->nWords ) // the same info
+                Vec_IntWriteEntry( vClass, k++, NodeId );
+            else
+            {
+                Vec_IntPush( vClass2, NodeId );
+                // record the diffs if they are not distinguished by the first pattern
+                if ( ((pRootData[0] ^ pTempData[0]) & 1) == 0 )
+                    for ( w = 0; w < pInfo->nWords; w++ )
+                        pPat->pData[w] |= (pRootData[w] ^ pTempData[w]);
+            }
+        }
+        else
+        {
+            for ( w = 0; w < pInfo->nWords; w++ )
+                if ( pRootData[w] != ~pTempData[w] )
+                    break;
+            if ( w == pInfo->nWords ) // the same info
+                Vec_IntWriteEntry( vClass, k++, NodeId );
+            else
+            {
+                Vec_IntPush( vClass2, NodeId );
+                // record the diffs if they are not distinguished by the first pattern
+                if ( ((pRootData[0] ^ ~pTempData[0]) & 1) == 0 )
+                    for ( w = 0; w < pInfo->nWords; w++ )
+                        pPat->pData[w] |= (pRootData[w] ^ ~pTempData[w]);
+            }
+        }
+    }
+    Vec_IntShrink( vClass, k );
+//    printf( "Class1 = %5d. Class2 = %5d.\n", Vec_IntSize(vClass), Vec_IntSize(vClass2) ); 
+}
+
 /**Function*************************************************************
 
   Synopsis    [Updates the equivalence classes using the simulation info.]
@@ -135,8 +209,108 @@ unsigned Aig_ManHashKey( unsigned * pData, int nWords, bool fPhase )
   SeeAlso     []
 
 ***********************************************************************/
-void Aig_ManUpdateClasses( Aig_Man_t * p, Aig_SimInfo_t * pInfo, Vec_Vec_t * vClasses )
+int Aig_ManUpdateClasses( Aig_Man_t * p, Aig_SimInfo_t * pInfo, Vec_Vec_t * vClasses, Aig_Pattern_t * pPatMask )
 {
+    Vec_Ptr_t * vClass;
+    int i, k, fSplit = 0;
+    assert( Vec_VecSize(vClasses) > 0 );
+    // collect patterns that lead to changes
+    Aig_PatternClean( pPatMask );
+    // split the classes using the new symmetry info
+    Vec_VecForEachLevel( vClasses, vClass, i )
+    {
+        if ( i == 0 )
+            continue;
+        // split vClass into two parts (vClass and vClassTemp)
+        Aig_ManSplitClass( p, pInfo, (Vec_Int_t *)vClass, p->vClassTemp, pPatMask );
+        // check if there is any splitting
+        if ( Vec_IntSize(p->vClassTemp) > 0 )
+            fSplit = 1;
+        // skip the new class if it is empty or trivial
+        if ( Vec_IntSize(p->vClassTemp) < 2 )
+            continue;
+        // consider replacing the current class with the new one
+        if ( Vec_PtrSize(vClass) == 1 )
+        {
+            assert( vClasses->pArray[i] == vClass );
+            vClasses->pArray[i] = p->vClassTemp;
+            p->vClassTemp = (Vec_Int_t *)vClass;
+            i--;
+            continue;
+        }
+        // add the new non-trival class in the end
+        Vec_PtrPush( (Vec_Ptr_t *)vClasses, p->vClassTemp );
+        p->vClassTemp = Vec_IntAlloc( 10 );
+    }
+    // free trivial classes
+    k = 0;
+    Vec_VecForEachLevel( vClasses, vClass, i )
+    {
+        assert( Vec_PtrSize(vClass) > 0 );
+        if ( Vec_PtrSize(vClass) == 1 )
+            Vec_PtrFree(vClass);
+        else
+            vClasses->pArray[k++] = vClass;
+    }
+    Vec_PtrShrink( (Vec_Ptr_t *)vClasses, k );
+    // catch the patterns which led to splitting
+    printf( "Classes = %6d. Pairs = %6d.  Patterns = %3d.\n", 
+        Vec_VecSize(vClasses), 
+        Vec_VecSizeSize(vClasses) - Vec_VecSize(vClasses), 
+        Vec_PtrSize(p->vPats) );
+    return fSplit;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Collects useful patterns.]
+
+  Description [If the flag fAddToVector is 1, creates and adds new patterns
+  to the internal storage of patterns.]
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Aig_ManCollectPatterns( Aig_Man_t * p, Aig_SimInfo_t * pInfo, Aig_Pattern_t * pMask, Vec_Ptr_t * vPats )
+{
+    Aig_SimInfo_t * pInfoRes = p->pInfo;
+    Aig_Pattern_t * pPatNew;
+    Aig_Node_t * pNode;
+    int i, k;
+
+    assert( Aig_InfoHasBit(pMask->pData, 0) == 0 );
+    for ( i = 0; i < pMask->nBits; i++ )
+    {
+        if ( vPats && Vec_PtrSize(vPats) >= p->nPatsMax )
+            break;
+        if ( i == 0 || Aig_InfoHasBit(pMask->pData, i) )
+        {
+            // expand storage if needed
+            if ( pInfoRes->nPatsCur == pInfoRes->nPatsMax )
+                Aig_SimInfoResize( pInfoRes );
+            // create a new pattern
+            if ( vPats )
+            {
+                pPatNew = Aig_PatternAlloc( Aig_ManPiNum(p) );
+                Aig_PatternClean( pPatNew );
+            }
+            // go through the PIs
+            Aig_ManForEachPi( p, pNode, k )
+            {
+                if ( Aig_InfoHasBit( Aig_SimInfoForNode(pInfo, pNode), i ) )
+                {
+                    Aig_InfoSetBit( Aig_SimInfoForPi(pInfoRes, k), pInfoRes->nPatsCur );
+                    if ( vPats ) Aig_InfoSetBit( pPatNew->pData, k );
+                }
+            }
+            // store the new pattern
+            if ( vPats ) Vec_PtrPush( vPats, pPatNew ); 
+            // increment the number of patterns stored
+            pInfoRes->nPatsCur++;
+        }
+    }
 }
 
 ////////////////////////////////////////////////////////////////////////

src/sat/aig/fraigCore.c

@@ -68,6 +68,8 @@ Aig_ProofType_t Aig_FraigProve( Aig_Man_t * pMan )
 
     // create equivalence classes
     Aig_EngineSimulateRandomFirst( pMan );
+    // reduce equivalence classes using simulation
+    Aig_EngineSimulateFirst( pMan );
     return RetValue;
 }
 

src/sat/aig/fraigEngine.c

@@ -30,6 +30,39 @@
 
 /**Function*************************************************************
 
+  Synopsis    [Simulates all nodes using random simulation for the first time.]
+
+  Description [Assigns the original simulation info and the storage for the
+  future simulation info.]
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Aig_EngineSimulateRandomFirst( Aig_Man_t * p )
+{
+    Aig_SimInfo_t * pInfoPi, * pInfoAll;
+    assert( !p->pInfo && !p->pInfoTemp );
+    // create random PI info
+    pInfoPi = Aig_SimInfoAlloc( Aig_ManPiNum(p), p->pParam->nPatsRand, 0 );
+    Aig_SimInfoRandom( pInfoPi );
+    // allocate sim info for all nodes
+    pInfoAll = Aig_SimInfoAlloc( Aig_ManNodeNum(p), p->pParam->nPatsRand, 1 );
+    // simulate though the circuit
+    Aig_ManSimulateInfo( p, pInfoPi, pInfoAll );
+    // detect classes
+    p->vClasses = Aig_ManDeriveClassesFirst( p, pInfoAll );
+    Aig_SimInfoFree( pInfoAll );
+    // save simulation info
+    p->pInfo     = pInfoPi;
+    p->pInfoPi   = Aig_SimInfoAlloc( Aig_ManPiNum(p),   Aig_ManPiNum(p)+1,  0 );
+    p->pInfoTemp = Aig_SimInfoAlloc( Aig_ManNodeNum(p), Aig_ManPiNum(p)+1,  1 );
+    p->pPatMask  = Aig_PatternAlloc( Aig_ManPiNum(p)+1 );
+}
+
+/**Function*************************************************************
+
   Synopsis    [Starts the simulation engine for the first time.]
 
   Description [Tries several random patterns and their distance-1 
@@ -43,15 +76,55 @@
 void Aig_EngineSimulateFirst( Aig_Man_t * p )
 {
     Aig_Pattern_t * pPat;
-    int i;
-    assert( Vec_PtrSize(p->vPats) == 0 );
-    for ( i = 0; i < p->nPatsMax; i++ )
-    {
+    int i, Counter;
+
+    // simulate the pattern of all zeros
     pPat = Aig_PatternAlloc( Aig_ManPiNum(p) ); 
-        Aig_PatternRandom( pPat );
+    Aig_PatternClean( pPat );
     Vec_PtrPush( p->vPats, pPat );
     if ( !Aig_EngineSimulate( p ) )
         return;
+
+    // simulate the pattern of all ones
+    pPat = Aig_PatternAlloc( Aig_ManPiNum(p) ); 
+    Aig_PatternFill( pPat );
+    Vec_PtrPush( p->vPats, pPat );
+    if ( !Aig_EngineSimulate( p ) )
+        return;
+
+    // simulate random until the number of new patterns is reasonable
+    do {
+        // generate random PI siminfo
+        Aig_SimInfoRandom( p->pInfoPi );
+        // simulate this info
+        Aig_ManSimulateInfo( p, p->pInfoPi, p->pInfoTemp );
+        // split the classes and collect the new patterns
+        if ( Aig_ManUpdateClasses( p, p->pInfoTemp, p->vClasses, p->pPatMask ) )
+            Aig_ManCollectPatterns( p, p->pInfoTemp, p->pPatMask, NULL );
+        if ( Vec_VecSize(p->vClasses) == 0 )
+            return;
+        // count the number of useful patterns
+        Counter = Aig_PatternCount(p->pPatMask);
+    }
+    while ( Counter > p->nPatsMax/2 );
+
+    // perform targetted simulation
+    for ( i = 0; i < 3; i++ )
+    {
+        assert( Vec_PtrSize(p->vPats) == 0 );
+        // generate random PI siminfo
+        Aig_SimInfoRandom( p->pInfoPi );
+        // simulate this info
+        Aig_ManSimulateInfo( p, p->pInfoPi, p->pInfoTemp );
+        // split the classes and collect the new patterns
+        if ( Aig_ManUpdateClasses( p, p->pInfoTemp, p->vClasses, p->pPatMask ) )
+            Aig_ManCollectPatterns( p, p->pInfoTemp, p->pPatMask, p->vPats );
+        if ( Vec_VecSize(p->vClasses) == 0 )
+            return;
+        // simulate the remaining patters
+        if ( Vec_PtrSize(p->vPats) > 0 )
+            if ( !Aig_EngineSimulate( p ) )
+                return;
     }
 }
 
@@ -79,51 +152,21 @@ int Aig_EngineSimulate( Aig_Man_t * p )
     {
         // get the pattern and create new siminfo
         pPat = Vec_PtrPop(p->vPats);
+        assert( pPat->nBits == Aig_ManPiNum(p) );
         // create the new siminfo
         Aig_SimInfoFromPattern( p->pInfoPi, pPat );
-        // free the patter
+        // free the pattern
         Aig_PatternFree( pPat );
 
         // simulate this info
         Aig_ManSimulateInfo( p, p->pInfoPi, p->pInfoTemp );
         // split the classes and collect the new patterns
-        Aig_ManUpdateClasses( p, p->pInfoTemp, p->vClasses );
+        if ( Aig_ManUpdateClasses( p, p->pInfoTemp, p->vClasses, p->pPatMask ) )
+            Aig_ManCollectPatterns( p, p->pInfoTemp, p->pPatMask, p->vPats );
     }
     return Vec_VecSize(p->vClasses) > 0;
 }
 
-/**Function*************************************************************
-
-  Synopsis    [Simulates all nodes using random simulation for the first time.]
-
-  Description [Assigns the original simulation info and the storage for the
-  future simulation info.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Aig_EngineSimulateRandomFirst( Aig_Man_t * p )
-{
-    Aig_SimInfo_t * pInfoPi, * pInfoAll;
-    assert( !p->pInfo && !p->pInfoTemp );
-    // create random PI info
-    pInfoPi = Aig_SimInfoAlloc( p->vPis->nSize, Aig_BitWordNum(p->pParam->nPatsRand), 0 );
-    Aig_SimInfoRandom( pInfoPi );
-    // allocate sim info for all nodes
-    pInfoAll = Aig_SimInfoAlloc( p->vNodes->nSize, pInfoPi->nWords, 1 );
-    // simulate though the circuit
-    Aig_ManSimulateInfo( p, pInfoPi, pInfoAll );
-    // detect classes
-    p->vClasses = Aig_ManDeriveClassesFirst( p, pInfoAll );
-    Aig_SimInfoFree( pInfoAll );
-    // save simulation info
-    p->pInfo     = pInfoPi;
-    p->pInfoPi   = Aig_SimInfoAlloc( p->vPis->nSize,   Aig_BitWordNum(p->vPis->nSize),  0 );
-    p->pInfoTemp = Aig_SimInfoAlloc( p->vNodes->nSize, Aig_BitWordNum(p->vPis->nSize),  1 );
-}
-
 ////////////////////////////////////////////////////////////////////////
 ///                       END OF FILE                                ///
 ////////////////////////////////////////////////////////////////////////

src/sat/aig/fraigSim.c

@@ -80,7 +80,7 @@ void Aig_ManSimulateInfo( Aig_Man_t * p, Aig_SimInfo_t * pInfoPi, Aig_SimInfo_t
                 pDataAnd[k] =  pData0[k] &  pData1[k];
     }
     // derive the PO siminfo
-    Aig_ManForEachPi( p, pNode, i )
+    Aig_ManForEachPo( p, pNode, i )
     {
         pDataPo  = Aig_SimInfoForNode( pInfoAll, pNode );
         pDataAnd = Aig_SimInfoForNode( pInfoAll, Aig_NodeFanin0(pNode) );
@@ -106,16 +106,17 @@ void Aig_ManSimulateInfo( Aig_Man_t * p, Aig_SimInfo_t * pInfoPi, Aig_SimInfo_t
   SeeAlso     []
 
 ***********************************************************************/
-Aig_SimInfo_t * Aig_SimInfoAlloc( int nNodes, int nWords, int Type )
+Aig_SimInfo_t * Aig_SimInfoAlloc( int nNodes, int nBits, int Type )
 {
     Aig_SimInfo_t * p;
     p = ALLOC( Aig_SimInfo_t, 1 );
     memset( p, 0, sizeof(Aig_SimInfo_t) );
     p->Type     = Type;
     p->nNodes   = nNodes;
-    p->nWords   = nWords;
-    p->nPatsMax = nWords * sizeof(unsigned) * 8;
-    p->pData    = ALLOC( unsigned, nNodes * nWords );
+    p->nWords   = Aig_BitWordNum(nBits);
+    p->nPatsCur = nBits;
+    p->nPatsMax = p->nWords * sizeof(unsigned) * 8;
+    p->pData    = ALLOC( unsigned, nNodes * p->nWords );
     return p;
 }
 
@@ -161,7 +162,6 @@ void Aig_SimInfoRandom( Aig_SimInfo_t * p )
         pData = p->pData + p->nWords * i;
         *pData <<= 1;
     }
-    p->nPatsCur = p->nPatsMax;
 }
 
 /**Function*************************************************************
@@ -180,8 +180,8 @@ void Aig_SimInfoFromPattern( Aig_SimInfo_t * p, Aig_Pattern_t * pPat )
     unsigned * pData;
     int i, k;
     assert( p->Type == 0 );
-    assert( p->nNodes == pPat->nBits );
-    for ( i = 0; i < p->nNodes; i++ )
+    assert( p->nPatsCur == pPat->nBits+1 );
+    for ( i = 0; i < p->nPatsCur; i++ )
     {
         // get the pointer to the bitdata for node i
         pData = p->pData + p->nWords * i;
@@ -192,8 +192,8 @@ void Aig_SimInfoFromPattern( Aig_SimInfo_t * p, Aig_Pattern_t * pPat )
         else
             for ( k = 0; k < p->nWords; k++ )
                 pData[k] = 0;
-        // flip one bit
-        Aig_InfoXorBit( pData, i );
+        // flip one bit, starting from the first pattern
+        if ( i ) Aig_InfoXorBit( pData, i-1 );
     }
 }
 
@@ -285,6 +285,22 @@ void Aig_PatternClean( Aig_Pattern_t * pPat )
 
 /**Function*************************************************************
 
+  Synopsis    [Cleans the pattern.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Aig_PatternFill( Aig_Pattern_t * pPat )
+{
+    memset( pPat->pData, 0xff, sizeof(unsigned) * pPat->nWords );
+}
+
+/**Function*************************************************************
+
   Synopsis    [Sets the random pattern.]
 
   Description []
@@ -303,6 +319,25 @@ void Aig_PatternRandom( Aig_Pattern_t * pPat )
 
 /**Function*************************************************************
 
+  Synopsis    [Counts the number of 1s in the pattern.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Aig_PatternCount( Aig_Pattern_t * pPat )
+{
+    int i, Counter = 0;
+    for ( i = 0; i < pPat->nBits; i++ )
+        Counter += Aig_InfoHasBit( pPat->pData, i );
+    return Counter;
+}
+
+/**Function*************************************************************
+
   Synopsis    [Deallocates the pattern.]
 
   Description []

src/sat/csat/csat_apis.c

@@ -34,6 +34,7 @@ struct ABC_ManagerStruct_t
     Abc_Ntk_t *           pNtk;          // the starting ABC network
     Abc_Ntk_t *           pTarget;       // the AIG representing the target
     char *                pDumpFileName; // the name of the file to dump the target network
+    Extra_MmFlex_t *      pMmNames;      // memory manager for signal names
     // solving parameters
     int                   mode;          // 0 = brute-force SAT;  1 = resource-aware FRAIG
     int                   nSeconds;      // time limit for pure SAT solving
@@ -76,6 +77,7 @@ ABC_Manager ABC_InitManager()
     mng->pNtk->pName = util_strsav("csat_network");
     mng->tName2Node = stmm_init_table(strcmp, stmm_strhash);
     mng->tNode2Name = stmm_init_table(stmm_ptrcmp, stmm_ptrhash);
+    mng->pMmNames   = Extra_MmFlexStart();
     mng->vNodes     = Vec_PtrAlloc( 100 );
     mng->vValues    = Vec_IntAlloc( 100 );
     mng->nSeconds   = ABC_DEFAULT_TIMEOUT;
@@ -97,6 +99,7 @@ void ABC_QuitManager( ABC_Manager mng )
 {
     if ( mng->tNode2Name ) stmm_free_table( mng->tNode2Name );
     if ( mng->tName2Node ) stmm_free_table( mng->tName2Node );
+    if ( mng->pMmNames )   Extra_MmFlexStop( mng->pMmNames, 0 );
     if ( mng->pNtk )       Abc_NtkDelete( mng->pNtk );
     if ( mng->pTarget )    Abc_NtkDelete( mng->pTarget );
     if ( mng->vNodes )     Vec_PtrFree( mng->vNodes );
@@ -146,9 +149,15 @@ void ABC_SetSolveOption( ABC_Manager mng, enum ABC_OptionT option )
 int ABC_AddGate( ABC_Manager mng, enum GateType type, char * name, int nofi, char ** fanins, int dc_attr )
 {
     Abc_Obj_t * pObj, * pFanin;
-    char * pSop;
+    char * pSop, * pNewName;
     int i;
 
+    // save the name in the local memory manager
+    pNewName = Extra_MmFlexEntryFetch( mng->pMmNames, strlen(name) + 1 );
+    strcpy( pNewName, name );
+    name = pNewName;
+
+    // consider different cases, create the node, and map the node into the name
     switch( type )
     {
     case ABC_BPI:
@@ -250,6 +259,8 @@ int ABC_AddGate( ABC_Manager mng, enum GateType type, char * name, int nofi, cha
         printf( "ABC_AddGate: Unknown gate type.\n" );
         break;
     }
+
+    // map the name into the node
     if ( stmm_insert( mng->tName2Node, name, (char *)pObj ) )
         { printf( "ABC_AddGate: The same gate \"%s\" is added twice.\n", name ); return 0; }
     return 1;
@@ -690,6 +701,101 @@ char * ABC_GetNodeName( ABC_Manager mng, Abc_Obj_t * pNode )
     return pName;
 }
 
+
+
+/**Function*************************************************************
+
+  Synopsis    [This procedure applies a rewriting script to the network.]
+
+  Description [Rewriting is performed without regard for the number of 
+  logic levels. This corresponds to "circuit compression for formal 
+  verification" (Per Bjesse et al, ICCAD 2004) but implemented in a more 
+  exhaustive way than in the above paper.]
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void ABC_PerformRewriting( ABC_Manager mng )
+{
+    void * pAbc;
+    char Command[1000];
+    int clkBalan, clkResyn, clk;
+    int fPrintStats = 1;
+    int fUseResyn   = 1;
+
+    // procedures to get the ABC framework and execute commands in it
+    extern void * Abc_FrameGetGlobalFrame();
+    extern void Abc_FrameReplaceCurrentNetwork( void * p, Abc_Ntk_t * pNtk );
+    extern int  Cmd_CommandExecute( void * p, char * sCommand );
+    extern Abc_Ntk_t * Abc_FrameReadNtk( void * p );
+
+
+    // get the pointer to the ABC framework
+    pAbc = Abc_FrameGetGlobalFrame();
+    assert( pAbc != NULL );
+
+    // replace the current network by the target network
+    Abc_FrameReplaceCurrentNetwork( pAbc, mng->pTarget );
+
+clk = clock();
+    //////////////////////////////////////////////////////////////////////////
+    // balance
+    sprintf( Command, "balance" );
+    if ( Cmd_CommandExecute( pAbc, Command ) )
+    {
+        fprintf( stdout, "Cannot execute command \"%s\".\n", Command );
+        return;
+    }
+clkBalan = clock() - clk;
+
+    //////////////////////////////////////////////////////////////////////////
+    // print stats
+    if ( fPrintStats )
+    {
+        sprintf( Command, "print_stats" );
+        if ( Cmd_CommandExecute( pAbc, Command ) )
+        {
+            fprintf( stdout, "Cannot execute command \"%s\".\n", Command );
+            return;
+        }
+    }
+
+clk = clock();
+    //////////////////////////////////////////////////////////////////////////
+    // synthesize
+    if ( fUseResyn )
+    {
+        sprintf( Command, "balance; rewrite -l; rewrite -lz; balance; rewrite -lz; balance" );
+        if ( Cmd_CommandExecute( pAbc, Command ) )
+        {
+            fprintf( stdout, "Cannot execute command \"%s\".\n", Command );
+            return;
+        }
+    }
+clkResyn = clock() - clk;
+
+    //////////////////////////////////////////////////////////////////////////
+    // print stats
+    if ( fPrintStats )
+    {
+        sprintf( Command, "print_stats" );
+        if ( Cmd_CommandExecute( pAbc, Command ) )
+        {
+            fprintf( stdout, "Cannot execute command \"%s\".\n", Command );
+            return;
+        }
+    }
+    printf( "Balancing = %6.2f sec   ",   (float)(clkBalan)/(float)(CLOCKS_PER_SEC) );
+    printf( "Rewriting = %6.2f sec   ",   (float)(clkResyn)/(float)(CLOCKS_PER_SEC) );
+    printf( "\n" );
+
+    // read the target network from the current network
+    mng->pTarget = Abc_NtkDup( Abc_FrameReadNtk(pAbc) );
+}
+
+
 ////////////////////////////////////////////////////////////////////////
 ///                       END OF FILE                                ///
 ////////////////////////////////////////////////////////////////////////

src/sat/csat/csat_apis.h

@@ -171,6 +171,8 @@ extern void                  ABC_Dump_Bench_File(ABC_Manager mng);
 extern void                  ABC_QuitManager( ABC_Manager mng );
 extern void                  ABC_TargetResFree( ABC_Target_ResultT * p );
 
+extern void                  ABC_PerformRewriting( ABC_Manager mng );
+
 ////////////////////////////////////////////////////////////////////////
 ///                       END OF FILE                                ///
 ////////////////////////////////////////////////////////////////////////

src/sat/fraig/fraigSat.c

@@ -156,6 +156,132 @@ int Fraig_ManCheckMiter( Fraig_Man_t * p )
 
 /**Function*************************************************************
 
+  Synopsis    [Returns 1 if pOld is in the TFI of pNew.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Fraig_MarkTfi_rec( Fraig_Man_t * pMan, Fraig_Node_t * pNode )
+{
+    // skip the visited node
+    if ( pNode->TravId == pMan->nTravIds )
+        return 0;
+    pNode->TravId = pMan->nTravIds;
+    // skip the PI node
+    if ( pNode->NumPi >= 0 )
+        return 1;
+    // check the children
+    return Fraig_MarkTfi_rec( pMan, Fraig_Regular(pNode->p1) ) +
+           Fraig_MarkTfi_rec( pMan, Fraig_Regular(pNode->p2) );
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Returns 1 if pOld is in the TFI of pNew.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Fraig_MarkTfi2_rec( Fraig_Man_t * pMan, Fraig_Node_t * pNode )
+{
+    // skip the visited node
+    if ( pNode->TravId == pMan->nTravIds )
+        return 0;
+    // skip the boundary node
+    if ( pNode->TravId == pMan->nTravIds-1 )
+    {
+        pNode->TravId = pMan->nTravIds;
+        return 1;
+    }
+    pNode->TravId = pMan->nTravIds;
+    // skip the PI node
+    if ( pNode->NumPi >= 0 )
+        return 1;
+    // check the children
+    return Fraig_MarkTfi2_rec( pMan, Fraig_Regular(pNode->p1) ) +
+           Fraig_MarkTfi2_rec( pMan, Fraig_Regular(pNode->p2) );
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Returns 1 if pOld is in the TFI of pNew.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Fraig_MarkTfi3_rec( Fraig_Man_t * pMan, Fraig_Node_t * pNode )
+{
+    // skip the visited node
+    if ( pNode->TravId == pMan->nTravIds )
+        return 1;
+    // skip the boundary node
+    if ( pNode->TravId == pMan->nTravIds-1 )
+    {
+        pNode->TravId = pMan->nTravIds;
+        return 1;
+    }
+    pNode->TravId = pMan->nTravIds;
+    // skip the PI node
+    if ( pNode->NumPi >= 0 )
+        return 0;
+    // check the children
+    return Fraig_MarkTfi3_rec( pMan, Fraig_Regular(pNode->p1) ) *
+           Fraig_MarkTfi3_rec( pMan, Fraig_Regular(pNode->p2) );
+}
+
+/**Function*************************************************************
+
+  Synopsis    []
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Fraig_VarsStudy( Fraig_Man_t * p, Fraig_Node_t * pOld, Fraig_Node_t * pNew )
+{
+    int NumPis, NumCut, fContain;
+
+    // mark the TFI of pNew
+    p->nTravIds++;
+    NumPis = Fraig_MarkTfi_rec( p, pNew );
+    printf( "(%d)(%d,%d):", NumPis, pOld->Level, pNew->Level );
+
+    // check if the old is in the TFI
+    if ( pOld->TravId == p->nTravIds )
+    {
+        printf( "* " );
+        return;
+    }
+
+    // count the boundary of nodes in pOld
+    p->nTravIds++;
+    NumCut = Fraig_MarkTfi2_rec( p, pOld );
+    printf( "%d", NumCut );
+
+    // check if the new is contained in the old's support
+    p->nTravIds++;
+    fContain = Fraig_MarkTfi3_rec( p, pNew );
+    printf( "%c ", fContain? '+':'-' );
+}
+
+
+/**Function*************************************************************
+
   Synopsis    [Checks whether two nodes are functinally equivalent.]
 
   Description [The flag (fComp) tells whether the nodes to be checked
@@ -202,6 +328,7 @@ int Fraig_NodeIsEquivalent( Fraig_Man_t * p, Fraig_Node_t * pOld, Fraig_Node_t *
 
     // get the logic cone
 clk = clock();
+//    Fraig_VarsStudy( p, pOld, pNew );
     Fraig_OrderVariables( p, pOld, pNew );
 //    Fraig_PrepareCones( p, pOld, pNew );
 p->timeTrav += clock() - clk;
@@ -223,18 +350,20 @@ if ( fVerbose )
     Msat_SolverPrepare( p->pSat, p->vVarsInt );
 //p->time3 += clock() - clk;
 
+
     // solve under assumptions
     // A = 1; B = 0     OR     A = 1; B = 1 
     Msat_IntVecClear( p->vProj );
     Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pOld->Num, 0) );
     Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNew->Num, !fComp) );
+
+//Msat_SolverWriteDimacs( p->pSat, "temp_fraig.cnf" );
+
     // run the solver
 clk = clock();
     RetValue1 = Msat_SolverSolve( p->pSat, p->vProj, nBTLimit, nTimeLimit );
 p->timeSat += clock() - clk;
 
-//Msat_SolverWriteDimacs( p->pSat, "temp_fraig.cnf" );
-
     if ( RetValue1 == MSAT_FALSE )
     {
 //p->time1 += clock() - clk;

src/sat/msat/msatClause.c

@@ -194,7 +194,7 @@ bool Msat_ClauseCreate( Msat_Solver_t * p, Msat_IntVec_t * vLits, bool fLearned,
         {
             Msat_SolverVarBumpActivity( p, pLits[i] );
 //            Msat_SolverVarBumpActivity( p, pLits[i] );
-            p->pFreq[ MSAT_LIT2VAR(pLits[i]) ]++;
+//            p->pFreq[ MSAT_LIT2VAR(pLits[i]) ]++;
         }
     }
 

src/sat/msat/msatSolverCore.c

@@ -140,8 +140,8 @@ bool Msat_SolverSolve( Msat_Solver_t * p, Msat_IntVec_t * vAssumps, int nBackTra
     int64 nConflictsOld = p->Stats.nConflicts;
     int64 nDecisionsOld = p->Stats.nDecisions;
 
-    p->pFreq = ALLOC( int, p->nVarsAlloc );
-    memset( p->pFreq, 0, sizeof(int) * p->nVarsAlloc );
+//    p->pFreq = ALLOC( int, p->nVarsAlloc );
+//    memset( p->pFreq, 0, sizeof(int) * p->nVarsAlloc );
  
     if ( vAssumps )
     {

todo.txt

+Minor things:
+
+- add required time support
+
+- clean end-of-line markers (CR is more preferable than CR-LF)
+
+- mysterious Mac problem (fixed?)
+- mysterious Solaris problem (fixed)
+
+- QR's compilation problems
+
+- add storage for internal memory for node names in the ABC_ package
+
+- prevent node name clash between PO and internal names (i.e. [484])
+- add the output of ABC version/platform in the output files
+
+- fix gcc compiler warnings
+
+- update CVS regularly
+
+
+Major things:
+
+- substantially improving performance of FRAIGing 
+(used in equivalence checking and lossless synthesis)
+
+- developing a new (much more efficient and faster) AIG rewriting package
+
+- implementing additional rewriting options for delay optimization
+
+- making technology mapping applicable to very large designs by adding 
+on-demand cut computation currenlty available as a stand-alone command "cut"
+
+- experimenting with yield-aware standard-cell mapping
+
+- developing a hybrid mapper for arbitrary programmable macrocell 
+architecture specified using a configuration file (this mapper should work 
+for both cell-evalution and mainstream FPGA mapping)
+
+- developing incremental retiming and incremental integrated sequential 
+synthesis
+
+- developing sequential verification combined with integrated sequential 
+synthesis 
+
+- add hierarchical BLIF interface (for designs with black boxes)
+