Adding support for standard-cell mapping.

src/aig/gia/gia.h

@@ -129,6 +129,7 @@ struct Gia_Man_t_
     Vec_Int_t *    vFanoutNums;   // static fanout
     Vec_Int_t *    vFanout;       // static fanout
     Vec_Int_t *    vMapping;      // mapping for each node
+    Vec_Int_t *    vCellMapping;  // mapping for each node
     Vec_Int_t *    vPacking;      // packing information
     Vec_Int_t *    vLutConfigs;   // LUT configurations
     Abc_Cex_t *    pCexComb;      // combinational counter-example
@@ -282,6 +283,10 @@ struct Jf_Par_t_
     word           Edge;
     word           Clause;
     word           Mux7;
+    float          MapDelay;
+    float          MapArea;
+    float          MapDelayTarget;
+    float          Epsilon;
     float *        pTimesArr;
     float *        pTimesReq;
 };
@@ -919,6 +924,13 @@ static inline int *       Gia_ObjLutFanins( Gia_Man_t * p, int Id )         { re
 static inline int         Gia_ObjLutFanin( Gia_Man_t * p, int Id, int i )   { return Gia_ObjLutFanins(p, Id)[i];                                            }
 static inline int         Gia_ObjLutIsMux( Gia_Man_t * p, int Id )          { return (int)(Gia_ObjLutFanins(p, Id)[Gia_ObjLutSize(p, Id)] == -Id);          }
 
+static inline int         Gia_ManHasCellMapping( Gia_Man_t * p )            { return p->vCellMapping != NULL;                                               }
+static inline int         Gia_ObjIsCell( Gia_Man_t * p, int iLit )          { return Vec_IntEntry(p->vCellMapping, iLit) != 0;                              }
+static inline int         Gia_ObjCellSize( Gia_Man_t * p, int iLit )        { return Vec_IntEntry(p->vCellMapping, Vec_IntEntry(p->vCellMapping, iLit));    }
+static inline int *       Gia_ObjCellFanins( Gia_Man_t * p, int iLit )      { return Vec_IntEntryP(p->vCellMapping, Vec_IntEntry(p->vCellMapping, iLit))+1; }
+static inline int         Gia_ObjCellFanin( Gia_Man_t * p, int iLit, int i ){ return Gia_ObjCellFanins(p, iLit)[i];                                         }
+static inline int         Gia_ObjCellId( Gia_Man_t * p, int iLit )          { return Gia_ObjCellFanins(p, iLit)[Gia_ObjCellSize(p, iLit)];                  }
+
 #define Gia_ManForEachLut( p, i )                                       \
     for ( i = 1; i < Gia_ManObjNum(p); i++ ) if ( !Gia_ObjIsLut(p, i) ) {} else
 #define Gia_LutForEachFanin( p, i, iFan, k )                            \
@@ -926,6 +938,11 @@ static inline int         Gia_ObjLutIsMux( Gia_Man_t * p, int Id )          { re
 #define Gia_LutForEachFaninObj( p, i, pFanin, k )                       \
     for ( k = 0; k < Gia_ObjLutSize(p,i) && ((pFanin = Gia_ManObj(p, Gia_ObjLutFanins(p,i)[k])),1); k++ )
 
+#define Gia_ManForEachCell( p, i )                                      \
+    for ( i = 2; i < 2*Gia_ManObjNum(p); i++ ) if ( !Gia_ObjIsCell(p, i) ) {} else
+#define Gia_CellForEachFanin( p, i, iFanLit, k )                        \
+    for ( k = 0; k < Gia_ObjCellSize(p,i) && ((iFanLit = Gia_ObjCellFanins(p,i)[k]),1); k++ )
+
 ////////////////////////////////////////////////////////////////////////
 ///                      MACRO DEFINITIONS                           ///
 ////////////////////////////////////////////////////////////////////////

src/aig/gia/giaMan.c

@@ -109,6 +109,7 @@ void Gia_ManStop( Gia_Man_t * p )
     Vec_WrdFreeP( &p->vTtMemory );
     Vec_PtrFreeP( &p->vTtInputs );
     Vec_IntFreeP( &p->vMapping );
+    Vec_IntFreeP( &p->vCellMapping );
     Vec_IntFreeP( &p->vPacking );
     Vec_FltFreeP( &p->vInArrs );
     Vec_FltFreeP( &p->vOutReqs );

src/base/abci/abc.c

@@ -25264,6 +25264,11 @@ int Abc_CommandAbc9Put( Abc_Frame_t * pAbc, int argc, char ** argv )
         extern Abc_Ntk_t * Abc_NtkFromMappedGia( Gia_Man_t * p );
         pNtk = Abc_NtkFromMappedGia( pAbc->pGia );
     }
+    else if ( Gia_ManHasCellMapping(pAbc->pGia) )
+    {
+        extern Abc_Ntk_t * Abc_NtkFromCellMappedGia( Gia_Man_t * p );
+        pNtk = Abc_NtkFromCellMappedGia( pAbc->pGia );
+    }
     else if ( Gia_ManHasDangling(pAbc->pGia) == 0 )
     {
         pMan = Gia_ManToAig( pAbc->pGia, 0 );

src/base/abci/abcDar.c

@@ -35,6 +35,7 @@
 #include "opt/csw/csw.h"
 #include "proof/pdr/pdr.h"
 #include "sat/bmc/bmc.h"
+#include "map/mio/mio.h"
 
 ABC_NAMESPACE_IMPL_START
 
@@ -798,6 +799,116 @@ Abc_Ntk_t * Abc_NtkFromMappedGia( Gia_Man_t * p )
     return pNtkNew;
 }
 
+/**Function*************************************************************
+
+  Synopsis    [Converts the network from the mapped GIA manager.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+static inline void Abc_NtkFromCellWrite( Vec_Int_t * vCopyLits, int i, int c, int Id )
+{
+    Vec_IntWriteEntry( vCopyLits, Abc_Var2Lit(i, c), Id );
+}
+static inline Abc_Obj_t * Abc_NtkFromCellRead( Abc_Ntk_t * p, Vec_Int_t * vCopyLits, int i, int c )
+{
+    Abc_Obj_t * pObjNew;
+    int iObjNew = Vec_IntEntry( vCopyLits, Abc_Var2Lit(i, c) );
+    if ( iObjNew >= 0 )
+        return Abc_NtkObj(p, iObjNew);
+    if ( i == 0 )
+        pObjNew = c ? Abc_NtkCreateNodeConst1(p) : Abc_NtkCreateNodeConst0(p);
+    else
+    {
+        iObjNew = Vec_IntEntry( vCopyLits, Abc_Var2Lit(i, !c) );   assert( iObjNew >= 0 );
+        pObjNew = Abc_NtkCreateNodeInv( p, Abc_NtkObj(p, iObjNew) );
+    }
+    Abc_NtkFromCellWrite( vCopyLits, i, c, Abc_ObjId(pObjNew) );
+    return pObjNew;
+}
+Abc_Ntk_t * Abc_NtkFromCellMappedGia( Gia_Man_t * p )
+{
+    int fVerbose = 0;
+    int fDuplicate = 1;
+    Abc_Ntk_t * pNtkNew;
+    Vec_Int_t * vCopyLits;
+    Abc_Obj_t * pObjNew, * pObjNewLi, * pObjNewLo;
+    Gia_Obj_t * pObj, * pObjLi, * pObjLo;
+    int i, k, iLit, iFanLit, nDupGates, nCells; 
+    Mio_Cell_t * pCells = Mio_CollectRootsNewDefault( 6, &nCells, 0 );
+    assert( Gia_ManHasCellMapping(p) );
+    // start network
+    pNtkNew = Abc_NtkAlloc( ABC_NTK_LOGIC, ABC_FUNC_MAP, 1 );
+    pNtkNew->pName = Extra_UtilStrsav(p->pName);
+    pNtkNew->pSpec = Extra_UtilStrsav(p->pSpec);
+    assert( pNtkNew->pManFunc == Abc_FrameReadLibGen() );
+    vCopyLits = Vec_IntStartFull( 2*Gia_ManObjNum(p) );
+    // create PIs
+    Gia_ManForEachPi( p, pObj, i )
+        Abc_NtkFromCellWrite( vCopyLits, Gia_ObjId(p, pObj), 0, Abc_ObjId( Abc_NtkCreatePi( pNtkNew ) ) );
+    // create POs
+    Gia_ManForEachPo( p, pObj, i )
+        Abc_NtkFromCellWrite( vCopyLits, Gia_ObjId(p, pObj), 0, Abc_ObjId( Abc_NtkCreatePo( pNtkNew ) ) );
+    // create as many latches as there are registers in the manager
+    Gia_ManForEachRiRo( p, pObjLi, pObjLo, i )
+    {
+        pObjNew = Abc_NtkCreateLatch( pNtkNew );
+        pObjNewLi = Abc_NtkCreateBi( pNtkNew );
+        pObjNewLo = Abc_NtkCreateBo( pNtkNew );
+        Abc_ObjAddFanin( pObjNew, pObjNewLi );
+        Abc_ObjAddFanin( pObjNewLo, pObjNew );
+//        pObjLi->Value = Abc_ObjId( pObjNewLi );
+//        pObjLo->Value = Abc_ObjId( pObjNewLo );
+        Abc_NtkFromCellWrite( vCopyLits, Gia_ObjId(p, pObjLi), 0, Abc_ObjId( pObjNewLi ) );
+        Abc_NtkFromCellWrite( vCopyLits, Gia_ObjId(p, pObjLo), 0, Abc_ObjId( pObjNewLo ) );
+        Abc_LatchSetInit0( pObjNew );
+    }
+    // rebuild the AIG
+    Gia_ManForEachCell( p, iLit )
+    {
+        assert( Vec_IntEntry(vCopyLits, iLit) == -1 );
+        pObjNew = Abc_NtkCreateNode( pNtkNew );
+        Gia_CellForEachFanin( p, iLit, iFanLit, k )
+            Abc_ObjAddFanin( pObjNew, Abc_NtkFromCellRead(pNtkNew, vCopyLits, Abc_Lit2Var(iFanLit), Abc_LitIsCompl(iFanLit)) );
+        pObjNew->pData = Mio_LibraryReadGateByName( (Mio_Library_t *)pNtkNew->pManFunc, pCells[Gia_ObjCellId(p, iLit)].pName, NULL );
+        Abc_NtkFromCellWrite( vCopyLits, Abc_Lit2Var(iLit), Abc_LitIsCompl(iLit), Abc_ObjId(pObjNew) );
+    }
+    // connect the PO nodes
+    Gia_ManForEachCo( p, pObj, i )
+    {
+        pObjNew = Abc_NtkFromCellRead( pNtkNew, vCopyLits, Gia_ObjFaninId0p(p, pObj), Gia_ObjFaninC0(pObj) );
+        Abc_ObjAddFanin( Abc_NtkCo(pNtkNew, i), pObjNew );
+    }
+    // create names
+    Abc_NtkAddDummyPiNames( pNtkNew );
+    Abc_NtkAddDummyPoNames( pNtkNew );
+    Abc_NtkAddDummyBoxNames( pNtkNew );
+
+    // decouple the PO driver nodes to reduce the number of levels
+    nDupGates = Abc_NtkLogicMakeSimpleCos( pNtkNew, fDuplicate );
+    if ( fVerbose && nDupGates && !Abc_FrameReadFlag("silentmode") )
+    {
+        if ( !fDuplicate )
+            printf( "Added %d buffers/inverters to decouple the CO drivers.\n", nDupGates );
+        else
+            printf( "Duplicated %d gates to decouple the CO drivers.\n", nDupGates );
+    }
+    assert( Gia_ManPiNum(p) == Abc_NtkPiNum(pNtkNew) );
+    assert( Gia_ManPoNum(p) == Abc_NtkPoNum(pNtkNew) );
+    assert( Gia_ManRegNum(p) == Abc_NtkLatchNum(pNtkNew) );
+    Vec_IntFree( vCopyLits );
+    ABC_FREE( pCells );
+
+    // check the resulting AIG
+    if ( !Abc_NtkCheck( pNtkNew ) )
+        Abc_Print( 1, "Abc_NtkFromMappedGia(): Network check has failed.\n" );
+    return pNtkNew;
+}
+
 
 /**Function*************************************************************
 

src/base/abci/abcPrint.c

@@ -287,6 +287,9 @@ void Abc_NtkPrintStats( Abc_Ntk_t * pNtk, int fFactored, int fSaveBest, int fDum
         assert( pNtk->pManFunc == Abc_FrameReadLibGen() );
         Abc_Print( 1,"  area =%5.2f", Abc_NtkGetMappedArea(pNtk) );
         Abc_Print( 1,"  delay =%5.2f", Abc_NtkDelayTrace(pNtk, NULL, NULL, 0) );
+        if ( pNtk->pManTime )
+            Abc_ManTimeStop( pNtk->pManTime );
+        pNtk->pManTime = NULL;
     }
     else if ( !Abc_NtkHasBlackbox(pNtk) )
     {