Commit 3e150dd5 by Alan Mishchenko

Adding dumping of genlib library in Verilog.

parent d51f7989
......@@ -121,6 +121,36 @@ static inline void Exp_Print( int nVars, Vec_Int_t * p )
Exp_PrintLit( nVars, Vec_IntEntryLast(p) );
Abc_Print( 1, "\n" );
}
static inline void Exp_PrintNodeVerilog( FILE * pFile, int nVars, Vec_Int_t * p, Vec_Ptr_t * vNames, int Node, int fCompl )
{
extern void Exp_PrintLitVerilog( FILE * pFile, int nVars, Vec_Int_t * p, Vec_Ptr_t * vNames, int Lit );
if ( Vec_IntEntry(p, 2*Node+1) >= 2*nVars )
fprintf( pFile, "(" );
Exp_PrintLitVerilog( pFile, nVars, p, vNames, Vec_IntEntry(p, 2*Node+1) ^ fCompl );
if ( Vec_IntEntry(p, 2*Node+1) >= 2*nVars )
fprintf( pFile, ")" );
fprintf( pFile, " %c ", fCompl ? '|' : '&' );
if ( Vec_IntEntry(p, 2*Node+0) >= 2*nVars )
fprintf( pFile, "(" );
Exp_PrintLitVerilog( pFile, nVars, p, vNames, Vec_IntEntry(p, 2*Node+0) ^ fCompl );
if ( Vec_IntEntry(p, 2*Node+0) >= 2*nVars )
fprintf( pFile, ")" );
}
static inline void Exp_PrintLitVerilog( FILE * pFile, int nVars, Vec_Int_t * p, Vec_Ptr_t * vNames, int Lit )
{
if ( Lit == EXP_CONST0 )
fprintf( pFile, "1\'b0" );
else if ( Lit == EXP_CONST1 )
fprintf( pFile, "1\'b1" );
else if ( Lit < 2 * nVars )
fprintf( pFile, "%s%s", (Lit&1) ? "~" : "", (char *)Vec_PtrEntry(vNames, Lit/2) );
else
Exp_PrintNodeVerilog( pFile, nVars, p, vNames, Lit/2-nVars, Lit&1 );
}
static inline void Exp_PrintVerilog( FILE * pFile, int nVars, Vec_Int_t * p, Vec_Ptr_t * vNames )
{
Exp_PrintLitVerilog( pFile, nVars, p, vNames, Vec_IntEntryLast(p) );
}
static inline Vec_Int_t * Exp_Reverse( Vec_Int_t * p )
{
Vec_IntReverseOrder( p );
......
......@@ -408,6 +408,7 @@ int Mio_CommandWriteGenlib( Abc_Frame_t * pAbc, int argc, char **argv )
FILE * pOut, * pErr, * pFile;
char * pFileName;
int fSelected = 0;
int fVerilog = 0;
int fVerbose = 0;
int c;
......@@ -415,16 +416,19 @@ int Mio_CommandWriteGenlib( Abc_Frame_t * pAbc, int argc, char **argv )
pErr = Abc_FrameReadErr(pAbc);
Extra_UtilGetoptReset();
while ( (c = Extra_UtilGetopt(argc, argv, "vah")) != EOF )
while ( (c = Extra_UtilGetopt(argc, argv, "agvh")) != EOF )
{
switch (c)
{
case 'v':
fVerbose ^= 1;
break;
case 'a':
fSelected ^= 1;
break;
case 'g':
fVerilog ^= 1;
break;
case 'v':
fVerbose ^= 1;
break;
case 'h':
goto usage;
break;
......@@ -450,16 +454,20 @@ int Mio_CommandWriteGenlib( Abc_Frame_t * pAbc, int argc, char **argv )
printf( "Error! Cannot open file \"%s\" for writing the library.\n", pFileName );
return 1;
}
if ( fVerilog )
Mio_WriteLibraryVerilog( pFile, (Mio_Library_t *)Abc_FrameReadLibGen(), 0, 0, fSelected );
else
Mio_WriteLibrary( pFile, (Mio_Library_t *)Abc_FrameReadLibGen(), 0, 0, fSelected );
fclose( pFile );
printf( "The current genlib library is written into file \"%s\".\n", pFileName );
return 0;
usage:
fprintf( pErr, "\nusage: write_genlib [-vah] <file>\n");
fprintf( pErr, "\nusage: write_genlib [-agvh] <file>\n");
fprintf( pErr, "\t writes the current genlib library into a file\n" );
fprintf( pErr, "\t-v : toggles enabling of verbose output [default = %s]\n", fVerbose? "yes" : "no" );
fprintf( pErr, "\t-a : toggles writing min-area gates [default = %s]\n", fSelected? "yes" : "no" );
fprintf( pErr, "\t-g : toggles writing the library in Verilog [default = %s]\n", fVerilog? "yes" : "no" );
fprintf( pErr, "\t-v : toggles enabling of verbose output [default = %s]\n", fVerbose? "yes" : "no" );
fprintf( pErr, "\t-h : print the command usage\n");
fprintf( pErr, "\t<file> : optional file name to write the library\n");
return 1;
......
......@@ -194,6 +194,7 @@ extern void Mio_GateDelete( Mio_Gate_t * pGate );
extern void Mio_PinDelete( Mio_Pin_t * pPin );
extern Mio_Pin_t * Mio_PinDup( Mio_Pin_t * pPin );
extern void Mio_WriteLibrary( FILE * pFile, Mio_Library_t * pLib, int fPrintSops, int fShort, int fSelected );
extern void Mio_WriteLibraryVerilog( FILE * pFile, Mio_Library_t * pLib, int fPrintSops, int fShort, int fSelected );
extern Mio_Gate_t ** Mio_CollectRoots( Mio_Library_t * pLib, int nInputs, float tDelay, int fSkipInv, int * pnGates, int fVerbose );
extern Mio_Cell_t * Mio_CollectRootsNew( Mio_Library_t * pLib, int nInputs, int * pnGates, int fVerbose );
extern Mio_Cell_t * Mio_CollectRootsNewDefault( int nInputs, int * pnGates, int fVerbose );
......
......@@ -288,6 +288,70 @@ void Mio_WriteLibrary( FILE * pFile, Mio_Library_t * pLib, int fPrintSops, int f
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Mio_WriteGateVerilog( FILE * pFile, Mio_Gate_t * pGate, Vec_Ptr_t * vNames )
{
char * pName; int i;
fprintf( pFile, "module %s ( ", pGate->pName );
fprintf( pFile, "%s", pGate->pOutName );
Vec_PtrForEachEntry( char *, vNames, pName, i )
fprintf( pFile, ", %s", pName );
fprintf( pFile, " );\n" );
fprintf( pFile, " output %s;\n", pGate->pOutName );
if ( Vec_PtrSize(vNames) > 0 )
{
fprintf( pFile, " input %s", (char *)Vec_PtrEntry(vNames, 0) );
Vec_PtrForEachEntryStart( char *, vNames, pName, i, 1 )
fprintf( pFile, ", %s", pName );
fprintf( pFile, ";\n" );
}
fprintf( pFile, " assign %s = ", pGate->pOutName );
Exp_PrintVerilog( pFile, Vec_PtrSize(vNames), pGate->vExpr, vNames );
fprintf( pFile, ";\n" );
fprintf( pFile, "endmodule\n\n" );
}
void Mio_WriteLibraryVerilog( FILE * pFile, Mio_Library_t * pLib, int fPrintSops, int fShort, int fSelected )
{
Mio_Gate_t * pGate;
Mio_Pin_t * pPin;
Vec_Ptr_t * vGates = Vec_PtrAlloc( 1000 );
Vec_Ptr_t * vNames = Vec_PtrAlloc( 100 );
int i, nCells;
int fAllPins = fShort || Mio_CheckGates( pLib );
if ( fSelected )
{
Mio_Cell2_t * pCells = Mio_CollectRootsNewDefault2( 6, &nCells, 0 );
for ( i = 0; i < nCells; i++ )
Vec_PtrPush( vGates, pCells[i].pMioGate );
ABC_FREE( pCells );
}
else
{
for ( i = 0; i < pLib->nGates; i++ )
Vec_PtrPush( vGates, pLib->ppGates0[i] );
}
fprintf( pFile, "// Verilog for genlib library \"%s\" with %d gates written by ABC on %s\n\n", pLib->pName, Vec_PtrSize(vGates), Extra_TimeStamp() );
Vec_PtrForEachEntry( Mio_Gate_t *, vGates, pGate, i )
{
Vec_PtrClear( vNames );
Mio_GateForEachPin( pGate, pPin )
Vec_PtrPush( vNames, pPin->pName );
Mio_WriteGateVerilog( pFile, pGate, vNames );
}
Vec_PtrFree( vNames );
Vec_PtrFree( vGates );
}
/**Function*************************************************************
Synopsis [Compares the max delay of two gates.]
Description []
......
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