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Commit 37f19d8d by Alan Mishchenko
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Version abc51205

parent a6086f08
Showing with 238 additions and 499 deletions
abc.opt
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examples/s38417.blif 0 → 100644
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examples/s444.blif
.model iscas\s444.bench
.model s444
.inputs G0 G1 G2
.outputs G118 G167 G107 G119 G168 G108
......
examples/s6669.blif 0 → 100644
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regtest.script
r examples/apex4.pla
resyn
sharem
fpga
cec
ps
clp
share
resyn
map
cec
ps
r examples/C2670.blif
resyn
fpga
cec
ps
u
map
cec
ps
r examples/frg2.blif
dsd
muxes
cec
clp
share
resyn
map
cec
ps
r examples/pj1.blif
resyn
fpga
cec
ps
u
map
cec
ps
r examples/s38584.bench
resyn
fpga
cec
ps
u
map
cec
ps
r examples/ac.v
resyn
fpga
cec
ps
u
map
cec
ps
r examples/s444.blif
b
esd -v
dsd
cec
ps
r examples/i10.blif
fpga
cec
ps
u
map
cec
ps
r examples/i10.blif
b
fraig_store
resyn
fraig_store
resyn2
fraig_store
fraig_restore
fpga
cec
ps
u
map
cec
ps
r examples/apex4.pla; resyn; sharem; fpga; cec; ps; clp; share; resyn; map; cec; ps
r examples/C2670.blif; resyn; fpga; cec; ps; u; map; cec; ps
r examples/frg2.blif; dsd; muxes; cec; clp; share; resyn; map; cec; ps
r examples/pj1.blif; resyn; fpga; cec; ps; u; map; cec; ps
r examples/s38584.bench; resyn; fpga; cec; ps; u; map; cec; ps
r examples/ac.v; resyn; fpga; cec; ps; u; map; cec; ps
r examples/s444.blif; b; esd -v; dsd; cec; ps
r examples/i10.blif; fpga; cec; ps; u; map; cec; ps
r examples/i10.blif; choice; fpga; cec; ps; u; map; cec; ps
r examples/s6669.blif; fpga; ps; sec; u; sfpga; ps; sec; u; fpga; ret; ps; sec
r examples/s5378.blif; map -s; ps; sec; u; smap; ps; sec; u; map; ret; ps; sec
time
src/base/abc/abcNtk.c
......@@ -236,7 +236,7 @@ Abc_Ntk_t * Abc_NtkStartRead( char * pName )
pNtkNew = Abc_NtkAlloc( ABC_NTK_NETLIST, ABC_FUNC_SOP );
// set the specs
pNtkNew->pName = util_strsav( Extra_FileNameGeneric(pName) );
pNtkNew->pSpec = util_strsav( Extra_FileNameGeneric(pName) );
pNtkNew->pSpec = util_strsav( pName );
return pNtkNew;
}
......
src/base/abci/abc.c
......@@ -42,6 +42,7 @@ static int Abc_CommandPrintSupport ( Abc_Frame_t * pAbc, int argc, char ** argv
static int Abc_CommandPrintSymms ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandPrintKMap ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandPrintGates ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandPrintSharing ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandShowBdd ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandShowCut ( Abc_Frame_t * pAbc, int argc, char ** argv );
......@@ -137,6 +138,7 @@ void Abc_Init( Abc_Frame_t * pAbc )
Cmd_CommandAdd( pAbc, "Printing", "print_symm", Abc_CommandPrintSymms, 0 );
Cmd_CommandAdd( pAbc, "Printing", "print_kmap", Abc_CommandPrintKMap, 0 );
Cmd_CommandAdd( pAbc, "Printing", "print_gates", Abc_CommandPrintGates, 0 );
Cmd_CommandAdd( pAbc, "Printing", "print_sharing", Abc_CommandPrintSharing, 0 );
Cmd_CommandAdd( pAbc, "Printing", "show_bdd", Abc_CommandShowBdd, 0 );
Cmd_CommandAdd( pAbc, "Printing", "show_cut", Abc_CommandShowCut, 0 );
......@@ -1019,6 +1021,69 @@ usage:
SeeAlso []
***********************************************************************/
int Abc_CommandPrintSharing( Abc_Frame_t * pAbc, int argc, char ** argv )
{
FILE * pOut, * pErr;
Abc_Ntk_t * pNtk;
int c;
int fUseLibrary;
extern void Abc_NtkPrintSharing( Abc_Ntk_t * pNtk );
pNtk = Abc_FrameReadNet(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
// set defaults
fUseLibrary = 1;
util_getopt_reset();
while ( ( c = util_getopt( argc, argv, "lh" ) ) != EOF )
{
switch ( c )
{
case 'l':
fUseLibrary ^= 1;
break;
case 'h':
goto usage;
default:
goto usage;
}
}
if ( pNtk == NULL )
{
fprintf( pErr, "Empty network.\n" );
return 1;
}
if ( Abc_NtkIsSeq(pNtk) )
{
fprintf( pErr, "Printing logic sharing does not work for sequential AIGs.\n" );
return 1;
}
Abc_NtkPrintSharing( pNtk );
return 0;
usage:
fprintf( pErr, "usage: print_sharing [-h]\n" );
fprintf( pErr, "\t prints the number of shared nodes in the TFO cones of the COs\n" );
// fprintf( pErr, "\t-l : used library gate names (if mapped) [default = %s]\n", fUseLibrary? "yes": "no" );
fprintf( pErr, "\t-h : print the command usage\n");
return 1;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_CommandShowBdd( Abc_Frame_t * pAbc, int argc, char ** argv )
{
FILE * pOut, * pErr;
......@@ -4245,12 +4310,12 @@ usage:
sprintf( Buffer, "not used" );
else
sprintf( Buffer, "%.3f", DelayTarget );
fprintf( pErr, "usage: map [-D num] [-aspvh]\n" );
fprintf( pErr, "usage: map [-D float] [-aspvh]\n" );
fprintf( pErr, "\t performs standard cell mapping of the current network\n" );
fprintf( pErr, "\t-D num : sets the global required times [default = %s]\n", Buffer );
fprintf( pErr, "\t-D float : sets the global required times [default = %s]\n", Buffer );
fprintf( pErr, "\t-a : toggles area recovery [default = %s]\n", fRecovery? "yes": "no" );
fprintf( pErr, "\t-s : toggles sweep after mapping [default = %s]\n", fSweep? "yes": "no" );
fprintf( pErr, "\t-p : optimizes power by minimizing switching activity [default = %s]\n", fSwitching? "yes": "no" );
fprintf( pErr, "\t-p : optimizes power by minimizing switching [default = %s]\n", fSwitching? "yes": "no" );
fprintf( pErr, "\t-v : toggles verbose output [default = %s]\n", fVerbose? "yes": "no" );
fprintf( pErr, "\t-h : print the command usage\n");
return 1;
......@@ -4461,13 +4526,16 @@ usage:
***********************************************************************/
int Abc_CommandFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
{
char Buffer[100];
FILE * pOut, * pErr;
Abc_Ntk_t * pNtk, * pNtkRes;
int c;
int fRecovery;
int fSwitching;
int fVerbose;
extern Abc_Ntk_t * Abc_NtkFpga( Abc_Ntk_t * pNtk, int fRecovery, int fSwitching, int fVerbose );
float DelayTarget;
extern Abc_Ntk_t * Abc_NtkFpga( Abc_Ntk_t * pNtk, float DelayTarget, int fRecovery, int fSwitching, int fVerbose );
pNtk = Abc_FrameReadNet(pAbc);
pOut = Abc_FrameReadOut(pAbc);
......@@ -4477,8 +4545,9 @@ int Abc_CommandFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
fRecovery = 1;
fSwitching = 0;
fVerbose = 0;
DelayTarget =-1;
util_getopt_reset();
while ( ( c = util_getopt( argc, argv, "apvh" ) ) != EOF )
while ( ( c = util_getopt( argc, argv, "apvhD" ) ) != EOF )
{
switch ( c )
{
......@@ -4493,6 +4562,17 @@ int Abc_CommandFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
break;
case 'h':
goto usage;
case 'D':
if ( util_optind >= argc )
{
fprintf( pErr, "Command line switch \"-D\" should be followed by a floating point number.\n" );
goto usage;
}
DelayTarget = (float)atof(argv[util_optind]);
util_optind++;
if ( DelayTarget <= 0.0 )
goto usage;
break;
default:
goto usage;
}
......@@ -4528,7 +4608,7 @@ int Abc_CommandFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
}
fprintf( pOut, "The network was strashed and balanced before FPGA mapping.\n" );
// get the new network
pNtkRes = Abc_NtkFpga( pNtk, fRecovery, fSwitching, fVerbose );
pNtkRes = Abc_NtkFpga( pNtk, DelayTarget, fRecovery, fSwitching, fVerbose );
if ( pNtkRes == NULL )
{
Abc_NtkDelete( pNtk );
......@@ -4540,7 +4620,7 @@ int Abc_CommandFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
else
{
// get the new network
pNtkRes = Abc_NtkFpga( pNtk, fRecovery, fSwitching, fVerbose );
pNtkRes = Abc_NtkFpga( pNtk, DelayTarget, fRecovery, fSwitching, fVerbose );
if ( pNtkRes == NULL )
{
fprintf( pErr, "FPGA mapping has failed.\n" );
......@@ -4552,10 +4632,15 @@ int Abc_CommandFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
return 0;
usage:
fprintf( pErr, "usage: fpga [-apvh]\n" );
if ( DelayTarget == -1 )
sprintf( Buffer, "not used" );
else
sprintf( Buffer, "%.2f", DelayTarget );
fprintf( pErr, "usage: fpga [-D float] [-apvh]\n" );
fprintf( pErr, "\t performs FPGA mapping of the current network\n" );
fprintf( pErr, "\t-a : toggles area recovery [default = %s]\n", fRecovery? "yes": "no" );
fprintf( pErr, "\t-p : optimizes power by minimizing switching activity [default = %s]\n", fSwitching? "yes": "no" );
fprintf( pErr, "\t-D : sets the required time for the mapping [default = %s]\n", Buffer );
fprintf( pErr, "\t-v : toggles verbose output [default = %s]\n", fVerbose? "yes": "no" );
fprintf( pErr, "\t-h : prints the command usage\n");
return 1;
......
src/base/abci/abcFpga.c
......@@ -44,7 +44,7 @@ static Abc_Obj_t * Abc_NodeFromFpga_rec( Abc_Ntk_t * pNtkNew, Fpga_Node_t * pNo
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkFpga( Abc_Ntk_t * pNtk, int fRecovery, int fSwitching, int fVerbose )
Abc_Ntk_t * Abc_NtkFpga( Abc_Ntk_t * pNtk, float DelayTarget, int fRecovery, int fSwitching, int fVerbose )
{
int fShowSwitching = 1;
Abc_Ntk_t * pNtkNew;
......@@ -73,6 +73,7 @@ Abc_Ntk_t * Abc_NtkFpga( Abc_Ntk_t * pNtk, int fRecovery, int fSwitching, int fV
if ( pMan == NULL )
return NULL;
Fpga_ManSetSwitching( pMan, fSwitching );
Fpga_ManSetDelayTarget( pMan, DelayTarget );
if ( !Fpga_Mapping( pMan ) )
{
Fpga_ManFree( pMan );
......
src/base/abci/abcPrint.c
......@@ -667,6 +667,55 @@ void Abc_NtkPrintGates( Abc_Ntk_t * pNtk, int fUseLibrary )
Abc_NtkSopToBdd(pNtk);
}
/**Function*************************************************************
Synopsis [Prints statistics about gates used in the network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkPrintSharing( Abc_Ntk_t * pNtk )
{
Vec_Ptr_t * vNodes1, * vNodes2;
Abc_Obj_t * pObj1, * pObj2, * pNode1, * pNode2;
int i, k, m, n, Counter;
// print the template
printf( "Statistics about sharing of logic nodes among the CO pairs.\n" );
printf( "(CO1,CO2)=NumShared : " );
// go though the CO pairs
Abc_NtkForEachCo( pNtk, pObj1, i )
{
vNodes1 = Abc_NtkDfsNodes( pNtk, &pObj1, 1 );
// mark the nodes
Vec_PtrForEachEntry( vNodes1, pNode1, m )
pNode1->fMarkA = 1;
// go through the second COs
Abc_NtkForEachCo( pNtk, pObj2, k )
{
if ( i >= k )
continue;
vNodes2 = Abc_NtkDfsNodes( pNtk, &pObj2, 1 );
// count the number of marked
Counter = 0;
Vec_PtrForEachEntry( vNodes2, pNode2, n )
Counter += pNode2->fMarkA;
// print
printf( "(%d,%d)=%d ", i, k, Counter );
Vec_PtrFree( vNodes2 );
}
// unmark the nodes
Vec_PtrForEachEntry( vNodes1, pNode1, m )
pNode1->fMarkA = 0;
Vec_PtrFree( vNodes1 );
}
printf( "\n" );
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
......
src/base/abci/abcStrash.c
......@@ -68,8 +68,8 @@ Abc_Ntk_t * Abc_NtkStrash( Abc_Ntk_t * pNtk, bool fAllNodes, bool fCleanup )
Abc_NtkStrashPerform( pNtk, pNtkAig, fAllNodes );
Abc_NtkFinalize( pNtk, pNtkAig );
// print warning about self-feed latches
if ( Abc_NtkCountSelfFeedLatches(pNtkAig) )
printf( "Warning: The network has %d self-feeding latches.\n", Abc_NtkCountSelfFeedLatches(pNtkAig) );
// if ( Abc_NtkCountSelfFeedLatches(pNtkAig) )
// printf( "Warning: The network has %d self-feeding latches.\n", Abc_NtkCountSelfFeedLatches(pNtkAig) );
if ( fCleanup && (nNodes = Abc_AigCleanup(pNtkAig->pManFunc)) )
printf( "Warning: AIG cleanup removed %d nodes (this is not a bug).\n", nNodes );
// duplicate EXDC
......
src/base/seq/seqMapCore.c
......@@ -82,6 +82,7 @@ Abc_Ntk_t * Seq_MapRetime( Abc_Ntk_t * pNtk, int nMaxIters, int fVerbose )
printf( "The mininum clock period computed is %5.2f.\n", p->FiBestFloat );
return NULL;
}
printf( "The mininum clock period computed is %5.2f.\n", p->FiBestFloat );
printf( "The resulting network is derived as BDD logic network (this is temporary).\n" );
// duplicate the nodes contained in multiple cuts
......
src/map/fpga/fpga.c
......@@ -57,8 +57,8 @@ void Fpga_Init( Abc_Frame_t * pAbc )
{
// set the default library
//Fpga_LutLib_t s_LutLib = { "lutlib", 6, {0,1,2,4,8,16,32}, {0,1,2,3,4,5,6} };
Fpga_LutLib_t s_LutLib = { "lutlib", 5, {0,1,1,1,1,1}, {0,1,1,1,1,1} };
//Fpga_LutLib_t s_LutLib = { "lutlib", 4, {0,1,1,1,1}, {0,1,1,1,1} };
// Fpga_LutLib_t s_LutLib = { "lutlib", 5, {0,1,1,1,1,1}, {0,1,1,1,1,1} };
Fpga_LutLib_t s_LutLib = { "lutlib", 4, {0,1,1,1,1}, {0,1,1,1,1} };
//Fpga_LutLib_t s_LutLib = { "lutlib", 3, {0,1,1,1}, {0,1,1,1} };
Abc_FrameSetLibLut( Fpga_LutLibDup(&s_LutLib) );
......
src/map/fpga/fpga.h
......@@ -92,6 +92,7 @@ extern void Fpga_ManSetChoiceNodeNum( Fpga_Man_t * p, int nChoiceNode
extern void Fpga_ManSetChoiceNum( Fpga_Man_t * p, int nChoices );
extern void Fpga_ManSetVerbose( Fpga_Man_t * p, int fVerbose );
extern void Fpga_ManSetSwitching( Fpga_Man_t * p, int fSwitching );
extern void Fpga_ManSetDelayTarget( Fpga_Man_t * p, float DelayTarget );
extern void Fpga_ManSetLatchNum( Fpga_Man_t * p, int nLatches );
extern void Fpga_ManSetName( Fpga_Man_t * p, char * pFileName );
......
src/map/fpga/fpgaCore.c
......@@ -118,7 +118,7 @@ PRT( "Time", p->timeMatch );
{
clk = clock();
// compute the required times and the fanouts
Fpga_TimeComputeRequiredGlobal( p );
Fpga_TimeComputeRequiredGlobal( p, 1 );
// remap topologically
Fpga_MappingMatches( p, 0 );
// get the resulting area
......@@ -143,7 +143,7 @@ PRT( "Time", clock() - clk );
{
clk = clock();
// compute the required times and the fanouts
Fpga_TimeComputeRequiredGlobal( p );
Fpga_TimeComputeRequiredGlobal( p, 0 );
// remap topologically
if ( p->fSwitching )
Fpga_MappingMatchesSwitch( p );
......
src/map/fpga/fpgaCreate.c
......@@ -66,6 +66,7 @@ void Fpga_ManSetChoiceNodeNum( Fpga_Man_t * p, int nChoiceNodes ) { p
void Fpga_ManSetChoiceNum( Fpga_Man_t * p, int nChoices ) { p->nChoices = nChoices; }
void Fpga_ManSetVerbose( Fpga_Man_t * p, int fVerbose ) { p->fVerbose = fVerbose; }
void Fpga_ManSetSwitching( Fpga_Man_t * p, int fSwitching ) { p->fSwitching = fSwitching; }
void Fpga_ManSetDelayTarget( Fpga_Man_t * p, float DelayTarget ) { p->DelayTarget = DelayTarget; }
void Fpga_ManSetLatchNum( Fpga_Man_t * p, int nLatches ) { p->nLatches = nLatches; }
void Fpga_ManSetName( Fpga_Man_t * p, char * pFileName ) { p->pFileName = pFileName; }
......
src/map/fpga/fpgaInt.h
......@@ -123,7 +123,8 @@ struct Fpga_ManStruct_t_
int fAreaRecovery; // the flag to use area flow as the first parameter
int fVerbose; // the verbosiness flag
int fSwitching; // minimize the switching activity (instead of area)
int nTravIds;
int nTravIds; // the counter of traversal IDs
float DelayTarget; // the target required times
// support of choice nodes
int nChoiceNodes; // the number of choice nodes
......@@ -331,7 +332,7 @@ extern float Fpga_MappingGetSwitching( Fpga_Man_t * pMan, Fpga_NodeV
extern float Fpga_TimeCutComputeArrival( Fpga_Man_t * pMan, Fpga_Cut_t * pCut );
extern float Fpga_TimeCutComputeArrival_rec( Fpga_Man_t * pMan, Fpga_Cut_t * pCut );
extern float Fpga_TimeComputeArrivalMax( Fpga_Man_t * p );
extern void Fpga_TimeComputeRequiredGlobal( Fpga_Man_t * p );
extern void Fpga_TimeComputeRequiredGlobal( Fpga_Man_t * p, int fFirstTime );
extern void Fpga_TimeComputeRequired( Fpga_Man_t * p, float fRequired );
extern void Fpga_TimePropagateRequired( Fpga_Man_t * p, Fpga_NodeVec_t * vNodes );
extern void Fpga_TimePropagateArrival( Fpga_Man_t * p );
......
src/map/fpga/fpgaMatch.c
......@@ -501,7 +501,7 @@ void Fpga_Experiment( Fpga_Man_t * p )
AreaBefore = pNode->pCutBest->aFlow;
pNode->pCutBest->aFlow = FPGA_FLOAT_LARGE;
Fpga_TimeComputeRequiredGlobal( p );
Fpga_TimeComputeRequiredGlobal( p, 0 );
vNodesTfo = Fpga_CollectNodeTfo( p, pNode );
if ( Fpga_MappingMatchesAreaArray( p, vNodesTfo ) == 0 )
......
src/map/fpga/fpgaTime.c
......@@ -109,9 +109,24 @@ float Fpga_TimeComputeArrivalMax( Fpga_Man_t * p )
SeeAlso []
***********************************************************************/
void Fpga_TimeComputeRequiredGlobal( Fpga_Man_t * p )
void Fpga_TimeComputeRequiredGlobal( Fpga_Man_t * p, int fFirstTime )
{
p->fRequiredGlo = Fpga_TimeComputeArrivalMax( p );
// update the required times according to the target
if ( p->DelayTarget != -1 )
{
if ( p->fRequiredGlo > p->DelayTarget + p->fEpsilon )
{
if ( fFirstTime )
printf( "Cannot meet the target required times (%4.2f). Mapping continues anyway.\n", p->DelayTarget );
}
else if ( p->fRequiredGlo < p->DelayTarget - p->fEpsilon )
{
if ( fFirstTime )
printf( "Relaxing the required times from (%4.2f) to the target (%4.2f).\n", p->fRequiredGlo, p->DelayTarget );
p->fRequiredGlo = p->DelayTarget;
}
}
Fpga_TimeComputeRequired( p, p->fRequiredGlo );
}
......
src/map/fpga/fpgaUtils.c
......@@ -30,6 +30,7 @@ static int Fpga_MappingCompareOutputDelay( Fpga_Node_t ** ppNode1, Fpga_Node_t
static void Fpga_MappingFindLatest( Fpga_Man_t * p, int * pNodes, int nNodesMax );
static void Fpga_DfsLim_rec( Fpga_Node_t * pNode, int Level, Fpga_NodeVec_t * vNodes );
static int Fpga_CollectNodeTfo_rec( Fpga_Node_t * pNode, Fpga_Node_t * pPivot, Fpga_NodeVec_t * vVisited, Fpga_NodeVec_t * vTfo );
static Fpga_NodeVec_t * Fpga_MappingOrderCosByLevel( Fpga_Man_t * pMan );
static Fpga_Man_t * s_pMan = NULL;
////////////////////////////////////////////////////////////////////////
......@@ -50,9 +51,11 @@ static Fpga_Man_t * s_pMan = NULL;
***********************************************************************/
Fpga_NodeVec_t * Fpga_MappingDfs( Fpga_Man_t * pMan, int fCollectEquiv )
{
Fpga_NodeVec_t * vNodes;
Fpga_NodeVec_t * vNodes, * vNodesCo;
Fpga_Node_t * pNode;
int i;
// collect the CO nodes by level
vNodesCo = Fpga_MappingOrderCosByLevel( pMan );
// start the array
vNodes = Fpga_NodeVecAlloc( 100 );
// collect the PIs
......@@ -63,12 +66,17 @@ Fpga_NodeVec_t * Fpga_MappingDfs( Fpga_Man_t * pMan, int fCollectEquiv )
pNode->fMark0 = 1;
}
// perform the traversal
for ( i = 0; i < pMan->nOutputs; i++ )
Fpga_MappingDfs_rec( Fpga_Regular(pMan->pOutputs[i]), vNodes, fCollectEquiv );
// for ( i = 0; i < pMan->nOutputs; i++ )
// Fpga_MappingDfs_rec( Fpga_Regular(pMan->pOutputs[i]), vNodes, fCollectEquiv );
for ( i = 0; i < vNodesCo->nSize; i++ )
for ( pNode = vNodesCo->pArray[i]; pNode; pNode = (Fpga_Node_t *)pNode->pData0 )
Fpga_MappingDfs_rec( pNode, vNodes, fCollectEquiv );
// clean the node marks
for ( i = 0; i < vNodes->nSize; i++ )
vNodes->pArray[i]->fMark0 = 0;
// for ( i = 0; i < pMan->nOutputs; i++ )
// Fpga_MappingUnmark_rec( Fpga_Regular(pMan->pOutputs[i]) );
Fpga_NodeVecFree( vNodesCo );
return vNodes;
}
......@@ -930,6 +938,47 @@ void Fpga_ManReportChoices( Fpga_Man_t * pMan )
*/
}
/**Function*************************************************************
Synopsis [Returns the array of CO nodes sorted by level.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Fpga_NodeVec_t * Fpga_MappingOrderCosByLevel( Fpga_Man_t * pMan )
{
Fpga_Node_t * pNode;
Fpga_NodeVec_t * vNodes;
int i, nLevels;
// get the largest node
nLevels = Fpga_MappingMaxLevel( pMan );
// allocate the array of nodes
vNodes = Fpga_NodeVecAlloc( nLevels + 1 );
for ( i = 0; i <= nLevels; i++ )
Fpga_NodeVecPush( vNodes, NULL );
// clean the marks
for ( i = 0; i < pMan->nOutputs; i++ )
Fpga_Regular(pMan->pOutputs[i])->fMark0 = 0;
// put the nodes into the structure
for ( i = 0; i < pMan->nOutputs; i++ )
{
pNode = Fpga_Regular(pMan->pOutputs[i]);
if ( pNode->fMark0 )
continue;
pNode->fMark0 = 1;
pNode->pData0 = (char *)Fpga_NodeVecReadEntry( vNodes, pNode->Level );
Fpga_NodeVecWriteEntry( vNodes, pNode->Level, pNode );
}
for ( i = 0; i < pMan->nOutputs; i++ )
Fpga_Regular(pMan->pOutputs[i])->fMark0 = 0;
return vNodes;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
......
src/misc/vec/vecFan_.h deleted 100644 → 0
/**CFile****************************************************************
FileName [vecFan.h]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Resizable arrays.]
Synopsis [Resizable arrays of integers (fanins/fanouts) with memory management.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: vecFan.h,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#ifndef __VEC_FAN_H__
#define __VEC_FAN_H__
////////////////////////////////////////////////////////////////////////
/// INCLUDES ///
////////////////////////////////////////////////////////////////////////
#include <stdio.h>
#include "extra.h"
////////////////////////////////////////////////////////////////////////
/// PARAMETERS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// BASIC TYPES ///
////////////////////////////////////////////////////////////////////////
typedef struct Abc_Fan_t_ Abc_Fan_t;
struct Abc_Fan_t_ // 1 word
{
unsigned iFan : 31; // the ID of the object
unsigned fCompl : 1; // the complemented attribute
};
typedef struct Vec_Fan_t_ Vec_Fan_t;
struct Vec_Fan_t_
{
int nCap;
int nSize;
Abc_Fan_t * pArray;
};
////////////////////////////////////////////////////////////////////////
/// MACRO DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
#define Vec_FanForEachEntry( vVec, Entry, i ) \
for ( i = 0; (i < Vec_FanSize(vVec)) && (((Entry) = Vec_FanEntry(vVec, i)), 1); i++ )
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Converts an integer into the simple fanin structure.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline Abc_Fan_t Vec_Int2Fan( int iFan )
{
return *((Abc_Fan_t *)&iFan);
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline Abc_Fan_t * Vec_FanArray( Vec_Fan_t * p )
{
return p->pArray;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline int Vec_FanSize( Vec_Fan_t * p )
{
return p->nSize;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline Abc_Fan_t Vec_FanEntry( Vec_Fan_t * p, int i )
{
assert( i >= 0 && i < p->nSize );
return p->pArray[i];
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline void Vec_FanWriteEntry( Vec_Fan_t * p, int i, Abc_Fan_t Entry )
{
assert( i >= 0 && i < p->nSize );
p->pArray[i] = Entry;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline Abc_Fan_t Vec_FanEntryLast( Vec_Fan_t * p )
{
return p->pArray[p->nSize-1];
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline void Vec_FanShrink( Vec_Fan_t * p, int nSizeNew )
{
assert( p->nSize >= nSizeNew );
p->nSize = nSizeNew;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline void Vec_FanClear( Vec_Fan_t * p )
{
p->nSize = 0;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline void Vec_FanPush( Extra_MmStep_t * pMemMan, Vec_Fan_t * p, Abc_Fan_t Entry )
{
if ( p->nSize == p->nCap )
{
Abc_Fan_t * pArray;
int i;
if ( p->nSize == 0 )
p->nCap = 1;
pArray = (Abc_Fan_t *)Extra_MmStepEntryFetch( pMemMan, p->nCap * 8 );
// pArray = ALLOC( int, p->nCap * 2 );
if ( p->pArray )
{
for ( i = 0; i < p->nSize; i++ )
pArray[i] = p->pArray[i];
Extra_MmStepEntryRecycle( pMemMan, (char *)p->pArray, p->nCap * 4 );
// free( p->pArray );
}
p->nCap *= 2;
p->pArray = pArray;
}
p->pArray[p->nSize++] = Entry;
}
/**Function*************************************************************
Synopsis [Returns the last entry and removes it from the list.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline Abc_Fan_t Vec_FanPop( Vec_Fan_t * p )
{
assert( p->nSize > 0 );
return p->pArray[--p->nSize];
}
/**Function*************************************************************
Synopsis [Find entry.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline int Vec_FanFindEntry( Vec_Fan_t * p, unsigned iFan )
{
int i;
for ( i = 0; i < p->nSize; i++ )
if ( p->pArray[i].iFan == iFan )
return i;
return -1;
}
/**Function*************************************************************
Synopsis [Deletes entry.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline int Vec_FanDeleteEntry( Vec_Fan_t * p, unsigned iFan )
{
/*
int i, k, fFound = 0;
for ( i = k = 0; i < p->nSize; i++ )
{
if ( p->pArray[i].iFan == iFan )
fFound = 1;
else
p->pArray[k++] = p->pArray[i];
}
p->nSize = k;
return fFound;
*/
int i;
for ( i = 0; i < p->nSize; i++ )
if ( p->pArray[i].iFan == iFan )
break;
if ( i == p->nSize )
return 0;
for ( i++; i < p->nSize; i++ )
p->pArray[i-1] = p->pArray[i];
p->nSize--;
return 1;
}
/**Function*************************************************************
Synopsis [Comparison procedure for two integers.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline int Vec_FanSortCompare1( int * pp1, int * pp2 )
{
// for some reason commenting out lines (as shown) led to crashing of the release version
if ( *pp1 < *pp2 )
return -1;
if ( *pp1 > *pp2 ) //
return 1;
return 0; //
}
/**Function*************************************************************
Synopsis [Comparison procedure for two integers.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline int Vec_FanSortCompare2( int * pp1, int * pp2 )
{
// for some reason commenting out lines (as shown) led to crashing of the release version
if ( *pp1 > *pp2 )
return -1;
if ( *pp1 < *pp2 ) //
return 1;
return 0; //
}
/**Function*************************************************************
Synopsis [Sorting the entries by their integer value.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline void Vec_FanSort( Vec_Fan_t * p, int fReverse )
{
if ( fReverse )
qsort( (void *)p->pArray, p->nSize, sizeof(int),
(int (*)(const void *, const void *)) Vec_FanSortCompare2 );
else
qsort( (void *)p->pArray, p->nSize, sizeof(int),
(int (*)(const void *, const void *)) Vec_FanSortCompare1 );
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
#endif
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