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lvzhengyang
abc
Commits
2325cd77
Commit
2325cd77
authored
Oct 31, 2020
by
Alan Mishchenko
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Adding an option to write Verilog with LUT instances (compiler warnings).
parent
f9af41ba
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2 changed files
with
3 additions
and
3 deletions
+3
-3
src/base/io/io.c
+1
-1
src/base/io/ioWriteVerilog.c
+2
-2
No files found.
src/base/io/io.c
View file @
2325cd77
...
...
@@ -3039,7 +3039,7 @@ int IoCommandWriteVerilog( Abc_Frame_t * pAbc, int argc, char **argv )
usage
:
fprintf
(
pAbc
->
Err
,
"usage: write_verilog [-K num] [-ah] <file>
\n
"
);
fprintf
(
pAbc
->
Err
,
"
\t
writes the current network in Verilog format
\n
"
);
fprintf
(
pAbc
->
Err
,
"
\t
-K num : write the network using instances of K-LUTs (2 <= K <=
%d) [default = not used]
\n
"
,
6
,
nLutSize
);
fprintf
(
pAbc
->
Err
,
"
\t
-K num : write the network using instances of K-LUTs (2 <= K <=
6) [default = not used]
\n
"
);
fprintf
(
pAbc
->
Err
,
"
\t
-a : toggle writing expressions with only ANDs (without XORs and MUXes) [default = %s]
\n
"
,
fOnlyAnds
?
"yes"
:
"no"
);
fprintf
(
pAbc
->
Err
,
"
\t
-h : print the help massage
\n
"
);
fprintf
(
pAbc
->
Err
,
"
\t
file : the name of the file to write
\n
"
);
...
...
src/base/io/ioWriteVerilog.c
View file @
2325cd77
...
...
@@ -718,7 +718,7 @@ void Io_WriteVerilogObjectsLut( FILE * pFile, Abc_Ntk_t * pNtk, int nLutSize )
if
(
nLutSize
==
6
)
fprintf
(
pFile
,
"%08x%08x"
,
(
unsigned
)(
Truth
>>
32
),
(
unsigned
)
Truth
);
else
fprintf
(
pFile
,
"%0*x"
,
1
<<
(
nLutSize
-
2
),
Abc_InfoMask
(
1
<<
nLutSize
)
&
Truth
);
fprintf
(
pFile
,
"%0*x"
,
1
<<
(
nLutSize
-
2
),
Abc_InfoMask
(
1
<<
nLutSize
)
&
(
unsigned
)
Truth
);
fprintf
(
pFile
,
") lut_%0*d ( {"
,
nDigits
,
Counter
++
);
for
(
k
=
nLutSize
-
1
;
k
>=
Abc_ObjFaninNum
(
pObj
);
k
--
)
fprintf
(
pFile
,
"%*s, "
,
Length
,
"1
\'
b0"
);
...
...
@@ -804,7 +804,7 @@ void Io_WriteVerilogLut( Abc_Ntk_t * pNtk, char * pFileName, int nLutSize )
}
if
(
Counter
)
{
printf
(
"In total, %d internal logic nodes exceed
ed the fanout count limit
.
\n
"
,
Counter
);
printf
(
"In total, %d internal logic nodes exceed
the fanin count limit. Verilog is not written
.
\n
"
,
Counter
);
return
;
}
...
...
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