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lvzhengyang
abc
Commits
08d2b310
Commit
08d2b310
authored
Nov 21, 2005
by
Alan Mishchenko
Browse files
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Version abc51121
parent
69643dfe
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Showing
23 changed files
with
173 additions
and
87 deletions
+173
-87
abc.opt
+0
-0
abc.plg
+8
-8
src/base/abc/abc.h
+0
-14
src/base/abc/abcFanio.c
+3
-3
src/base/abc/abcNtk.c
+2
-2
src/base/abci/abc.c
+30
-22
src/base/abci/abcCut.c
+9
-2
src/base/io/ioWriteDot.c
+3
-3
src/base/io/ioWriteList.c
+2
-1
src/base/seq/seq.h
+1
-0
src/base/seq/seqCreate.c
+3
-2
src/base/seq/seqFpgaCore.c
+0
-0
src/base/seq/seqFpgaIter.c
+5
-4
src/base/seq/seqInt.h
+19
-6
src/base/seq/seqLatch.c
+4
-4
src/base/seq/seqMan.c
+3
-0
src/base/seq/seqRetCore.c
+0
-0
src/base/seq/seqRetIter.c
+22
-4
src/base/seq/seqShare.c
+8
-2
src/base/seq/seqUtil.c
+33
-8
src/map/fpga/fpgaCore.c
+0
-0
src/misc/vec/vecFan.h
+1
-2
src/misc/vec/vecInt.h
+17
-0
No files found.
abc.opt
View file @
08d2b310
No preview for this file type
abc.plg
View file @
08d2b310
...
...
@@ -6,13 +6,13 @@
--------------------Configuration: abc - Win32 Debug--------------------
</h3>
<h3>
Command Lines
</h3>
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP
F90
.tmp" with contents
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP
1416
.tmp" with contents
[
/nologo /MLd /W3 /Gm /GX /ZI /Od /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\seq" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\map\fpga" /I "src\map\pga" /I "src\map\mapper" /I "src\map\mapp" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D "HAVE_ASSERT_H" /FR"Debug/" /Fp"Debug/abc.pch" /YX /Fo"Debug/" /Fd"Debug/" /FD /GZ /c
"C:\_projects\abc\src\base\seq\seqFpga
Core
.c"
"C:\_projects\abc\src\base\seq\seqFpga
Iter
.c"
]
Creating command line "cl.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP
F90
.tmp"
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP
F91
.tmp" with contents
Creating command line "cl.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP
1416
.tmp"
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP
1417
.tmp" with contents
[
kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /incremental:yes /pdb:"Debug/abc.pdb" /debug /machine:I386 /out:"_TEST/abc.exe" /pdbtype:sept
.\Debug\abcAig.obj
...
...
@@ -329,12 +329,12 @@ kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32
.\Debug\mvcSort.obj
.\Debug\mvcUtils.obj
]
Creating command line "link.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP
F91
.tmp"
Creating command line "link.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP
1417
.tmp"
<h3>
Output Window
</h3>
Compiling...
seqFpga
Core
.c
seqFpga
Iter
.c
Linking...
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP
F92
.tmp" with contents
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP
1418
.tmp" with contents
[
/nologo /o"Debug/abc.bsc"
.\Debug\abcAig.sbr
...
...
@@ -650,7 +650,7 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSPF92.tmp" with conte
.\Debug\mvcPrint.sbr
.\Debug\mvcSort.sbr
.\Debug\mvcUtils.sbr]
Creating command line "bscmake.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP
F92
.tmp"
Creating command line "bscmake.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP
1418
.tmp"
Creating browse info file...
<h3>
Output Window
</h3>
...
...
src/base/abc/abc.h
View file @
08d2b310
...
...
@@ -312,11 +312,6 @@ static inline Abc_Obj_t * Abc_ObjFanout0Ntk( Abc_Obj_t * pObj ) { return (A
static
inline
bool
Abc_ObjFaninC
(
Abc_Obj_t
*
pObj
,
int
i
)
{
return
pObj
->
vFanins
.
pArray
[
i
].
fCompl
;
}
static
inline
bool
Abc_ObjFaninC0
(
Abc_Obj_t
*
pObj
)
{
return
pObj
->
vFanins
.
pArray
[
0
].
fCompl
;
}
static
inline
bool
Abc_ObjFaninC1
(
Abc_Obj_t
*
pObj
)
{
return
pObj
->
vFanins
.
pArray
[
1
].
fCompl
;
}
static
inline
int
Abc_ObjFaninL
(
Abc_Obj_t
*
pObj
,
int
i
)
{
return
pObj
->
vFanins
.
pArray
[
i
].
nLats
;
}
static
inline
int
Abc_ObjFaninL0
(
Abc_Obj_t
*
pObj
)
{
return
pObj
->
vFanins
.
pArray
[
0
].
nLats
;
}
static
inline
int
Abc_ObjFaninL1
(
Abc_Obj_t
*
pObj
)
{
return
pObj
->
vFanins
.
pArray
[
1
].
nLats
;
}
static
inline
int
Abc_ObjFaninLMin
(
Abc_Obj_t
*
pObj
)
{
assert
(
Abc_ObjIsNode
(
pObj
)
);
return
ABC_MIN
(
Abc_ObjFaninL0
(
pObj
),
Abc_ObjFaninL1
(
pObj
)
);
}
static
inline
int
Abc_ObjFaninLMax
(
Abc_Obj_t
*
pObj
)
{
assert
(
Abc_ObjIsNode
(
pObj
)
);
return
ABC_MAX
(
Abc_ObjFaninL0
(
pObj
),
Abc_ObjFaninL1
(
pObj
)
);
}
static
inline
Abc_Obj_t
*
Abc_ObjChild
(
Abc_Obj_t
*
pObj
,
int
i
)
{
return
Abc_ObjNotCond
(
Abc_ObjFanin
(
pObj
,
i
),
Abc_ObjFaninC
(
pObj
,
i
)
);}
static
inline
Abc_Obj_t
*
Abc_ObjChild0
(
Abc_Obj_t
*
pObj
)
{
return
Abc_ObjNotCond
(
Abc_ObjFanin0
(
pObj
),
Abc_ObjFaninC0
(
pObj
)
);
}
static
inline
Abc_Obj_t
*
Abc_ObjChild1
(
Abc_Obj_t
*
pObj
)
{
return
Abc_ObjNotCond
(
Abc_ObjFanin1
(
pObj
),
Abc_ObjFaninC1
(
pObj
)
);
}
...
...
@@ -325,15 +320,6 @@ static inline Abc_Obj_t * Abc_ObjChild0Copy( Abc_Obj_t * pObj ) { return Ab
static
inline
Abc_Obj_t
*
Abc_ObjChild1Copy
(
Abc_Obj_t
*
pObj
)
{
return
Abc_ObjNotCond
(
Abc_ObjFanin1
(
pObj
)
->
pCopy
,
Abc_ObjFaninC1
(
pObj
)
);
}
static
inline
void
Abc_ObjSetFaninC
(
Abc_Obj_t
*
pObj
,
int
i
){
pObj
->
vFanins
.
pArray
[
i
].
fCompl
=
1
;
}
static
inline
void
Abc_ObjXorFaninC
(
Abc_Obj_t
*
pObj
,
int
i
){
pObj
->
vFanins
.
pArray
[
i
].
fCompl
^=
1
;
}
static
inline
void
Abc_ObjSetFaninL
(
Abc_Obj_t
*
pObj
,
int
i
,
int
nLats
)
{
pObj
->
vFanins
.
pArray
[
i
].
nLats
=
nLats
;
}
static
inline
void
Abc_ObjSetFaninL0
(
Abc_Obj_t
*
pObj
,
int
nLats
)
{
pObj
->
vFanins
.
pArray
[
0
].
nLats
=
nLats
;
}
static
inline
void
Abc_ObjSetFaninL1
(
Abc_Obj_t
*
pObj
,
int
nLats
)
{
pObj
->
vFanins
.
pArray
[
1
].
nLats
=
nLats
;
}
static
inline
void
Abc_ObjAddFaninL
(
Abc_Obj_t
*
pObj
,
int
i
,
int
nLats
)
{
pObj
->
vFanins
.
pArray
[
i
].
nLats
+=
nLats
;
}
static
inline
void
Abc_ObjAddFaninL0
(
Abc_Obj_t
*
pObj
,
int
nLats
)
{
pObj
->
vFanins
.
pArray
[
0
].
nLats
+=
nLats
;
}
static
inline
void
Abc_ObjAddFaninL1
(
Abc_Obj_t
*
pObj
,
int
nLats
)
{
pObj
->
vFanins
.
pArray
[
1
].
nLats
+=
nLats
;
}
static
inline
int
Abc_ObjFanoutL
(
Abc_Obj_t
*
pObj
,
Abc_Obj_t
*
pFanout
)
{
return
Abc_ObjFaninL
(
pFanout
,
Abc_ObjFanoutEdgeNum
(
pObj
,
pFanout
)
);
}
static
inline
void
Abc_ObjSetFanoutL
(
Abc_Obj_t
*
pObj
,
Abc_Obj_t
*
pFanout
,
int
nLats
)
{
Abc_ObjSetFaninL
(
pFanout
,
Abc_ObjFanoutEdgeNum
(
pObj
,
pFanout
),
nLats
);
}
static
inline
void
Abc_ObjAddFanoutL
(
Abc_Obj_t
*
pObj
,
Abc_Obj_t
*
pFanout
,
int
nLats
)
{
Abc_ObjAddFaninL
(
pFanout
,
Abc_ObjFanoutEdgeNum
(
pObj
,
pFanout
),
nLats
);
}
// checking the node type
static
inline
bool
Abc_NodeIsAigAnd
(
Abc_Obj_t
*
pNode
)
{
assert
(
Abc_NtkHasAig
(
pNode
->
pNtk
));
return
Abc_ObjFaninNum
(
pNode
)
==
2
;
}
...
...
src/base/abc/abcFanio.c
View file @
08d2b310
...
...
@@ -19,6 +19,7 @@
***********************************************************************/
#include "abc.h"
#include "seqInt.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
...
...
@@ -146,14 +147,13 @@ void Abc_ObjPatchFanin( Abc_Obj_t * pObj, Abc_Obj_t * pFaninOld, Abc_Obj_t * pFa
}
// remember the attributes of the old fanin
fCompl
=
Abc_ObjFaninC
(
pObj
,
iFanin
);
nLats
=
Abc_ObjFaninL
(
pObj
,
iFanin
);
// replace the old fanin entry by the new fanin entry (removes attributes)
Vec_FanWriteEntry
(
&
pObj
->
vFanins
,
iFanin
,
Vec_Int2Fan
(
pFaninNewR
->
Id
)
);
// set the attributes of the new fanin
if
(
fCompl
^
Abc_ObjIsComplement
(
pFaninNew
)
)
Abc_ObjSetFaninC
(
pObj
,
iFanin
);
if
(
nLats
)
Abc
_ObjSetFaninL
(
pObj
,
iFanin
,
nLats
);
if
(
Abc_NtkIsSeq
(
pObj
->
pNtk
)
&&
(
nLats
=
Seq_ObjFaninL
(
pObj
,
iFanin
))
)
Seq
_ObjSetFaninL
(
pObj
,
iFanin
,
nLats
);
// update the fanout of the fanin
if
(
!
Vec_FanDeleteEntry
(
&
pFaninOld
->
vFanouts
,
pObj
->
Id
)
)
{
...
...
src/base/abc/abcNtk.c
View file @
08d2b310
...
...
@@ -22,7 +22,7 @@
#include "abcInt.h"
#include "main.h"
#include "mio.h"
#include "seq.h"
#include "seq
Int
.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
...
...
@@ -322,7 +322,7 @@ Abc_Ntk_t * Abc_NtkDup( Abc_Ntk_t * pNtk )
Abc_ObjAddFanin
(
pObj
->
pCopy
,
pFanin
->
pCopy
);
if
(
Abc_ObjFaninC
(
pObj
,
k
)
)
Abc_ObjSetFaninC
(
pObj
->
pCopy
,
k
);
if
(
Abc_ObjFaninL
(
pObj
,
k
)
>
0
)
if
(
Seq_ObjFaninL
(
pObj
,
k
)
)
Seq_NodeDupLats
(
pObj
->
pCopy
,
pObj
,
k
);
}
}
...
...
src/base/abci/abc.c
View file @
08d2b310
...
...
@@ -901,7 +901,7 @@ int Abc_CommandPrintKMap( Abc_Frame_t * pAbc, int argc, char ** argv )
if
(
!
Abc_NtkIsBddLogic
(
pNtk
)
)
{
fprintf
(
pErr
,
"Visualizing
BDDs can only be done for logic BDD
networks (run
\"
bdd
\"
).
\n
"
);
fprintf
(
pErr
,
"Visualizing
Karnaugh map works for BDD logic
networks (run
\"
bdd
\"
).
\n
"
);
return
1
;
}
if
(
argc
>
util_optind
+
1
)
...
...
@@ -1388,6 +1388,11 @@ int Abc_CommandBalance( Abc_Frame_t * pAbc, int argc, char ** argv )
fprintf
(
pErr
,
"Empty network.
\n
"
);
return
1
;
}
if
(
Abc_NtkIsSeq
(
pNtk
)
)
{
fprintf
(
pErr
,
"Balancing cannot be applied to a sequential AIG.
\n
"
);
return
1
;
}
// get the new network
if
(
Abc_NtkIsStrash
(
pNtk
)
)
...
...
@@ -2731,7 +2736,7 @@ int Abc_CommandExtSeqDcs( Abc_Frame_t * pAbc, int argc, char ** argv )
}
if
(
!
Abc_NtkIsStrash
(
pNtk
)
)
{
fprintf
(
stdout
,
"
This command
works only for AIGs (run
\"
strash
\"
).
\n
"
);
fprintf
(
stdout
,
"
Extracting sequential don't-cares
works only for AIGs (run
\"
strash
\"
).
\n
"
);
return
0
;
}
if
(
!
Abc_NtkExtractSequentialDcs
(
pNtk
,
fVerbose
)
)
...
...
@@ -4279,7 +4284,7 @@ int Abc_CommandSuperChoice( Abc_Frame_t * pAbc, int argc, char ** argv )
if
(
!
Abc_NtkIsStrash
(
pNtk
)
)
{
fprintf
(
pErr
,
"
W
orks only for the AIG representation (run
\"
strash
\"
).
\n
"
);
fprintf
(
pErr
,
"
Superchoicing w
orks only for the AIG representation (run
\"
strash
\"
).
\n
"
);
return
1
;
}
...
...
@@ -4736,7 +4741,7 @@ int Abc_CommandSeq( Abc_Frame_t * pAbc, int argc, char ** argv )
{
FILE
*
pOut
,
*
pErr
;
Abc_Ntk_t
*
pNtk
,
*
pNtkRes
;
int
c
;
int
c
,
nLoops
;
pNtk
=
Abc_FrameReadNet
(
pAbc
);
pOut
=
Abc_FrameReadOut
(
pAbc
);
...
...
@@ -4769,14 +4774,14 @@ int Abc_CommandSeq( Abc_Frame_t * pAbc, int argc, char ** argv )
if
(
!
Abc_NtkIsStrash
(
pNtk
)
)
{
fprintf
(
pErr
,
"
Works only for AIG
(run
\"
strash
\"
).
\n
"
);
fprintf
(
pErr
,
"
Conversion to sequential AIG works only for combinational AIGs
(run
\"
strash
\"
).
\n
"
);
return
1
;
}
if
(
Abc_NtkCountSelfFeedLatches
(
pNtk
)
)
if
(
nLoops
=
Abc_NtkCountSelfFeedLatches
(
pNtk
)
)
{
fprintf
(
pErr
,
"
Sequential AIG cannot be created for designs with self-feeding latches.
\n
"
);
return
1
;
fprintf
(
pErr
,
"
Cannot create sequential AIG because the network contains %d self-feeding latches.
\n
"
,
nLoops
);
return
0
;
}
// get the new network
...
...
@@ -4844,7 +4849,7 @@ int Abc_CommandUnseq( Abc_Frame_t * pAbc, int argc, char ** argv )
if
(
!
Abc_NtkIsSeq
(
pNtk
)
)
{
fprintf
(
pErr
,
"
W
orks only for sequential AIG (run
\"
seq
\"
).
\n
"
);
fprintf
(
pErr
,
"
Conversion to combinational AIG w
orks only for sequential AIG (run
\"
seq
\"
).
\n
"
);
return
1
;
}
...
...
@@ -4891,6 +4896,7 @@ int Abc_CommandRetime( Abc_Frame_t * pAbc, int argc, char ** argv )
int
fBackward
;
int
fInitial
;
int
fVerbose
;
int
nLoops
;
pNtk
=
Abc_FrameReadNet
(
pAbc
);
pOut
=
Abc_FrameReadOut
(
pAbc
);
...
...
@@ -4933,8 +4939,14 @@ int Abc_CommandRetime( Abc_Frame_t * pAbc, int argc, char ** argv )
if
(
!
Abc_NtkIsSeq
(
pNtk
)
)
{
fprintf
(
pErr
,
"Works only for sequential AIG (run
\"
seq
\"
).
\n
"
);
return
1
;
fprintf
(
pErr
,
"Retiming works only for sequential AIG (run
\"
seq
\"
).
\n
"
);
return
0
;
}
if
(
nLoops
=
Abc_NtkCountSelfFeedLatches
(
pNtk
)
)
{
fprintf
(
pErr
,
"Cannot retime because the network contains %d self-feeding latches.
\n
"
,
nLoops
);
return
0
;
}
// get the new network
...
...
@@ -4979,7 +4991,7 @@ int Abc_CommandSeqFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
pErr
=
Abc_FrameReadErr
(
pAbc
);
// set defaults
fVerbose
=
1
;
fVerbose
=
0
;
util_getopt_reset
();
while
(
(
c
=
util_getopt
(
argc
,
argv
,
"vh"
)
)
!=
EOF
)
{
...
...
@@ -5003,20 +5015,16 @@ int Abc_CommandSeqFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
if
(
!
Abc_NtkIsSeq
(
pNtk
)
)
{
fprintf
(
pErr
,
"
W
orks only for sequential AIG (run
\"
seq
\"
).
\n
"
);
return
1
;
fprintf
(
pErr
,
"
Sequential FPGA mapping w
orks only for sequential AIG (run
\"
seq
\"
).
\n
"
);
return
0
;
}
// printf( "This command is not yet implemented.\n" );
// return 0;
// get the new network
pNtkRes
=
Seq_NtkFpgaMapRetime
(
pNtk
,
fVerbose
);
if
(
pNtkRes
==
NULL
)
{
fprintf
(
pErr
,
"Sequential FPGA mapping has failed.
\n
"
);
return
1
;
return
0
;
}
// replace the current network
Abc_FrameReplaceCurrentNetwork
(
pAbc
,
pNtkRes
);
...
...
@@ -5078,7 +5086,7 @@ int Abc_CommandSeqMap( Abc_Frame_t * pAbc, int argc, char ** argv )
if
(
!
Abc_NtkIsSeq
(
pNtk
)
)
{
fprintf
(
pErr
,
"
W
orks only for sequential AIG (run
\"
seq
\"
).
\n
"
);
fprintf
(
pErr
,
"
Sequential standard cell mapping w
orks only for sequential AIG (run
\"
seq
\"
).
\n
"
);
return
1
;
}
...
...
@@ -5178,7 +5186,7 @@ int Abc_CommandSeqSweep( Abc_Frame_t * pAbc, int argc, char ** argv )
if
(
Abc_NtkIsSeq
(
pNtk
)
)
{
fprintf
(
pErr
,
"
W
orks only for combinational networks (run
\"
unseq
\"
).
\n
"
);
fprintf
(
pErr
,
"
Sequential sweep w
orks only for combinational networks (run
\"
unseq
\"
).
\n
"
);
return
1
;
}
...
...
@@ -5190,7 +5198,7 @@ int Abc_CommandSeqSweep( Abc_Frame_t * pAbc, int argc, char ** argv )
if
(
!
Abc_NtkIsStrash
(
pNtk
)
)
{
fprintf
(
pErr
,
"
W
orks only for structurally hashed networks (run
\"
strash
\"
).
\n
"
);
fprintf
(
pErr
,
"
Sequential sweep w
orks only for structurally hashed networks (run
\"
strash
\"
).
\n
"
);
return
1
;
}
...
...
src/base/abci/abcCut.c
View file @
08d2b310
...
...
@@ -20,6 +20,7 @@
#include "abc.h"
#include "cut.h"
#include "seqInt.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
...
...
@@ -196,7 +197,10 @@ Cut_Man_t * Abc_NtkSeqCuts( Abc_Ntk_t * pNtk, Cut_Params_t * pParams )
pParams
->
nCutSet
=
Abc_NtkCutSetNodeNum
(
pNtk
);
p
=
Cut_ManStart
(
pParams
);
// set cuts for PIs
// set cuts for the constant node and the PIs
pObj
=
Abc_NtkConst1
(
pNtk
);
if
(
Abc_ObjFanoutNum
(
pObj
)
>
0
)
Cut_NodeSetTriv
(
p
,
pObj
->
Id
);
Abc_NtkForEachPi
(
pNtk
,
pObj
,
i
)
Cut_NodeSetTriv
(
p
,
pObj
->
Id
);
// label the cutset nodes and set their number in the array
...
...
@@ -240,8 +244,11 @@ Cut_Man_t * Abc_NtkSeqCuts( Abc_Ntk_t * pNtk, Cut_Params_t * pParams )
// unlabel the cutset nodes
Abc_SeqForEachCutsetNode
(
pNtk
,
pObj
,
i
)
pObj
->
fMarkC
=
0
;
if
(
pParams
->
fVerbose
)
{
PRT
(
"Total"
,
clock
()
-
clk
);
printf
(
"Converged after %d iterations.
\n
"
,
nIters
);
}
//Abc_NtkPrintCuts( p, pNtk, 1 );
return
p
;
}
...
...
@@ -306,7 +313,7 @@ void Abc_NodeGetCutsSeq( void * p, Abc_Obj_t * pObj, int fTriv )
fTriv
=
pObj
->
fMarkC
?
0
:
fTriv
;
CutSetNum
=
pObj
->
fMarkC
?
(
int
)
pObj
->
pCopy
:
-
1
;
Cut_NodeComputeCutsSeq
(
p
,
pObj
->
Id
,
Abc_ObjFaninId0
(
pObj
),
Abc_ObjFaninId1
(
pObj
),
Abc_ObjFaninC0
(
pObj
),
Abc_ObjFaninC1
(
pObj
),
Abc_ObjFaninL0
(
pObj
),
Abc
_ObjFaninL1
(
pObj
),
fTriv
,
CutSetNum
);
Abc_ObjFaninC0
(
pObj
),
Abc_ObjFaninC1
(
pObj
),
Seq_ObjFaninL0
(
pObj
),
Seq
_ObjFaninL1
(
pObj
),
fTriv
,
CutSetNum
);
}
/**Function*************************************************************
...
...
src/base/io/ioWriteDot.c
View file @
08d2b310
...
...
@@ -19,7 +19,7 @@
***********************************************************************/
#include "io.h"
#include "seq.h"
#include "seq
Int
.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
...
...
@@ -315,7 +315,7 @@ void Io_WriteDot( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesShow,
fprintf
(
pFile
,
"Node%d%s"
,
Abc_ObjFaninId0
(
pNode
),
(
Abc_ObjIsLatch
(
Abc_ObjFanin0
(
pNode
))
?
"_out"
:
""
)
);
fprintf
(
pFile
,
" ["
);
fprintf
(
pFile
,
"style = %s"
,
Abc_ObjFaninC0
(
pNode
)
?
"dotted"
:
"bold"
);
if
(
Abc
_ObjFaninL0
(
pNode
)
>
0
)
if
(
Seq
_ObjFaninL0
(
pNode
)
>
0
)
fprintf
(
pFile
,
", label =
\"
%s
\"
"
,
Seq_ObjFaninGetInitPrintable
(
pNode
,
0
)
);
fprintf
(
pFile
,
"]"
);
fprintf
(
pFile
,
";
\n
"
);
...
...
@@ -330,7 +330,7 @@ void Io_WriteDot( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesShow,
fprintf
(
pFile
,
"Node%d%s"
,
Abc_ObjFaninId1
(
pNode
),
(
Abc_ObjIsLatch
(
Abc_ObjFanin1
(
pNode
))
?
"_out"
:
""
)
);
fprintf
(
pFile
,
" ["
);
fprintf
(
pFile
,
"style = %s"
,
Abc_ObjFaninC1
(
pNode
)
?
"dotted"
:
"bold"
);
if
(
Abc
_ObjFaninL1
(
pNode
)
>
0
)
if
(
Seq
_ObjFaninL1
(
pNode
)
>
0
)
fprintf
(
pFile
,
", label =
\"
%s
\"
"
,
Seq_ObjFaninGetInitPrintable
(
pNode
,
1
)
);
fprintf
(
pFile
,
"]"
);
fprintf
(
pFile
,
";
\n
"
);
...
...
src/base/io/ioWriteList.c
View file @
08d2b310
...
...
@@ -19,6 +19,7 @@
***********************************************************************/
#include "io.h"
#include "seqInt.h"
/*
-------- Original Message --------
...
...
@@ -156,7 +157,7 @@ void Io_WriteListEdge( FILE * pFile, Abc_Obj_t * pObj )
fprintf
(
pFile
,
"%-10s > "
,
Abc_ObjName
(
pObj
)
);
Abc_ObjForEachFanout
(
pObj
,
pFanout
,
i
)
{
fprintf
(
pFile
,
" %s ([%s_to_%s] = %d)"
,
Abc_ObjName
(
pFanout
),
Abc_ObjName
(
pObj
),
Abc_ObjName
(
pFanout
),
Abc
_ObjFanoutL
(
pObj
,
pFanout
)
);
fprintf
(
pFile
,
" %s ([%s_to_%s] = %d)"
,
Abc_ObjName
(
pFanout
),
Abc_ObjName
(
pObj
),
Abc_ObjName
(
pFanout
),
Seq
_ObjFanoutL
(
pObj
,
pFanout
)
);
if
(
i
==
Abc_ObjFanoutNum
(
pObj
)
-
1
)
fprintf
(
pFile
,
"."
);
else
...
...
src/base/seq/seq.h
View file @
08d2b310
...
...
@@ -68,6 +68,7 @@ extern int Seq_NtkLatchNum( Abc_Ntk_t * pNtk );
extern
int
Seq_NtkLatchNumMax
(
Abc_Ntk_t
*
pNtk
);
extern
int
Seq_NtkLatchNumShared
(
Abc_Ntk_t
*
pNtk
);
extern
void
Seq_NtkLatchGetInitNums
(
Abc_Ntk_t
*
pNtk
,
int
*
pInits
);
extern
int
Seq_NtkLatchGetEqualFaninNum
(
Abc_Ntk_t
*
pNtk
);
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
...
...
src/base/seq/seqCreate.c
View file @
08d2b310
...
...
@@ -158,6 +158,7 @@ Abc_Ntk_t * Abc_NtkAigToSeq( Abc_Ntk_t * pNtk )
// set the cutset composed of latch drivers
Abc_NtkAigCutsetCopy
(
pNtk
);
Seq_NtkLatchGetEqualFaninNum
(
pNtkNew
);
// copy EXDC and check correctness
if
(
pNtkNew
->
pExdc
)
...
...
@@ -280,7 +281,7 @@ Abc_Ntk_t * Abc_NtkSeqToLogicSop( Abc_Ntk_t * pNtk )
if
(
Abc_ObjFaninNum
(
pObj
)
==
0
)
continue
;
// create the edge
pFaninNew
=
Abc_NodeSeqToLogic
(
pNtkNew
,
Abc_ObjFanin0
(
pObj
),
Seq_NodeGetRing
(
pObj
,
0
),
Abc
_ObjFaninL0
(
pObj
)
);
pFaninNew
=
Abc_NodeSeqToLogic
(
pNtkNew
,
Abc_ObjFanin0
(
pObj
),
Seq_NodeGetRing
(
pObj
,
0
),
Seq
_ObjFaninL0
(
pObj
)
);
Abc_ObjAddFanin
(
pObj
->
pCopy
,
pFaninNew
);
if
(
Abc_ObjFaninNum
(
pObj
)
==
1
)
{
...
...
@@ -290,7 +291,7 @@ Abc_Ntk_t * Abc_NtkSeqToLogicSop( Abc_Ntk_t * pNtk )
continue
;
}
// create the edge
pFaninNew
=
Abc_NodeSeqToLogic
(
pNtkNew
,
Abc_ObjFanin1
(
pObj
),
Seq_NodeGetRing
(
pObj
,
1
),
Abc
_ObjFaninL1
(
pObj
)
);
pFaninNew
=
Abc_NodeSeqToLogic
(
pNtkNew
,
Abc_ObjFanin1
(
pObj
),
Seq_NodeGetRing
(
pObj
,
1
),
Seq
_ObjFaninL1
(
pObj
)
);
Abc_ObjAddFanin
(
pObj
->
pCopy
,
pFaninNew
);
// the complemented edges are subsumed by the node function
}
...
...
src/base/seq/seqFpgaCore.c
View file @
08d2b310
This diff is collapsed.
Click to expand it.
src/base/seq/seqFpgaIter.c
View file @
08d2b310
...
...
@@ -63,7 +63,7 @@ void Seq_FpgaMappingDelays( Abc_Ntk_t * pNtk, int fVerbose )
pParams
->
fTruth
=
0
;
// compute truth tables
pParams
->
fFilter
=
1
;
// filter dominated cuts
pParams
->
fSeq
=
1
;
// compute sequential cuts
pParams
->
fVerbose
=
0
;
// the verbosiness flag
pParams
->
fVerbose
=
fVerbose
;
// the verbosiness flag
// compute the cuts
clk
=
clock
();
...
...
@@ -84,7 +84,8 @@ p->timeDelay = clock() - clk;
Abc_NtkForEachPo
(
pNtk
,
pObj
,
i
)
Seq_FpgaMappingCollectNode_rec
(
Abc_ObjFanin0
(
pObj
),
p
->
vMapAnds
,
p
->
vMapCuts
);
printf
(
"The number of LUTs = %d.
\n
"
,
Vec_PtrSize
(
p
->
vMapAnds
)
);
if
(
fVerbose
)
printf
(
"The number of LUTs = %d.
\n
"
,
Vec_PtrSize
(
p
->
vMapAnds
)
);
// remove the cuts
Cut_ManStop
(
p
->
pCutMan
);
...
...
@@ -151,7 +152,7 @@ Cut_Cut_t * Seq_FpgaMappingSelectCut( Abc_Obj_t * pAnd )
int
ArrivalCut
,
ArrivalMin
,
i
;
// get the arrival time of the best non-trivial cut
ArrivalMin
=
Seq_NodeGetLValue
(
pAnd
);
// iterate through the cuts and
with
the one with the minimum cost
// iterate through the cuts and
select
the one with the minimum cost
pList
=
Abc_NodeReadCuts
(
Seq_NodeCutMan
(
pAnd
),
pAnd
);
CostMin
=
ABC_INFINITY
;
pCutBest
=
NULL
;
...
...
@@ -231,7 +232,7 @@ int Seq_FpgaNodeUpdateLValue( Abc_Obj_t * pObj, int Fi )
assert
(
Abc_ObjFaninNum
(
pObj
)
>
0
);
if
(
Abc_ObjIsPo
(
pObj
)
)
{
lValueNew
=
Seq_NodeGetLValue
(
Abc_ObjFanin0
(
pObj
))
-
Fi
*
Abc
_ObjFaninL0
(
pObj
);
lValueNew
=
Seq_NodeGetLValue
(
Abc_ObjFanin0
(
pObj
))
-
Fi
*
Seq
_ObjFaninL0
(
pObj
);
return
(
lValueNew
>
Fi
)
?
SEQ_UPDATE_FAIL
:
SEQ_UPDATE_NO
;
}
// get the arrival time of the best non-trivial cut
...
...
src/base/seq/seqInt.h
View file @
08d2b310
...
...
@@ -48,6 +48,7 @@ struct Abc_Seq_t_
// sequential information
Abc_Ntk_t
*
pNtk
;
// the network
int
nSize
;
// the number of entries in all internal arrays
Vec_Int_t
*
vNums
;
// the number of latches on each edge in the AIG
Vec_Ptr_t
*
vInits
;
// the initial states for each edge in the AIG
Extra_MmFixed_t
*
pMmInits
;
// memory manager for latch structures used to remember init states
int
fVerbose
;
// the verbose flag
...
...
@@ -104,18 +105,29 @@ static inline Seq_RetEdge_t Seq_Int2RetEdge( int Num ) { return *((S
static
inline
int
Seq_RetStep2Int
(
Seq_RetStep_t
Val
)
{
return
*
((
int
*
)
&
Val
);
}
static
inline
Seq_RetStep_t
Seq_Int2RetStep
(
int
Num
)
{
return
*
((
Seq_RetStep_t
*
)
&
Num
);
}
// manipulating the number of latches on each edge
static
inline
Vec_Int_t
*
Seq_ObjLNums
(
Abc_Obj_t
*
pObj
)
{
return
((
Abc_Seq_t
*
)
pObj
->
pNtk
->
pManFunc
)
->
vNums
;
}
static
inline
int
Seq_ObjFaninL
(
Abc_Obj_t
*
pObj
,
int
i
)
{
return
Vec_IntEntry
(
Seq_ObjLNums
(
pObj
),
2
*
pObj
->
Id
+
i
);
}
static
inline
int
Seq_ObjFaninL0
(
Abc_Obj_t
*
pObj
)
{
return
Vec_IntEntry
(
Seq_ObjLNums
(
pObj
),
2
*
pObj
->
Id
+
0
);
}
static
inline
int
Seq_ObjFaninL1
(
Abc_Obj_t
*
pObj
)
{
return
Vec_IntEntry
(
Seq_ObjLNums
(
pObj
),
2
*
pObj
->
Id
+
1
);
}
static
inline
void
Seq_ObjSetFaninL
(
Abc_Obj_t
*
pObj
,
int
i
,
int
nLats
)
{
Vec_IntWriteEntry
(
Seq_ObjLNums
(
pObj
),
2
*
pObj
->
Id
+
i
,
nLats
);
}
static
inline
void
Seq_ObjSetFaninL0
(
Abc_Obj_t
*
pObj
,
int
nLats
)
{
Vec_IntWriteEntry
(
Seq_ObjLNums
(
pObj
),
2
*
pObj
->
Id
+
0
,
nLats
);
}
static
inline
void
Seq_ObjSetFaninL1
(
Abc_Obj_t
*
pObj
,
int
nLats
)
{
Vec_IntWriteEntry
(
Seq_ObjLNums
(
pObj
),
2
*
pObj
->
Id
+
1
,
nLats
);
}
static
inline
void
Seq_ObjAddFaninL
(
Abc_Obj_t
*
pObj
,
int
i
,
int
nLats
)
{
Vec_IntAddToEntry
(
Seq_ObjLNums
(
pObj
),
2
*
pObj
->
Id
+
i
,
nLats
);
}
static
inline
void
Seq_ObjAddFaninL0
(
Abc_Obj_t
*
pObj
,
int
nLats
)
{
Vec_IntAddToEntry
(
Seq_ObjLNums
(
pObj
),
2
*
pObj
->
Id
+
0
,
nLats
);
}
static
inline
void
Seq_ObjAddFaninL1
(
Abc_Obj_t
*
pObj
,
int
nLats
)
{
Vec_IntAddToEntry
(
Seq_ObjLNums
(
pObj
),
2
*
pObj
->
Id
+
1
,
nLats
);
}
static
inline
int
Seq_ObjFanoutL
(
Abc_Obj_t
*
pObj
,
Abc_Obj_t
*
pFanout
)
{
return
Seq_ObjFaninL
(
pFanout
,
Abc_ObjFanoutEdgeNum
(
pObj
,
pFanout
)
);
}
static
inline
void
Seq_ObjSetFanoutL
(
Abc_Obj_t
*
pObj
,
Abc_Obj_t
*
pFanout
,
int
nLats
)
{
Seq_ObjSetFaninL
(
pFanout
,
Abc_ObjFanoutEdgeNum
(
pObj
,
pFanout
),
nLats
);
}
static
inline
void
Seq_ObjAddFanoutL
(
Abc_Obj_t
*
pObj
,
Abc_Obj_t
*
pFanout
,
int
nLats
)
{
Seq_ObjAddFaninL
(
pFanout
,
Abc_ObjFanoutEdgeNum
(
pObj
,
pFanout
),
nLats
);
}
static
inline
int
Seq_ObjFaninLMin
(
Abc_Obj_t
*
pObj
)
{
assert
(
Abc_ObjIsNode
(
pObj
)
);
return
ABC_MIN
(
Seq_ObjFaninL0
(
pObj
),
Seq_ObjFaninL1
(
pObj
)
);
}
static
inline
int
Seq_ObjFaninLMax
(
Abc_Obj_t
*
pObj
)
{
assert
(
Abc_ObjIsNode
(
pObj
)
);
return
ABC_MAX
(
Seq_ObjFaninL0
(
pObj
),
Seq_ObjFaninL1
(
pObj
)
);
}
// reading l-values and lags
static
inline
Vec_Int_t
*
Seq_NodeLValues
(
Abc_Obj_t
*
pNode
)
{
return
((
Abc_Seq_t
*
)(
pNode
)
->
pNtk
->
pManFunc
)
->
vLValues
;
}
static
inline
int
Seq_NodeGetLValue
(
Abc_Obj_t
*
pNode
)
{
return
Vec_IntEntry
(
Seq_NodeLValues
(
pNode
),
(
pNode
)
->
Id
);
}
static
inline
void
Seq_NodeSetLValue
(
Abc_Obj_t
*
pNode
,
int
Value
)
{
Vec_IntWriteEntry
(
Seq_NodeLValues
(
pNode
),
(
pNode
)
->
Id
,
Value
);
}
static
inline
int
Seq_NodeComputeLag
(
int
LValue
,
int
Fi
)
{
return
(
LValue
+
1024
*
Fi
)
/
Fi
-
1024
-
(
int
)(
LValue
%
Fi
==
0
);
}
// reading best cuts at each node
static
inline
Cut_Man_t
*
Seq_NodeCutMan
(
Abc_Obj_t
*
pNode
)
{
return
((
Abc_Seq_t
*
)(
pNode
)
->
pNtk
->
pManFunc
)
->
pCutMan
;
}
//static inline Vec_Ptr_t * Seq_NodeCutBests( Abc_Obj_t * pNode ) { return ((Abc_Seq_t *)(pNode)->pNtk->pManFunc)->vBestCuts; }
//static inline Cut_Cut_t * Seq_NodeGetCutBest( Abc_Obj_t * pNode ) { return Vec_PtrEntry( Seq_NodeCutBests(pNode), (pNode)->Id ); }
//static inline void Seq_NodeSetCutBest( Abc_Obj_t * pNode, Cut_Cut_t * pCut ) { Vec_PtrWriteEntry( Seq_NodeCutBests(pNode), (pNode)->Id, pCut ); }
// reading the contents of the lat
static
inline
Abc_InitType_t
Seq_LatInit
(
Seq_Lat_t
*
pLat
)
{
return
((
unsigned
)
pLat
->
pPrev
)
&
3
;
}
static
inline
Seq_Lat_t
*
Seq_LatNext
(
Seq_Lat_t
*
pLat
)
{
return
pLat
->
pNext
;
}
...
...
@@ -127,6 +139,7 @@ static inline void Seq_LatSetNext( Seq_Lat_t * pLat, Seq_Lat_t * pNext
static
inline
void
Seq_LatSetPrev
(
Seq_Lat_t
*
pLat
,
Seq_Lat_t
*
pPrev
)
{
Abc_InitType_t
Init
=
Seq_LatInit
(
pLat
);
pLat
->
pPrev
=
pPrev
;
Seq_LatSetInit
(
pLat
,
Init
);
}
// accessing retiming lags
static
inline
Cut_Man_t
*
Seq_NodeCutMan
(
Abc_Obj_t
*
pNode
)
{
return
((
Abc_Seq_t
*
)(
pNode
)
->
pNtk
->
pManFunc
)
->
pCutMan
;
}
static
inline
Vec_Str_t
*
Seq_NodeLags
(
Abc_Obj_t
*
pNode
)
{
return
((
Abc_Seq_t
*
)(
pNode
)
->
pNtk
->
pManFunc
)
->
vLags
;
}
static
inline
char
Seq_NodeGetLag
(
Abc_Obj_t
*
pNode
)
{
return
Vec_StrEntry
(
Seq_NodeLags
(
pNode
),
(
pNode
)
->
Id
);
}
static
inline
void
Seq_NodeSetLag
(
Abc_Obj_t
*
pNode
,
char
Value
)
{
Vec_StrWriteEntry
(
Seq_NodeLags
(
pNode
),
(
pNode
)
->
Id
,
(
Value
)
);
}
...
...
src/base/seq/seqLatch.c
View file @
08d2b310
...
...
@@ -60,7 +60,7 @@ void Seq_NodeInsertFirst( Abc_Obj_t * pObj, int Edge, Abc_InitType_t Init )
Seq_NodeSetRing
(
pObj
,
Edge
,
pLat
);
// rotate the ring to make pLat the first
}
Seq_LatSetInit
(
pLat
,
Init
);
Abc
_ObjAddFaninL
(
pObj
,
Edge
,
1
);
Seq
_ObjAddFaninL
(
pObj
,
Edge
,
1
);
}
/**Function*************************************************************
...
...
@@ -94,7 +94,7 @@ void Seq_NodeInsertLast( Abc_Obj_t * pObj, int Edge, Abc_InitType_t Init )
Seq_LatSetNext
(
pLat
,
pRing
);
}
Seq_LatSetInit
(
pLat
,
Init
);
Abc
_ObjAddFaninL
(
pObj
,
Edge
,
1
);
Seq
_ObjAddFaninL
(
pObj
,
Edge
,
1
);
}
/**Function*************************************************************
...
...
@@ -126,7 +126,7 @@ Abc_InitType_t Seq_NodeDeleteFirst( Abc_Obj_t * pObj, int Edge )
}
Init
=
Seq_LatInit
(
pLat
);
Seq_NodeRecycleLat
(
pObj
,
pLat
);
Abc
_ObjAddFaninL
(
pObj
,
Edge
,
-
1
);
Seq
_ObjAddFaninL
(
pObj
,
Edge
,
-
1
);
return
Init
;
}
...
...
@@ -158,7 +158,7 @@ Abc_InitType_t Seq_NodeDeleteLast( Abc_Obj_t * pObj, int Edge )
}
Init
=
Seq_LatInit
(
pLat
);
Seq_NodeRecycleLat
(
pObj
,
pLat
);
Abc
_ObjAddFaninL
(
pObj
,
Edge
,
-
1
);
Seq
_ObjAddFaninL
(
pObj
,
Edge
,
-
1
);
return
Init
;
}
...
...
src/base/seq/seqMan.c
View file @
08d2b310
...
...
@@ -51,6 +51,7 @@ Abc_Seq_t * Seq_Create( Abc_Ntk_t * pNtk )
p
->
nSize
=
1000
;
p
->
pMmInits
=
Extra_MmFixedStart
(
sizeof
(
Seq_Lat_t
)
);
// create internal data structures
p
->
vNums
=
Vec_IntStart
(
2
*
p
->
nSize
);
p
->
vInits
=
Vec_PtrStart
(
2
*
p
->
nSize
);
p
->
vLValues
=
Vec_IntStart
(
p
->
nSize
);
p
->
vLags
=
Vec_StrStart
(
p
->
nSize
);
...
...
@@ -73,6 +74,7 @@ void Seq_Resize( Abc_Seq_t * p, int nMaxId )
if
(
p
->
nSize
>
nMaxId
)
return
;
p
->
nSize
=
nMaxId
+
1
;
Vec_IntFill
(
p
->
vNums
,
2
*
p
->
nSize
,
0
);
Vec_PtrFill
(
p
->
vInits
,
2
*
p
->
nSize
,
NULL
);
Vec_IntFill
(
p
->
vLValues
,
p
->
nSize
,
0
);
Vec_StrFill
(
p
->
vLags
,
p
->
nSize
,
0
);
...
...
@@ -97,6 +99,7 @@ void Seq_Delete( Abc_Seq_t * p )
if
(
p
->
vLValues
)
Vec_IntFree
(
p
->
vLValues
);
// the arrival times (L-Values of nodes)
if
(
p
->
vLags
)
Vec_StrFree
(
p
->
vLags
);
// the lags of the mapped nodes
if
(
p
->
vInits
)
Vec_PtrFree
(
p
->
vInits
);
// the initial values of the latches
if
(
p
->
vNums
)
Vec_IntFree
(
p
->
vNums
);
// the numbers of latches
Extra_MmFixedStop
(
p
->
pMmInits
,
0
);
free
(
p
);
}
...
...
src/base/seq/seqRetCore.c
View file @
08d2b310
This diff is collapsed.
Click to expand it.
src/base/seq/seqRetIter.c
View file @
08d2b310
...
...
@@ -78,6 +78,23 @@ void Seq_NtkRetimeDelayLags( Abc_Ntk_t * pNtk, int fVerbose )
NodeLag
=
Seq_NodeComputeLag
(
Seq_NodeGetLValue
(
pNode
),
FiBest
);
Seq_NodeSetLag
(
pNode
,
NodeLag
);
}
/*
{
Abc_Obj_t * pFanin, * pFanout;
pNode = Abc_NtkObj( pNtk, 823 );
printf( "Node %d. Lag = %d. LValue = %d. Latches = (%d,%d) (%d,%d).\n", pNode->Id, Seq_NodeGetLag(pNode), Seq_NodeGetLValue(pNode),
Seq_ObjFaninL0(pNode), Seq_ObjFaninL1(pNode), Seq_ObjFanoutL(pNode, Abc_NtkObj(pNtk, 826)), Seq_ObjFanoutL(pNode, Abc_NtkObj(pNtk, 1210)) );
pFanin = Abc_ObjFanin0( pNode );
printf( "Fanin %d. Lag = %d. LValue = %d. Latches = (%d,%d)\n", pFanin->Id, Seq_NodeGetLag(pFanin), Seq_NodeGetLValue(pFanin),
Seq_ObjFaninL0(pFanin), Seq_ObjFaninL1(pFanin) );
pFanin = Abc_ObjFanin1( pNode );
printf( "Fanin %d. Lag = %d. LValue = %d.\n", pFanin->Id, Seq_NodeGetLag(pFanin), Seq_NodeGetLValue(pFanin) );
Abc_ObjForEachFanout( pNode, pFanout, i )
printf( "Fanout %d. Lag = %d. LValue = %d.\n", pFanout->Id, Seq_NodeGetLag(pFanout), Seq_NodeGetLValue(pFanout) );
Abc_ObjForEachFanout( Abc_ObjFanin0(pNode), pFanout, i )
printf( "Fanout %d. Lag = %d. LValue = %d.\n", pFanout->Id, Seq_NodeGetLag(pFanout), Seq_NodeGetLValue(pFanout) );
}
*/
// print the result
if
(
fVerbose
)
...
...
@@ -135,6 +152,7 @@ int Seq_RetimeForPeriod( Abc_Ntk_t * pNtk, int Fi, int fVerbose )
{
Abc_Seq_t
*
p
=
pNtk
->
pManFunc
;
Abc_Obj_t
*
pObj
;
int
nMaxSteps
=
10
;
int
i
,
c
,
RetValue
,
fChange
,
Counter
;
char
*
pReason
=
""
;
...
...
@@ -149,7 +167,7 @@ int Seq_RetimeForPeriod( Abc_Ntk_t * pNtk, int Fi, int fVerbose )
// update all values iteratively
Counter
=
0
;
for
(
c
=
0
;
c
<
20
;
c
++
)
for
(
c
=
0
;
c
<
nMaxSteps
;
c
++
)
{
fChange
=
0
;
Abc_AigForEachAnd
(
pNtk
,
pObj
,
i
)
...
...
@@ -185,7 +203,7 @@ int Seq_RetimeForPeriod( Abc_Ntk_t * pNtk, int Fi, int fVerbose )
if
(
fChange
==
0
)
break
;
}
if
(
c
==
20
)
if
(
c
==
nMaxSteps
)
{
RetValue
=
SEQ_UPDATE_FAIL
;
pReason
=
"(timeout)"
;
...
...
@@ -222,11 +240,11 @@ int Seq_RetimeNodeUpdateLValue( Abc_Obj_t * pObj, int Fi )
int
lValueNew
,
lValueOld
,
lValue0
,
lValue1
;
assert
(
!
Abc_ObjIsPi
(
pObj
)
);
assert
(
Abc_ObjFaninNum
(
pObj
)
>
0
);
lValue0
=
Seq_NodeGetLValue
(
Abc_ObjFanin0
(
pObj
))
-
Fi
*
Abc
_ObjFaninL0
(
pObj
);
lValue0
=
Seq_NodeGetLValue
(
Abc_ObjFanin0
(
pObj
))
-
Fi
*
Seq
_ObjFaninL0
(
pObj
);
if
(
Abc_ObjIsPo
(
pObj
)
)
return
(
lValue0
>
Fi
)
?
SEQ_UPDATE_FAIL
:
SEQ_UPDATE_NO
;
if
(
Abc_ObjFaninNum
(
pObj
)
==
2
)
lValue1
=
Seq_NodeGetLValue
(
Abc_ObjFanin1
(
pObj
))
-
Fi
*
Abc
_ObjFaninL1
(
pObj
);
lValue1
=
Seq_NodeGetLValue
(
Abc_ObjFanin1
(
pObj
))
-
Fi
*
Seq
_ObjFaninL1
(
pObj
);
else
lValue1
=
-
ABC_INFINITY
;
lValueNew
=
1
+
ABC_MAX
(
lValue0
,
lValue1
);
...
...
src/base/seq/seqShare.c
View file @
08d2b310
...
...
@@ -82,7 +82,7 @@ void Seq_NodeShareFanouts( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes )
// find the number of fanouts having latches of each type
Abc_ObjForEachFanout
(
pNode
,
pFanout
,
i
)
{
if
(
Abc
_ObjFanoutL
(
pNode
,
pFanout
)
==
0
)
if
(
Seq
_ObjFanoutL
(
pNode
,
pFanout
)
==
0
)
continue
;
Type
=
Seq_NodeGetInitLast
(
pFanout
,
Abc_ObjFanoutEdgeNum
(
pNode
,
pFanout
)
);
nLatches
[
Type
]
++
;
...
...
@@ -119,6 +119,7 @@ void Seq_NodeShareFanouts( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes )
***********************************************************************/
void
Seq_NodeShareOne
(
Abc_Obj_t
*
pNode
,
Abc_InitType_t
Init
,
Vec_Ptr_t
*
vNodes
)
{
Vec_Int_t
*
vNums
=
Seq_ObjLNums
(
pNode
);
Vec_Ptr_t
*
vInits
=
Seq_NodeLats
(
pNode
);
Abc_Obj_t
*
pFanout
,
*
pBuffer
;
Abc_InitType_t
Type
,
InitNew
;
...
...
@@ -128,7 +129,7 @@ void Seq_NodeShareOne( Abc_Obj_t * pNode, Abc_InitType_t Init, Vec_Ptr_t * vNode
Vec_PtrClear
(
vNodes
);
Abc_ObjForEachFanout
(
pNode
,
pFanout
,
i
)
{
if
(
Abc
_ObjFanoutL
(
pNode
,
pFanout
)
==
0
)
if
(
Seq
_ObjFanoutL
(
pNode
,
pFanout
)
==
0
)
continue
;
Type
=
Seq_NodeGetInitLast
(
pFanout
,
Abc_ObjFanoutEdgeNum
(
pNode
,
pFanout
)
);
if
(
Type
==
Init
)
...
...
@@ -147,6 +148,11 @@ void Seq_NodeShareOne( Abc_Obj_t * pNode, Abc_InitType_t Init, Vec_Ptr_t * vNode
Vec_PtrGrow
(
vInits
,
2
*
pBuffer
->
Id
+
2
);
for
(
i
=
Vec_PtrSize
(
vInits
);
i
<
2
*
(
int
)
pBuffer
->
Id
+
2
;
i
++
)
Vec_PtrPush
(
vInits
,
NULL
);
// grow storage for numbers of latches
Vec_IntGrow
(
vNums
,
2
*
pBuffer
->
Id
+
2
);
for
(
i
=
Vec_IntSize
(
vNums
);
i
<
2
*
(
int
)
pBuffer
->
Id
+
2
;
i
++
)
Vec_IntPush
(
vNums
,
0
);
// insert the new latch
Seq_NodeInsertFirst
(
pBuffer
,
0
,
InitNew
);
// redirect the fanouts
...
...
src/base/seq/seqUtil.c
View file @
08d2b310
...
...
@@ -48,7 +48,7 @@ int Seq_ObjFanoutLMax( Abc_Obj_t * pObj )
nLatchRes
=
0
;
Abc_ObjForEachFanout
(
pObj
,
pFanout
,
i
)
{
nLatchCur
=
Abc
_ObjFanoutL
(
pObj
,
pFanout
);
nLatchCur
=
Seq
_ObjFanoutL
(
pObj
,
pFanout
);
if
(
nLatchRes
<
nLatchCur
)
nLatchRes
=
nLatchCur
;
}
...
...
@@ -76,7 +76,7 @@ int Seq_ObjFanoutLMin( Abc_Obj_t * pObj )
nLatchRes
=
ABC_INFINITY
;
Abc_ObjForEachFanout
(
pObj
,
pFanout
,
i
)
{
nLatchCur
=
Abc
_ObjFanoutL
(
pObj
,
pFanout
);
nLatchCur
=
Seq
_ObjFanoutL
(
pObj
,
pFanout
);
if
(
nLatchRes
>
nLatchCur
)
nLatchRes
=
nLatchCur
;
}
...
...
@@ -100,7 +100,7 @@ int Seq_ObjFanoutLSum( Abc_Obj_t * pObj )
Abc_Obj_t
*
pFanout
;
int
i
,
nSum
=
0
;
Abc_ObjForEachFanout
(
pObj
,
pFanout
,
i
)
nSum
+=
Abc
_ObjFanoutL
(
pObj
,
pFanout
);
nSum
+=
Seq
_ObjFanoutL
(
pObj
,
pFanout
);
return
nSum
;
}
...
...
@@ -120,7 +120,7 @@ int Seq_ObjFaninLSum( Abc_Obj_t * pObj )
Abc_Obj_t
*
pFanin
;
int
i
,
nSum
=
0
;
Abc_ObjForEachFanin
(
pObj
,
pFanin
,
i
)
nSum
+=
Abc
_ObjFaninL
(
pObj
,
i
);
nSum
+=
Seq
_ObjFaninL
(
pObj
,
i
);
return
nSum
;
}
...
...
@@ -140,7 +140,7 @@ char * Seq_ObjFaninGetInitPrintable( Abc_Obj_t * pObj, int Edge )
static
char
Buffer
[
1000
];
Abc_InitType_t
Init
;
int
nLatches
,
i
;
nLatches
=
Abc
_ObjFaninL
(
pObj
,
Edge
);
nLatches
=
Seq
_ObjFaninL
(
pObj
,
Edge
);
for
(
i
=
0
;
i
<
nLatches
;
i
++
)
{
Init
=
Seq_LatInit
(
Seq_NodeGetLat
(
pObj
,
Edge
,
i
)
);
...
...
@@ -249,13 +249,13 @@ int Seq_NtkLatchNumMax( Abc_Ntk_t * pNtk )
Max
=
0
;
Abc_AigForEachAnd
(
pNtk
,
pObj
,
i
)
{
Cur
=
Abc
_ObjFaninLMax
(
pObj
);
Cur
=
Seq
_ObjFaninLMax
(
pObj
);
if
(
Max
<
Cur
)
Max
=
Cur
;
}
Abc_NtkForEachPo
(
pNtk
,
pObj
,
i
)
{
Cur
=
Abc
_ObjFaninL0
(
pObj
);
Cur
=
Seq
_ObjFaninL0
(
pObj
);
if
(
Max
<
Cur
)
Max
=
Cur
;
}
...
...
@@ -301,7 +301,7 @@ void Seq_ObjLatchGetInitNums( Abc_Obj_t * pObj, int Edge, int * pInits )
{
Abc_InitType_t
Init
;
int
nLatches
,
i
;
nLatches
=
Abc
_ObjFaninL
(
pObj
,
Edge
);
nLatches
=
Seq
_ObjFaninL
(
pObj
,
Edge
);
for
(
i
=
0
;
i
<
nLatches
;
i
++
)
{
Init
=
Seq_NodeGetInitOne
(
pObj
,
Edge
,
i
);
...
...
@@ -338,6 +338,31 @@ void Seq_NtkLatchGetInitNums( Abc_Ntk_t * pNtk, int * pInits )
}
}
/**Function*************************************************************
Synopsis [Report nodes with equal fanins.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int
Seq_NtkLatchGetEqualFaninNum
(
Abc_Ntk_t
*
pNtk
)
{
Abc_Obj_t
*
pObj
;
int
i
,
Counter
;
assert
(
Abc_NtkIsSeq
(
pNtk
)
);
Counter
=
0
;
Abc_AigForEachAnd
(
pNtk
,
pObj
,
i
)
if
(
Abc_ObjFaninId0
(
pObj
)
==
Abc_ObjFaninId1
(
pObj
)
)
Counter
++
;
if
(
Counter
)
printf
(
"The number of nodes with equal fanins = %d.
\n
"
,
Counter
);
return
Counter
;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
...
...
src/map/fpga/fpgaCore.c
View file @
08d2b310
src/misc/vec/vecFan.h
View file @
08d2b310
...
...
@@ -39,8 +39,7 @@
typedef
struct
Abc_Fan_t_
Abc_Fan_t
;
struct
Abc_Fan_t_
// 1 word
{
unsigned
iFan
:
24
;
// the ID of the object
unsigned
nLats
:
7
;
// the number of latches (up to 127)
unsigned
iFan
:
31
;
// the ID of the object
unsigned
fCompl
:
1
;
// the complemented attribute
};
...
...
src/misc/vec/vecInt.h
View file @
08d2b310
...
...
@@ -307,6 +307,23 @@ static inline void Vec_IntWriteEntry( Vec_Int_t * p, int i, int Entry )
SeeAlso []
***********************************************************************/
static
inline
void
Vec_IntAddToEntry
(
Vec_Int_t
*
p
,
int
i
,
int
Addition
)
{
assert
(
i
>=
0
&&
i
<
p
->
nSize
);
p
->
pArray
[
i
]
+=
Addition
;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static
inline
int
Vec_IntEntryLast
(
Vec_Int_t
*
p
)
{
return
p
->
pArray
[
p
->
nSize
-
1
];
...
...
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