Commit 033203b7 by Alan Mishchenko

Improvements to Cba data-structure.

parent 46fbad86
...@@ -35,6 +35,24 @@ ...@@ -35,6 +35,24 @@
ABC_NAMESPACE_HEADER_START ABC_NAMESPACE_HEADER_START
// Verilog keywords
typedef enum {
PRS_VER_NONE = 0, // 0: unused
PRS_VER_INPUT, // 1: input
PRS_VER_OUTPUT, // 2: output
PRS_VER_INOUT, // 3: inout
PRS_VER_WIRE, // 4: wire
PRS_VER_MODULE, // 5: module
PRS_VER_ASSIGN, // 6: assign
PRS_VER_REG, // 7: reg
PRS_VER_ALWAYS, // 8: always
PRS_VER_DEFPARAM, // 9: always
PRS_VER_BEGIN, // 10: begin
PRS_VER_END, // 11: end
PRS_VER_ENDMODULE, // 12: endmodule
PRS_VER_UNKNOWN // 13: unknown
} Cba_VerType_t;
// parser name types // parser name types
typedef enum { typedef enum {
CBA_PRS_NAME = 0, // 0: name/variable CBA_PRS_NAME = 0, // 0: name/variable
...@@ -456,7 +474,8 @@ static inline char * Ptr_TypeToSop( Cba_ObjType_t Type ) ...@@ -456,7 +474,8 @@ static inline char * Ptr_TypeToSop( Cba_ObjType_t Type )
/// FUNCTION DECLARATIONS /// /// FUNCTION DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/*=== cba.c ========================================================*/ /*=== cbaReadVer.c ========================================================*/
extern void Prs_NtkAddVerilogDirectives( Prs_Man_t * p );
ABC_NAMESPACE_HEADER_END ABC_NAMESPACE_HEADER_END
......
...@@ -27,24 +27,6 @@ ABC_NAMESPACE_IMPL_START ...@@ -27,24 +27,6 @@ ABC_NAMESPACE_IMPL_START
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
// Verilog keywords
typedef enum {
PRS_VER_NONE = 0, // 0: unused
PRS_VER_INPUT, // 1: input
PRS_VER_OUTPUT, // 2: output
PRS_VER_INOUT, // 3: inout
PRS_VER_WIRE, // 4: wire
PRS_VER_MODULE, // 5: module
PRS_VER_ASSIGN, // 6: assign
PRS_VER_REG, // 7: reg
PRS_VER_ALWAYS, // 8: always
PRS_VER_DEFPARAM, // 9: always
PRS_VER_BEGIN, // 10: begin
PRS_VER_END, // 11: end
PRS_VER_ENDMODULE, // 12: endmodule
PRS_VER_UNKNOWN // 13: unknown
} Cba_VerType_t;
static const char * s_VerTypes[PRS_VER_UNKNOWN+1] = { static const char * s_VerTypes[PRS_VER_UNKNOWN+1] = {
NULL, // 0: unused NULL, // 0: unused
"input", // 1: input "input", // 1: input
...@@ -62,7 +44,7 @@ static const char * s_VerTypes[PRS_VER_UNKNOWN+1] = { ...@@ -62,7 +44,7 @@ static const char * s_VerTypes[PRS_VER_UNKNOWN+1] = {
NULL // 13: unknown NULL // 13: unknown
}; };
static inline void Prs_NtkAddVerilogDirectives( Prs_Man_t * p ) void Prs_NtkAddVerilogDirectives( Prs_Man_t * p )
{ {
int i; int i;
for ( i = 1; s_VerTypes[i]; i++ ) for ( i = 1; s_VerTypes[i]; i++ )
...@@ -1209,23 +1191,20 @@ void Prs_CreateOutConcat( Cba_Ntk_t * p, int * pSlices, int nSlices ) ...@@ -1209,23 +1191,20 @@ void Prs_CreateOutConcat( Cba_Ntk_t * p, int * pSlices, int nSlices )
int RightId = Cba_NtkRangeRight( p, RangeId ); int RightId = Cba_NtkRangeRight( p, RangeId );
int BotId = Abc_MinInt( LeftId, RightId ); int BotId = Abc_MinInt( LeftId, RightId );
int TopId = Abc_MaxInt( LeftId, RightId ); int TopId = Abc_MaxInt( LeftId, RightId );
int RangeSize = Cba_NtkRangeSize( p, RangeId ); int i, k, iObj, iFon, nParts, Prev, nBits;
int i, k, iObj, iFon, nParts = 0, Prev = -1, nBits;
assert( RangeId > 0 ); assert( RangeId > 0 );
Vec_IntFill( vBits, Abc_MaxInt(LeftId, RightId) + 1, 0 ); Vec_IntFill( vBits, Abc_MaxInt(LeftId, RightId) + 1, 0 );
// fill up with slices // fill up with slices
for ( i = 0; i < nSlices; i++ ) for ( i = 0; i < nSlices; i++ )
{ {
int Name = pSlices[3*i+0];
int Range = pSlices[3*i+1]; int Range = pSlices[3*i+1];
int iFon = pSlices[3*i+2]; int iFon = pSlices[3*i+2];
int Size = Cba_NtkRangeSize( p, Range );
int Left = Cba_NtkRangeLeft( p, Range ); int Left = Cba_NtkRangeLeft( p, Range );
int Right = Cba_NtkRangeRight( p, Range ); int Right = Cba_NtkRangeRight( p, Range );
int Bot = Abc_MinInt( Left, Right ); int Bot = Abc_MinInt( Left, Right );
int Top = Abc_MaxInt( Left, Right ); int Top = Abc_MaxInt( Left, Right );
assert( Name == NameId && iFon > 0 ); assert( NameId == pSlices[3*i+0] && iFon > 0 );
assert( TopId >= Top && Bot >= BotId ); assert( BotId <= Bot && Top <= TopId );
for ( k = Bot; k <= Top; k++ ) for ( k = Bot; k <= Top; k++ )
{ {
assert( Vec_IntEntry(vBits, k) == 0 ); assert( Vec_IntEntry(vBits, k) == 0 );
...@@ -1233,6 +1212,7 @@ void Prs_CreateOutConcat( Cba_Ntk_t * p, int * pSlices, int nSlices ) ...@@ -1233,6 +1212,7 @@ void Prs_CreateOutConcat( Cba_Ntk_t * p, int * pSlices, int nSlices )
} }
} }
// check how many parts we have // check how many parts we have
Prev = -1; nParts = 0;
Vec_IntForEachEntryStartStop( vBits, iFon, i, BotId, TopId+1 ) Vec_IntForEachEntryStartStop( vBits, iFon, i, BotId, TopId+1 )
{ {
if ( Prev != iFon ) if ( Prev != iFon )
......
...@@ -859,7 +859,7 @@ void Cba_ManWriteVerilogNtk( Cba_Ntk_t * p, int fInlineConcat ) ...@@ -859,7 +859,7 @@ void Cba_ManWriteVerilogNtk( Cba_Ntk_t * p, int fInlineConcat )
Cba_NtkForEachPo( p, iObj, i ) Cba_NtkForEachPo( p, iObj, i )
{ {
iFon = Cba_ObjFinFon(p, iObj, 0); iFon = Cba_ObjFinFon(p, iObj, 0);
if ( !iFon || !Cba_FonIsConst(iFon) && Cba_FonName(p, iFon) == Cba_ObjName(p, iObj) ) // already written if ( !iFon || (!Cba_FonIsConst(iFon) && Cba_FonName(p, iFon) == Cba_ObjName(p, iObj)) ) // already written
continue; continue;
Vec_StrPrintStr( vStr, " assign " ); Vec_StrPrintStr( vStr, " assign " );
Vec_StrPrintStr( vStr, Cba_ObjGetName(p, iObj) ); Vec_StrPrintStr( vStr, Cba_ObjGetName(p, iObj) );
......
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