AXI_BUS Project Status
Project File:	RISCV_CPU.xise	Parser Errors:	No Errors
Module Name:	AXI_BUS	Implementation State:	New
Target Device:	xc3s500e-4vq100	Errors:
Product Version:	ISE 14.7	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:		Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated
ISIM Simulator Log	Current	ÖÜÒ» 3ÔÂ 7 15:48:26 2022

Date Generated: 03/08/2022 - 23:08:44