CPU Project Status (01/22/2022 - 12:33:25)
Project File: | RISCV_CPU.xise | Parser Errors: | No Errors
Module Name: | CPU | Implementation State: | Synthesized
Target Device: | xc3s500e-4vq100 | Errors: | X 1 Error (0 new)
Product Version: | ISE 14.7 | Warnings: | No Warnings
Design Goal: | Balanced | Routing Results: |
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: | System Settings | Final Timing Score: |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | ÖÜÁù 1ÔÂ 22 12:35:36 2022 | X 1 Error (0 new) | 0 | 0
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Current | ÖÜÁù 1ÔÂ 22 18:37:43 2022

Date Generated: 03/01/2022 - 08:38:30
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